static inline unsigned int axgbe_get_max_frame(struct axgbe_port *pdata)
{
- return pdata->eth_dev->data->mtu + ETHER_HDR_LEN +
- ETHER_CRC_LEN + VLAN_HLEN;
+ return pdata->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
+ RTE_ETHER_CRC_LEN + VLAN_HLEN;
}
/* query busy bit */
ehfc = 1;
AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
+
+ PMD_DRV_LOG(DEBUG, "flow control %s for RXq%u\n",
+ ehfc ? "enabled" : "disabled", i);
}
/* Set MAC flow control */
/*Calculate and config Flow control threshold*/
axgbe_calculate_flow_control_threshold(pdata);
axgbe_config_flow_control_threshold(pdata);
+
+ PMD_DRV_LOG(DEBUG, "%d Rx hardware queues, %d byte fifo per queue\n",
+ pdata->rx_q_count, q_fifo_size);
}
static void axgbe_config_tx_fifo_size(struct axgbe_port *pdata)
for (i = 0; i < pdata->tx_q_count; i++)
AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, p_fifo);
+
+ PMD_DRV_LOG(DEBUG, "%d Tx hardware queues, %d byte fifo per queue\n",
+ pdata->tx_q_count, q_fifo_size);
}
static void axgbe_config_queue_mapping(struct axgbe_port *pdata)
qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
- for (j = 0; j < qptc; j++)
+ for (j = 0; j < qptc; j++) {
+ PMD_DRV_LOG(DEBUG, "TXq%u mapped to TC%u\n", queue, i);
AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
Q2TCMAP, i);
- if (i < qptc_extra)
+ }
+ if (i < qptc_extra) {
+ PMD_DRV_LOG(DEBUG, "TXq%u mapped to TC%u\n", queue, i);
AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
Q2TCMAP, i);
+ }
}
if (pdata->rss_enable) {
AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
}
+static void axgbe_config_mmc(struct axgbe_port *pdata)
+{
+ struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
+
+ /* Reset stats */
+ memset(stats, 0, sizeof(*stats));
+
+ /* Set counters to reset on read */
+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
+
+ /* Reset the counters */
+ AXGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
+}
+
static int axgbe_init(struct axgbe_port *pdata)
{
int ret;
axgbe_config_flow_control(pdata);
axgbe_config_mac_speed(pdata);
axgbe_config_checksum_offload(pdata);
+ axgbe_config_mmc(pdata);
return 0;
}