/* MDIO port types */
#define AXGMAC_MAX_C22_PORT 3
+/* The max frame size with default MTU */
+#define AXGBE_ETH_MAX_LEN ( \
+ RTE_ETHER_MTU + \
+ RTE_ETHER_HDR_LEN + \
+ RTE_ETHER_CRC_LEN)
+
/* Helper macro for descriptor handling
* Always use AXGBE_GET_DESC_DATA to access the descriptor data
* since the index is free-running and needs to be and-ed
int (*config_tx_flow_control)(struct axgbe_port *);
int (*config_rx_flow_control)(struct axgbe_port *);
+ /* vlan */
+ int (*enable_rx_vlan_stripping)(struct axgbe_port *);
+ int (*disable_rx_vlan_stripping)(struct axgbe_port *);
+ int (*enable_rx_vlan_filtering)(struct axgbe_port *);
+ int (*disable_rx_vlan_filtering)(struct axgbe_port *);
+ int (*update_vlan_hash_table)(struct axgbe_port *);
+
int (*exit)(struct axgbe_port *);
};
unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
unsigned int pps_out_num; /* Number of PPS outputs */
unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
+
+ /* HW Feature Register3 */
+ unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */
+ /* insertion on Tx Enable */
+ unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */
+ /* Filters Enabled */
};
struct axgbe_version_data {
unsigned int uc_hash_mac_addr;
unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
+ /* Filtering support */
+ unsigned long active_vlans[VLAN_TABLE_SIZE];
+
/* For IEEE1588 PTP */
struct rte_timecounter systime_tc;
struct rte_timecounter tx_tstamp;