axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata)
{
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000);
static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
static void axgbe_kx_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000);
static void axgbe_x_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
{
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg |= AXGBE_KR_TRAINING_ENABLE;
+ reg |= AXGBE_KR_TRAINING_START;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
- if (pdata->phy_if.phy_impl.kr_training_post)
- pdata->phy_if.phy_impl.kr_training_post(pdata);
- }
+ PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ if (pdata->phy_if.phy_impl.kr_training_post)
+ pdata->phy_if.phy_impl.kr_training_post(pdata);
return AXGBE_AN_PAGE_RECEIVED;
}
pdata->an_int = 0;
axgbe_an73_clear_interrupts(pdata);
pdata->eth_dev->data->dev_link.link_status =
- ETH_LINK_DOWN;
+ RTE_ETH_LINK_DOWN;
} else if (pdata->an_state == AXGBE_AN_ERROR) {
PMD_DRV_LOG(ERR, "error during auto-negotiation, state=%u\n",
cur_state);
{
int ret;
- axgbe_set_bit(AXGBE_LINK_INIT, &pdata->dev_state);
+ rte_bit_relaxed_set32(AXGBE_LINK_INIT, &pdata->dev_state);
pdata->link_check = rte_get_timer_cycles();
ret = pdata->phy_if.phy_impl.an_config(pdata);
}
/* Disable auto-negotiation interrupt */
- rte_intr_disable(&pdata->pci_dev->intr_handle);
+ rte_intr_disable(pdata->pci_dev->intr_handle);
/* Start auto-negotiation in a supported mode */
if (axgbe_use_mode(pdata, AXGBE_MODE_KR)) {
} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_100)) {
axgbe_set_mode(pdata, AXGBE_MODE_SGMII_100);
} else {
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ rte_intr_enable(pdata->pci_dev->intr_handle);
return -EINVAL;
}
pdata->kx_state = AXGBE_RX_BPA;
/* Re-enable auto-negotiation interrupt */
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ rte_intr_enable(pdata->pci_dev->intr_handle);
axgbe_an37_enable_interrupts(pdata);
axgbe_an_init(pdata);
ret = __axgbe_phy_config_aneg(pdata);
if (ret)
- axgbe_set_bit(AXGBE_LINK_ERR, &pdata->dev_state);
+ rte_bit_relaxed_set32(AXGBE_LINK_ERR, &pdata->dev_state);
else
- axgbe_clear_bit(AXGBE_LINK_ERR, &pdata->dev_state);
+ rte_bit_relaxed_clear32(AXGBE_LINK_ERR, &pdata->dev_state);
pthread_mutex_unlock(&pdata->an_mutex);
unsigned int reg = 0;
unsigned long autoneg_start_time;
- if (axgbe_test_bit(AXGBE_LINK_ERR, &pdata->dev_state)) {
+ if (rte_bit_relaxed_get32(AXGBE_LINK_ERR, &pdata->dev_state)) {
pdata->phy.link = 0;
goto adjust_link;
}
}
}
axgbe_phy_status_result(pdata);
- if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state))
- axgbe_clear_bit(AXGBE_LINK_INIT, &pdata->dev_state);
+ if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state))
+ rte_bit_relaxed_clear32(AXGBE_LINK_INIT,
+ &pdata->dev_state);
} else {
- if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state)) {
+ if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state)) {
axgbe_check_link_timeout(pdata);
if (link_aneg)