#include <rte_time.h>
#include <rte_mempool.h>
#include <rte_mbuf.h>
+#include <rte_vect.h>
static void
axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue)
axgbe_rx_queue_release(rxq);
return -ENOMEM;
}
- rxq->ring_phys_addr = (uint64_t)dma->phys_addr;
+ rxq->ring_phys_addr = (uint64_t)dma->iova;
rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
memset((void *)rxq->desc, 0, size);
/* Allocate software ring */
/* Get the RSS hash */
if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
+ /* Indicate if a Context Descriptor is next */
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
+ mbuf->ol_flags |= PKT_RX_IEEE1588_PTP
+ | PKT_RX_IEEE1588_TMST;
pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
PL) - rxq->crc_len;
/* Mbuf populate */
return -ENOMEM;
}
memset(tz->addr, 0, tsize);
- txq->ring_phys_addr = (uint64_t)tz->phys_addr;
+ txq->ring_phys_addr = (uint64_t)tz->iova;
txq->desc = tz->addr;
txq->queue_id = queue_idx;
txq->port_id = dev->data->port_id;
if (!pdata->tx_queues)
pdata->tx_queues = dev->data->tx_queues;
- if (txq->vector_disable)
+ if (txq->vector_disable ||
+ rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
dev->tx_pkt_burst = &axgbe_xmit_pkts;
else
#ifdef RTE_ARCH_X86
/* Total msg length to transmit */
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
mbuf->pkt_len);
+ /* Timestamp enablement check */
+ if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
+ rte_wmb();
/* Mark it as First and Last Descriptor */
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
}
}
}
+
+int
+axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
+{
+ struct axgbe_rx_queue *rxq = rx_queue;
+ volatile union axgbe_rx_desc *desc;
+ uint16_t idx;
+
+
+ if (unlikely(offset >= rxq->nb_desc))
+ return -EINVAL;
+
+ if (offset >= rxq->nb_desc - rxq->dirty)
+ return RTE_ETH_RX_DESC_UNAVAIL;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ desc = &rxq->desc[idx + offset];
+
+ if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ return RTE_ETH_RX_DESC_DONE;
+
+ return RTE_ETH_RX_DESC_AVAIL;
+}
+
+int
+axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
+{
+ struct axgbe_tx_queue *txq = tx_queue;
+ volatile struct axgbe_tx_desc *desc;
+ uint16_t idx;
+
+
+ if (unlikely(offset >= txq->nb_desc))
+ return -EINVAL;
+
+ if (offset >= txq->nb_desc - txq->dirty)
+ return RTE_ETH_TX_DESC_UNAVAIL;
+
+ idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1);
+ desc = &txq->desc[idx + offset];
+
+ if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
+ return RTE_ETH_TX_DESC_DONE;
+
+ return RTE_ETH_TX_DESC_FULL;
+}