axgbe_rx_queue_release(rxq);
return -ENOMEM;
}
- rxq->ring_phys_addr = (uint64_t)dma->phys_addr;
+ rxq->ring_phys_addr = (uint64_t)dma->iova;
rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
memset((void *)rxq->desc, 0, size);
/* Allocate software ring */
/* Get the RSS hash */
if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
+ /* Indicate if a Context Descriptor is next */
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
+ mbuf->ol_flags |= PKT_RX_IEEE1588_PTP
+ | PKT_RX_IEEE1588_TMST;
pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
PL) - rxq->crc_len;
/* Mbuf populate */
return -ENOMEM;
}
memset(tz->addr, 0, tsize);
- txq->ring_phys_addr = (uint64_t)tz->phys_addr;
+ txq->ring_phys_addr = (uint64_t)tz->iova;
txq->desc = tz->addr;
txq->queue_id = queue_idx;
txq->port_id = dev->data->port_id;
/* Total msg length to transmit */
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
mbuf->pkt_len);
+ /* Timestamp enablement check */
+ if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
+ AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
+ rte_wmb();
/* Mark it as First and Last Descriptor */
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);