bus/dpaa: support shared MAC

[dpdk.git] / drivers / net / axgbe / axgbe_rxtx.c

diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 57e2bbb..da3a982 100644 (file)
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -95,7 +95,7 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
                axgbe_rx_queue_release(rxq);
                return -ENOMEM;
        }
-       rxq->ring_phys_addr = (uint64_t)dma->phys_addr;
+       rxq->ring_phys_addr = (uint64_t)dma->iova;
        rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
        memset((void *)rxq->desc, 0, size);
        /* Allocate software ring */
@@ -530,7 +530,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
                return -ENOMEM;
        }
        memset(tz->addr, 0, tsize);
-       txq->ring_phys_addr = (uint64_t)tz->phys_addr;
+       txq->ring_phys_addr = (uint64_t)tz->iova;
        txq->desc = tz->addr;
        txq->queue_id = queue_idx;
        txq->port_id = dev->data->port_id;
@@ -819,3 +819,49 @@ void axgbe_dev_clear_queues(struct rte_eth_dev *dev)
                }
        }
 }
+
+int
+axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
+{
+       struct axgbe_rx_queue *rxq = rx_queue;
+       volatile union axgbe_rx_desc *desc;
+       uint16_t idx;
+
+
+       if (unlikely(offset >= rxq->nb_desc))
+               return -EINVAL;
+
+       if (offset >= rxq->nb_desc - rxq->dirty)
+               return RTE_ETH_RX_DESC_UNAVAIL;
+
+       idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+       desc = &rxq->desc[idx + offset];
+
+       if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+               return RTE_ETH_RX_DESC_DONE;
+
+       return RTE_ETH_RX_DESC_AVAIL;
+}
+
+int
+axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
+{
+       struct axgbe_tx_queue *txq = tx_queue;
+       volatile struct axgbe_tx_desc *desc;
+       uint16_t idx;
+
+
+       if (unlikely(offset >= txq->nb_desc))
+               return -EINVAL;
+
+       if (offset >= txq->nb_desc - txq->dirty)
+               return RTE_ETH_TX_DESC_UNAVAIL;
+
+       idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1);
+       desc = &txq->desc[idx + offset];
+
+       if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
+               return RTE_ETH_TX_DESC_DONE;
+
+       return RTE_ETH_TX_DESC_FULL;
+}