uint8_t global = FALSE;
uint32_t val;
+ PMD_INIT_FUNC_TRACE(sc);
+
PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
/* mark driver as unloaded in shmem2 */
bnx2x_free_mem(sc);
}
+ /* free the host hardware/software hsi structures */
+ bnx2x_free_hsi_mem(sc);
+
bnx2x_free_fw_stats_mem(sc);
sc->state = BNX2X_STATE_CLOSED;
tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
- tx_start_bd->addr =
- rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
+ tx_start_bd->addr_lo =
+ rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
+ tx_start_bd->addr_hi =
+ rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
tx_start_bd->general_data =
REG_WR(sc, reg_offset, val);
rte_panic("FATAL HW block attention set0 0x%lx",
- (attn & HW_INTERRUT_ASSERT_SET_0));
+ (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
}
}
bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
- union ustorm_eth_rx_producers rx_prods;
+ struct ustorm_eth_rx_producers rx_prods;
uint32_t i;
+ memset(&rx_prods, 0, sizeof(rx_prods));
+
/* update producers */
- rx_prods.prod.bd_prod = rx_bd_prod;
- rx_prods.prod.cqe_prod = rx_cq_prod;
- rx_prods.prod.reserved = 0;
+ rx_prods.bd_prod = rx_bd_prod;
+ rx_prods.cqe_prod = rx_cq_prod;
/*
* Make sure that the BD and SGE data is updated before updating the
wmb();
for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
- REG_WR(sc,
- (fp->ustorm_rx_prods_offset + (i * 4)),
- rx_prods.raw_data[i]);
+ REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
+ ((uint32_t *)&rx_prods)[i]);
}
wmb(); /* keep prod updates ordered */
}
}
+ /* allocate the host hardware/software hsi structures */
+ if (bnx2x_alloc_hsi_mem(sc) != 0) {
+ PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
+ sc->state = BNX2X_STATE_CLOSED;
+ rc = -ENOMEM;
+ goto bnx2x_nic_load_error0;
+ }
+
if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
sc->state = BNX2X_STATE_CLOSED;
rc = -ENOMEM;
bnx2x_nic_load_error0:
bnx2x_free_fw_stats_mem(sc);
+ bnx2x_free_hsi_mem(sc);
bnx2x_free_mem(sc);
return rc;
uint32_t i;
if (IS_PF(sc)) {
-/************************/
-/* DEFAULT STATUS BLOCK */
-/************************/
+ /************************/
+ /* DEFAULT STATUS BLOCK */
+ /************************/
if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
&sc->def_sb_dma, "def_sb",
sc->def_sb =
(struct host_sp_status_block *)sc->def_sb_dma.vaddr;
-/***************/
-/* EVENT QUEUE */
-/***************/
+ /***************/
+ /* EVENT QUEUE */
+ /***************/
if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
&sc->eq_dma, "ev_queue",
sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
-/*************/
-/* SLOW PATH */
-/*************/
+ /*************/
+ /* SLOW PATH */
+ /*************/
if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
&sc->sp_dma, "sp",
sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
-/*******************/
-/* SLOW PATH QUEUE */
-/*******************/
+ /*******************/
+ /* SLOW PATH QUEUE */
+ /*******************/
if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
&sc->spq_dma, "sp_queue",
sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
-/***************************/
-/* FW DECOMPRESSION BUFFER */
-/***************************/
+ /***************************/
+ /* FW DECOMPRESSION BUFFER */
+ /***************************/
if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
"fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
fp->sc = sc;
fp->index = i;
-/*******************/
-/* FP STATUS BLOCK */
-/*******************/
+ /*******************/
+ /* FP STATUS BLOCK */
+ /*******************/
snprintf(buf, sizeof(buf), "fp_%d_sb", i);
if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
for (i = 0; i < sc->num_queues; i++) {
fp = &sc->fp[i];
-/*******************/
-/* FP STATUS BLOCK */
-/*******************/
+ /*******************/
+ /* FP STATUS BLOCK */
+ /*******************/
memset(&fp->status_block, 0, sizeof(fp->status_block));
+ bnx2x_dma_free(&fp->sb_dma);
}
- /***************************/
- /* FW DECOMPRESSION BUFFER */
- /***************************/
+ if (IS_PF(sc)) {
+ /***************************/
+ /* FW DECOMPRESSION BUFFER */
+ /***************************/
- sc->gz_buf = NULL;
+ bnx2x_dma_free(&sc->gz_buf_dma);
+ sc->gz_buf = NULL;
- /*******************/
- /* SLOW PATH QUEUE */
- /*******************/
+ /*******************/
+ /* SLOW PATH QUEUE */
+ /*******************/
- sc->spq = NULL;
+ bnx2x_dma_free(&sc->spq_dma);
+ sc->spq = NULL;
- /*************/
- /* SLOW PATH */
- /*************/
+ /*************/
+ /* SLOW PATH */
+ /*************/
- sc->sp = NULL;
+ bnx2x_dma_free(&sc->sp_dma);
+ sc->sp = NULL;
- /***************/
- /* EVENT QUEUE */
- /***************/
+ /***************/
+ /* EVENT QUEUE */
+ /***************/
- sc->eq = NULL;
+ bnx2x_dma_free(&sc->eq_dma);
+ sc->eq = NULL;
- /************************/
- /* DEFAULT STATUS BLOCK */
- /************************/
-
- sc->def_sb = NULL;
+ /************************/
+ /* DEFAULT STATUS BLOCK */
+ /************************/
+ bnx2x_dma_free(&sc->def_sb_dma);
+ sc->def_sb = NULL;
+ }
}
/*
ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
- REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
if (!CHIP_REV_IS_SLOW(sc)) {
/* enable hw interrupt from doorbell Q */