dma->sc = sc;
if (IS_PF(sc))
- sprintf(mz_name, "bnx2x%d_%s_%lx", SC_ABS_FUNC(sc), msg,
+ sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
rte_get_timer_cycles());
else
- sprintf(mz_name, "bnx2x%d_%s_%lx", sc->pcie_device, msg,
+ sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
rte_get_timer_cycles());
/* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
dma->paddr = (uint64_t) z->phys_addr;
dma->vaddr = z->addr;
- PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%lx", msg, dma->vaddr, dma->paddr);
+ PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
return 0;
}
rte_pktmbuf_free(tx_mbuf);
} else {
PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
- fp->index, TX_BD(pkt_idx, txq));
+ fp->index, (unsigned long)TX_BD(pkt_idx, txq));
}
txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
ramrod_param.rdata_mapping =
- (phys_addr_t) ((void *)BNX2X_SP_MAPPING(sc, rx_mode_rdata)),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
ramrod_param.ramrod_flags = ramrod_flags;
val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
REG_WR(sc, reg_offset, val);
- PMD_DRV_LOG(WARN, "SPIO5 hw attention");
+ PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
/* Fan failure attention */
elink_hw_reset_phy(&sc->link_params);
}
if (unlikely(status)) {
- PMD_DRV_LOG(WARN,
+ PMD_DRV_LOG(WARNING,
"Unexpected fastpath status (0x%08x)!", status);
}
ecore_init_func_obj(sc,
&sc->func_obj,
- BNX2X_SP(sc, func_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING(sc, func_rdata)), BNX2X_SP(sc, func_afex_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING(sc, func_afex_rdata)), &bnx2x_func_sp_drv);
+ BNX2X_SP(sc, func_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
+ BNX2X_SP(sc, func_afex_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
+ &bnx2x_func_sp_drv);
}
static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
cids,
sc->max_cos,
SC_FUNC(sc),
- BNX2X_SP(sc, q_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING
- (sc, q_rdata)),
+ BNX2X_SP(sc, q_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
q_type);
/* configure classification DBs */
fp->cl_id,
idx,
SC_FUNC(sc),
- BNX2X_SP(sc, mac_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING
- (sc,
- mac_rdata)),
+ BNX2X_SP(sc, mac_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
ECORE_FILTER_MAC_PENDING, &sc->sp_state,
ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
}
sc->fp[0].index,
SC_FUNC(sc),
SC_FUNC(sc),
- BNX2X_SP(sc, mcast_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING(sc, mcast_rdata)), ECORE_FILTER_MCAST_PENDING, &sc->sp_state, o_type);
+ BNX2X_SP(sc, mcast_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
+ ECORE_FILTER_MCAST_PENDING,
+ &sc->sp_state, o_type);
/* Setup CAM credit pools */
ecore_init_mac_credit_pool(sc,
sc->fp[0].index,
SC_FUNC(sc),
SC_FUNC(sc),
- BNX2X_SP(sc, rss_rdata), (phys_addr_t) ((void *)
- BNX2X_SP_MAPPING(sc, rss_rdata)), ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state, ECORE_OBJ_TYPE_RX);
+ BNX2X_SP(sc, rss_rdata),
+ (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
+ ECORE_FILTER_RSS_CONF_PENDING,
+ &sc->sp_state, ECORE_OBJ_TYPE_RX);
}
/*
/* If there is no power capability, silently succeed */
if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
- PMD_DRV_LOG(WARN, "No power capability");
+ PMD_DRV_LOG(WARNING, "No power capability");
return 0;
}
/* validate rings have enough entries to cross high thresholds */
if (sc->dropless_fc &&
pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
- PMD_DRV_LOG(WARN, "rx bd ring threshold limit");
+ PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
}
if (sc->dropless_fc &&
pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
- PMD_DRV_LOG(WARN, "rcq ring threshold limit");
+ PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
}
pause->pri_map = 1;
/* rxq setup */
- rxq_init->dscr_map = (phys_addr_t)((void *)rxq->rx_ring_phys_addr);
- rxq_init->rcq_map = (phys_addr_t)((void *)rxq->cq_ring_phys_addr);
- rxq_init->rcq_np_map = (phys_addr_t)((void *)(rxq->cq_ring_phys_addr +
- BNX2X_PAGE_SIZE));
+ rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
+ rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
+ rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
+ BNX2X_PAGE_SIZE);
/*
* This should be a maximum number of data bytes that may be
PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
return;
}
- txq_init->dscr_map = (phys_addr_t)((void *)txq->tx_ring_phys_addr);
+ txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
txq_init->fw_sb_id = fp->fw_sb_id;
{
if ((sc->state != BNX2X_STATE_OPEN) ||
(atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
- PMD_DRV_LOG(WARN, "periodic callout exit (state=0x%x)",
+ PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
sc->state);
return;
}
return ret;
}
- PMD_DRV_LOG(WARN, "PCIe capability NOT FOUND!!!");
+ PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
return 0;
}
/* only E2 and onwards support FLR */
if (CHIP_IS_E1x(sc)) {
- PMD_DRV_LOG(WARN, "FLR not supported in E1H");
+ PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
return -1;
}
/* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
- PMD_DRV_LOG(WARN,
+ PMD_DRV_LOG(WARNING,
"FLR not supported by BC_VER: 0x%08x",
sc->devinfo.bc_ver);
return -1;
if (cos < sc->max_cos) {
sc->prio_to_cos[pri] = cos;
} else {
- PMD_DRV_LOG(WARN,
+ PMD_DRV_LOG(WARNING,
"Invalid COS %d for priority %d "
"(max COS is %d), setting to 0", cos, pri,
(sc->max_cos - 1));
sc->fw_len = st.st_size;
if (sc->fw_len < FW_HEADER_LEN) {
- PMD_DRV_LOG(NOTICE, "Invalid fw size: %lu", sc->fw_len);
+ PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
return;
}
- PMD_DRV_LOG(DEBUG, "fw_len = %lu", sc->fw_len);
+ PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
}
static void
for (i = 0; i < L2_ILT_LINES(sc); i++) {
ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
ilt->lines[cdu_ilt_start + i].page_mapping =
- (phys_addr_t)((void *)sc->context[i].vcxt_dma.paddr);
+ (phys_addr_t)sc->context[i].vcxt_dma.paddr;
ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
}
ecore_ilt_init_op(sc, INITOP_SET);
elink_lfa_reset(&sc->link_params, &sc->link_vars);
} else {
if (!CHIP_REV_IS_SLOW(sc)) {
- PMD_DRV_LOG(WARN,
+ PMD_DRV_LOG(WARNING,
"Bootcode is missing - cannot reset link");
}
}