pci: introduce library and driver

[dpdk.git] / drivers / net / bnx2x / bnx2x.h

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 5cefea4..497bc69 100644 (file)
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -18,6 +18,8 @@
 
 #include <rte_byteorder.h>
 #include <rte_spinlock.h>
+#include <rte_bus_pci.h>
+#include <rte_io.h>
 
 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 #ifndef __LITTLE_ENDIAN
@@ -1146,11 +1148,12 @@ struct bnx2x_softc {
 #define BNX2X_RECOVERY_NIC_LOADING 5
 
        uint32_t rx_mode;
-#define BNX2X_RX_MODE_NONE     0
-#define BNX2X_RX_MODE_NORMAL   1
-#define BNX2X_RX_MODE_ALLMULTI 2
-#define BNX2X_RX_MODE_PROMISC  3
-#define BNX2X_MAX_MULTICAST    64
+#define BNX2X_RX_MODE_NONE             0
+#define BNX2X_RX_MODE_NORMAL           1
+#define BNX2X_RX_MODE_ALLMULTI         2
+#define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
+#define BNX2X_RX_MODE_PROMISC          4
+#define BNX2X_MAX_MULTICAST            64
 
        struct bnx2x_port port;
 
@@ -1419,8 +1422,7 @@ bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
 {
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
                               (unsigned long)offset, val);
-       *((volatile uint8_t*)
-         ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+       rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
 }
 
 static inline void
@@ -1433,8 +1435,8 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
 #endif
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
                               (unsigned long)offset, val);
-       *((volatile uint16_t*)
-         ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+       rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
+
 }
 
 static inline void
@@ -1448,8 +1450,7 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
 
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
                               (unsigned long)offset, val);
-       *((volatile uint32_t*)
-         ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+       rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
 }
 
 static inline uint8_t
@@ -1457,8 +1458,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
 {
        uint8_t val;
 
-       val = (uint8_t)(*((volatile uint8_t*)
-                         ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+       val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
                               (unsigned long)offset, val);
 
@@ -1476,8 +1476,7 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
                            (unsigned long)offset);
 #endif
 
-       val = (uint16_t)(*((volatile uint16_t*)
-                          ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+       val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
                               (unsigned long)offset, val);
 
@@ -1495,8 +1494,7 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
                            (unsigned long)offset);
 #endif
 
-       val = (uint32_t)(*((volatile uint32_t*)
-                          ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+       val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
        PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
                               (unsigned long)offset, val);
 
@@ -1528,12 +1526,12 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
 #define REG_RD_DMAE(sc, offset, valp, len32)               \
     do {                                                   \
        (void)bnx2x_read_dmae(sc, offset, len32);                  \
-       (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
+       rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
     } while (0)
 
 #define REG_WR_DMAE(sc, offset, valp, len32)                            \
     do {                                                                \
-       (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4);              \
+       rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4);              \
        (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
     } while (0)
 
@@ -1560,11 +1558,9 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
 #define DPM_TRIGGER_TYPE 0x40
 
 /* Doorbell macro */
-#define BNX2X_DB_WRITE(db_bar, val) \
-       *((volatile uint32_t *)(db_bar)) = (val)
+#define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
 
-#define BNX2X_DB_READ(db_bar) \
-       *((volatile uint32_t *)(db_bar))
+#define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
 
 #define DOORBELL_ADDR(sc, offset) \
        (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
@@ -1982,7 +1978,7 @@ bnx2x_set_rx_mode(struct bnx2x_softc *sc)
 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
                           void *val, uint8_t size)
 {
-       if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+       if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't read from PCI config space");
                return ENXIO;
        }
@@ -1994,7 +1990,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
 {
        uint16_t val16 = val;
 
-       if (rte_eal_pci_write_config(sc->pci_dev, &val16,
+       if (rte_pci_write_config(sc->pci_dev, &val16,
                                     sizeof(val16), addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't write to PCI config space");
                return ENXIO;
@@ -2006,7 +2002,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
 {
        uint32_t val32 = val;
-       if (rte_eal_pci_write_config(sc->pci_dev, &val32,
+       if (rte_pci_write_config(sc->pci_dev, &val32,
                                     sizeof(val32), addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't write to PCI config space");
                return ENXIO;