#include <rte_byteorder.h>
#include <rte_spinlock.h>
+#include <rte_bus_pci.h>
#include <rte_io.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#define REG_RD_DMAE(sc, offset, valp, len32) \
do { \
(void)bnx2x_read_dmae(sc, offset, len32); \
- (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
+ rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
} while (0)
#define REG_WR_DMAE(sc, offset, valp, len32) \
do { \
- (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
+ rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
(void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
} while (0)
static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
void *val, uint8_t size)
{
- if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+ if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't read from PCI config space");
return ENXIO;
}
{
uint16_t val16 = val;
- if (rte_eal_pci_write_config(sc->pci_dev, &val16,
+ if (rte_pci_write_config(sc->pci_dev, &val16,
sizeof(val16), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;
static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
{
uint32_t val32 = val;
- if (rte_eal_pci_write_config(sc->pci_dev, &val32,
+ if (rte_pci_write_config(sc->pci_dev, &val32,
sizeof(val32), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;