pci: remove eal prefix

[dpdk.git] / drivers / net / bnx2x / bnx2x.h

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index e4979ac..91c5aec 100644 (file)
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -18,6 +18,7 @@
 
 #include <rte_byteorder.h>
 #include <rte_spinlock.h>
+#include <rte_io.h>
 
 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 #ifndef __LITTLE_ENDIAN
@@ -1146,11 +1147,12 @@ struct bnx2x_softc {
 #define BNX2X_RECOVERY_NIC_LOADING 5
 
        uint32_t rx_mode;
-#define BNX2X_RX_MODE_NONE     0
-#define BNX2X_RX_MODE_NORMAL   1
-#define BNX2X_RX_MODE_ALLMULTI 2
-#define BNX2X_RX_MODE_PROMISC  3
-#define BNX2X_MAX_MULTICAST    64
+#define BNX2X_RX_MODE_NONE             0
+#define BNX2X_RX_MODE_NORMAL           1
+#define BNX2X_RX_MODE_ALLMULTI         2
+#define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
+#define BNX2X_RX_MODE_PROMISC          4
+#define BNX2X_MAX_MULTICAST            64
 
        struct bnx2x_port port;
 
@@ -1414,34 +1416,90 @@ struct bnx2x_func_init_params {
 #define BAR1 2
 #define BAR2 4
 
+static inline void
+bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
+{
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+                              (unsigned long)offset, val);
+       rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
+}
+
+static inline void
+bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
+{
 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
-uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);
-uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);
-uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);
+       if ((offset % 2) != 0)
+               PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
+                           (unsigned long)offset);
+#endif
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
+                              (unsigned long)offset, val);
+       rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
 
-void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);
-void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);
-void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);
-#else
-#define bnx2x_reg_write8(sc, offset, val)\
-       *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
+}
 
-#define bnx2x_reg_write16(sc, offset, val)\
-       *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
+static inline void
+bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
+{
+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
+       if ((offset % 4) != 0)
+               PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
+                           (unsigned long)offset);
+#endif
 
-#define bnx2x_reg_write32(sc, offset, val)\
-       *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+                              (unsigned long)offset, val);
+       rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
+}
 
-#define bnx2x_reg_read8(sc, offset)\
-       (*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
+static inline uint8_t
+bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
+{
+       uint8_t val;
 
-#define bnx2x_reg_read16(sc, offset)\
-       (*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
+       val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+                              (unsigned long)offset, val);
 
-#define bnx2x_reg_read32(sc, offset)\
-       (*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
+       return val;
+}
+
+static inline uint16_t
+bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
+{
+       uint16_t val;
+
+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
+       if ((offset % 2) != 0)
+               PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
+                           (unsigned long)offset);
+#endif
+
+       val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+                              (unsigned long)offset, val);
+
+       return val;
+}
+
+static inline uint32_t
+bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
+{
+       uint32_t val;
+
+#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
+       if ((offset % 4) != 0)
+               PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
+                           (unsigned long)offset);
 #endif
 
+       val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
+       PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+                              (unsigned long)offset, val);
+
+       return val;
+}
+
 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
 
 #define REG_RD8(sc, offset)  bnx2x_reg_read8(sc, (offset))
@@ -1499,11 +1557,9 @@ void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);
 #define DPM_TRIGGER_TYPE 0x40
 
 /* Doorbell macro */
-#define BNX2X_DB_WRITE(db_bar, val) \
-       *((volatile uint32_t *)(db_bar)) = (val)
+#define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
 
-#define BNX2X_DB_READ(db_bar) \
-       *((volatile uint32_t *)(db_bar))
+#define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
 
 #define DOORBELL_ADDR(sc, offset) \
        (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
@@ -1921,7 +1977,7 @@ bnx2x_set_rx_mode(struct bnx2x_softc *sc)
 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
                           void *val, uint8_t size)
 {
-       if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+       if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't read from PCI config space");
                return ENXIO;
        }
@@ -1933,7 +1989,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
 {
        uint16_t val16 = val;
 
-       if (rte_eal_pci_write_config(sc->pci_dev, &val16,
+       if (rte_pci_write_config(sc->pci_dev, &val16,
                                     sizeof(val16), addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't write to PCI config space");
                return ENXIO;
@@ -1945,7 +2001,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
 {
        uint32_t val32 = val;
-       if (rte_eal_pci_write_config(sc->pci_dev, &val32,
+       if (rte_pci_write_config(sc->pci_dev, &val32,
                                     sizeof(val32), addr) <= 0) {
                PMD_DRV_LOG(ERR, "Can't write to PCI config space");
                return ENXIO;