#include <rte_bus_pci.h>
#include <rte_io.h>
-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
-#ifndef __LITTLE_ENDIAN
-#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
-#endif
-#undef __BIG_ENDIAN
-#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __BIG_ENDIAN RTE_BIG_ENDIAN
-#endif
-#undef __LITTLE_ENDIAN
-#endif
-
+#include "bnx2x_osal.h"
#include "bnx2x_ethdev.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
#include "elink.h"
-#ifndef __FreeBSD__
+#ifndef RTE_EXEC_ENV_FREEBSD
#include <linux/pci_regs.h>
#define PCIY_PMG PCI_CAP_ID_PM
#define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
#define IFM_10G_T 26 /* 10GBase-T - RJ45 */
-#ifndef __FreeBSD__
+#ifndef RTE_EXEC_ENV_FREEBSD
#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
#endif
#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#endif
-#ifndef ARRSIZE
-#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#define ARRAY_SIZE(arr) RTE_DIM(arr)
#endif
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define ilog2(x) bnx2x_ilog2(x)
#endif
+#define BNX2X_BC_VER 0x040200
+
#include "ecore_sp.h"
struct bnx2x_device_type {
* Transmit Buffer Descriptor (tx_bd) definitions*
*/
/* NUM_TX_PAGES must be a power of 2. */
+#define NUM_TX_PAGES 16
#define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
#define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
#define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
#define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
-
+#define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2)
#define NEXT_TX_BD(x) \
((((x) & USABLE_TX_BD_PER_PAGE) == \
(USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
/*
* Receive Buffer Descriptor (rx_bd) definitions*
*/
-//#define NUM_RX_PAGES 1
+#define MAX_RX_PAGES 8
#define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
#define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
#define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
#define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
#define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
+#define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2)
#define RX_BD_NEXT_PAGE_DESC_CNT 2
#define NEXT_RX_BD(x) \
#define MIN_RX_AVAIL(sc) \
((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
+#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
+#define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\
+ (uint32_t)MIN_RX_AVAIL(sc)))
+
/*
* dropless fc calculations for RCQs
* Number of RCQs should be as number of buffers in BRB:
rte_iova_t paddr;
void *vaddr;
int nseg;
+ const void *mzone;
char msg[RTE_MEMZONE_NAMESIZE - 6];
};
/* pointer back to parent structure */
struct bnx2x_softc *sc;
+ /* Used to synchronize fastpath Rx access */
+ rte_spinlock_t rx_mtx;
+
/* status block */
struct bnx2x_dma sb_dma;
union bnx2x_host_hc_status_block status_block;
}; /* struct bnx2x_slowpath */
/*
- * Port specifc data structure.
+ * Port specific data structure.
*/
struct bnx2x_port {
/*
* Port Management Function (for 57711E only).
* When this field is set the driver instance is
- * responsible for managing port specifc
+ * responsible for managing port specific
* configurations such as handling link attentions.
*/
uint32_t pmf;
uint32_t phy_addr;
+ /* Used to synchronize phy accesses. */
+ rte_spinlock_t phy_mtx;
+ char phy_mtx_name[32];
+
+#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
+#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
+
/*
* MCP scratchpad address for port specific statistics.
- * The device is responsible for writing statistcss
+ * The device is responsible for writing statistics
* back to the MCP for use with management firmware such
* as UMP/NC-SI.
*/
#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
/* device ids */
+#define CHIP_NUM_57710 0x164e
#define CHIP_NUM_57711 0x164f
#define CHIP_NUM_57711E 0x1650
#define CHIP_NUM_57712 0x1662
#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
+#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
+#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
* already registered for this port (which means that the user wants storage
* services).
* 2. During cnic-related load, to know if offload mode is already configured
- * in the HW or needs to be configrued. Since the transition from nic-mode to
- * offload-mode in HW causes traffic coruption, nic-mode is configured only
+ * in the HW or needs to be configured. Since the transition from nic-mode to
+ * offload-mode in HW causes traffic corruption, nic-mode is configured only
* in ports on which storage services where never requested.
*/
#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
* link parameters twice.
*/
struct bnx2x_link_report_data {
- uint16_t line_speed; /* Effective line speed */
- unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
+ uint16_t line_speed; /* Effective line speed */
+ uint32_t link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
};
enum {
uint16_t addr;
};
+struct ecore_ilt;
+
struct bnx2x_vfdb;
/* Top level device private data structure. */
#define PERIODIC_STOP 0
#define PERIODIC_GO 1
volatile unsigned long periodic_flags;
-
+ rte_atomic32_t scan_fp;
struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
/* slow path */
struct bnx2x_dma sp_dma;
struct bnx2x_slowpath *sp;
- unsigned long sp_state;
+ uint32_t sp_state;
/* slow path queue */
struct bnx2x_dma spq_dma;
uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
int panic;
+ /* Array of Multicast addrs */
+ struct rte_ether_addr mc_addrs[VF_MAX_MULTICAST_PER_VF];
+ /* Multicast mac addresses number */
+ uint16_t mc_addrs_num;
}; /* struct bnx2x_softc */
/* IOCTL sub-commands for edebug and firmware upgrade */
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+#define HW_INTERRUT_ASSERT_SET_0 \
+ (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_1 \
+ (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_2 \
+ (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
+ AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
+ AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+#define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
+ (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
+
+#define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
+ AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
+ AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
+
#define MULTI_MASK 0x7f
#define PFS_PER_PORT(sc) \
#define PCI_PM_D0 1
#define PCI_PM_D3hot 2
-int bnx2x_test_bit(int nr, volatile unsigned long * addr);
-void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
-void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
-int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
int bnx2x_cmpxchg(volatile int *addr, int old, int new);
int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
struct bnx2x_dma *dma, const char *msg, uint32_t align);
-
+void bnx2x_dma_free(struct bnx2x_dma *dma);
uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
{
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
COMMAND_REG_INT_ACK);
- union igu_ack_register igu_ack;
+ union {
+ struct igu_ack_register igu_ack;
+ uint32_t val;
+ } val;
- igu_ack.sb.status_block_index = index;
- igu_ack.sb.sb_id_and_flags =
+ val.igu_ack.status_block_index = index;
+ val.igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
- REG_WR(sc, hc_addr, igu_ack.raw_data);
+ REG_WR(sc, hc_addr, val.val);
/* Make sure that ACK is written */
mb();
int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
-int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);
+void bnx2x_print_device_info(struct bnx2x_softc *sc);
+int bnx2x_intr_legacy(struct bnx2x_softc *sc);
void bnx2x_link_status_update(struct bnx2x_softc *sc);
int bnx2x_complete_sp(struct bnx2x_softc *sc);
int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
bnx2x_vf_set_rx_mode(sc);
}
} else {
- PMD_DRV_LOG(NOTICE, sc, "Card is not ready to change mode");
+ PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode");
}
}