net/i40e: extend VF reset waiting time

[dpdk.git] / drivers / net / bnxt / bnxt.h

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0db6e58..bd2dec4 100644 (file)
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2018 Broadcom
+ * Copyright(c) 2014-2021 Broadcom
  * All rights reserved.
  */
 
@@ -309,6 +309,7 @@ struct rte_flow {
 #define BNXT_PTP_FLAGS_PATH_TX         0x0
 #define BNXT_PTP_FLAGS_PATH_RX         0x1
 #define BNXT_PTP_FLAGS_CURRENT_TIME    0x2
+#define BNXT_PTP_CURRENT_TIME_MASK     0xFFFF00000000ULL
 
 struct bnxt_ptp_cfg {
 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
@@ -358,6 +359,7 @@ struct bnxt_ptp_cfg {
 
        /* On Thor, the Rx timestamp is present in the Rx completion record */
        uint64_t                        rx_timestamp;
+       uint64_t                        current_time;
 };
 
 struct bnxt_coal {
@@ -390,9 +392,17 @@ struct bnxt_coal {
 #define BNXT_MAX_RSS_CTXTS_P5 \
        (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5)
 
-#define BNXT_MAX_TC    8
-#define BNXT_MAX_QUEUE 8
-#define BNXT_MAX_TC_Q  (BNXT_MAX_TC + 1)
+#define BNXT_MAX_QUEUE                 8
+#define BNXT_MAX_TQM_SP_RINGS          1
+#define BNXT_MAX_TQM_FP_LEGACY_RINGS   8
+#define BNXT_MAX_TQM_FP_RINGS          9
+#define BNXT_MAX_TQM_LEGACY_RINGS      \
+       (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS)
+#define BNXT_MAX_TQM_RINGS             \
+       (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
+#define BNXT_BACKING_STORE_CFG_LEGACY_LEN      256
+#define BNXT_BACKING_STORE_CFG_LEN     \
+       sizeof(struct hwrm_func_backing_store_cfg_input)
 #define BNXT_PAGE_SHFT 12
 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
@@ -461,7 +471,7 @@ struct bnxt_ctx_mem_info {
        struct bnxt_ctx_pg_info cq_mem;
        struct bnxt_ctx_pg_info vnic_mem;
        struct bnxt_ctx_pg_info stat_mem;
-       struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
+       struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
 };
 
 struct bnxt_ctx_mem_buf_info {
@@ -587,13 +597,6 @@ struct bnxt_rep_info {
                                     DEV_RX_OFFLOAD_SCATTER | \
                                     DEV_RX_OFFLOAD_RSS_HASH)
 
-#define  MAX_TABLE_SUPPORT 4
-#define  MAX_DIR_SUPPORT   2
-struct bnxt_dmabuf_info {
-       uint32_t entry_num;
-       int      fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT];
-};
-
 #define BNXT_HWRM_SHORT_REQ_LEN                sizeof(struct hwrm_short_input)
 
 struct bnxt_flow_stat_info {
@@ -663,6 +666,12 @@ struct bnxt {
 #define BNXT_TRUFLOW_EN(bp)    ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 #define BNXT_GFID_ENABLED(bp)  ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 
+       uint32_t                        flags2;
+#define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED       BIT(0)
+#define BNXT_FLAGS2_PTP_ALARM_SCHEDULED                BIT(1)
+#define BNXT_P5_PTP_TIMESYNC_ENABLED(bp)       \
+       ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
+
        uint16_t                chip_num;
 #define CHIP_NUM_58818         0xd818
 #define BNXT_CHIP_SR2(bp)      ((bp)->chip_num == CHIP_NUM_58818)
@@ -818,7 +827,6 @@ struct bnxt {
        uint16_t                port_svif;
 
        struct tf               tfp;
-       struct bnxt_dmabuf_info dmabuf;
        struct bnxt_ulp_context *ulp_ctx;
        struct bnxt_flow_stat_info *flow_stat;
        uint16_t                max_num_kflows;
@@ -828,6 +836,7 @@ struct bnxt {
 static
 inline uint16_t bnxt_max_rings(struct bnxt *bp)
 {
+       struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
        uint16_t max_tx_rings = bp->max_tx_rings;
        uint16_t max_rx_rings = bp->max_rx_rings;
        uint16_t max_cp_rings = bp->max_cp_rings;
@@ -845,6 +854,18 @@ inline uint16_t bnxt_max_rings(struct bnxt *bp)
                                       bp->max_stat_ctx / 2U);
        }
 
+       if (BNXT_CHIP_P5(bp)) {
+               /* RSS table size in Thor is 512.
+                * Cap max Rx rings to the same value for RSS.
+                * For non-RSS case cap it to the max VNIC count.
+                */
+               if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
+                       max_rx_rings = RTE_MIN(max_rx_rings,
+                                              BNXT_RSS_TBL_SIZE_P5);
+               else
+                       max_rx_rings = RTE_MIN(max_rx_rings, bp->max_vnics);
+       }
+
        max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings);
        if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp))
                max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp);
@@ -981,9 +1002,7 @@ void bnxt_flow_cnt_alarm_cb(void *arg);
 int bnxt_flow_stats_req(struct bnxt *bp);
 int bnxt_flow_stats_cnt(struct bnxt *bp);
 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
+int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
+                        const struct rte_flow_ops **ops);
 
-int
-bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
-                   enum rte_filter_type filter_type,
-                   enum rte_filter_op filter_op, void *arg);
 #endif