mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
} else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
- req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
- req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
+ req.num_mc_entries = rte_cpu_to_le_32(bp->nb_mc_addr);
+ req.mc_tbl_addr = rte_cpu_to_le_64(bp->mc_list_dma_addr);
}
if (vlan_table) {
if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
uint16_t j = dst_id - 1;
//TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
- if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
+ if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
conf->pool_map[j].pools & (1UL << j)) {
PMD_DRV_LOG(DEBUG,
"Add vlan %u to vmdq pool %u\n",
bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
bp->max_l2_ctx += bp->max_rx_em_flows;
- /* TODO: For now, do not support VMDq/RFS on VFs. */
- if (BNXT_PF(bp)) {
- if (bp->pf->max_vfs)
- bp->max_vnics = 1;
- else
- bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
- } else {
- bp->max_vnics = 1;
- }
+ bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
+ bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
+
if (BNXT_PF(bp)) {
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
+ if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
+ bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
+ PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
+ }
+
+ bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
+ if (bp->tunnel_disable_flag)
+ PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
+ bp->tunnel_disable_flag);
unlock:
HWRM_UNLOCK();
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
+ PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
+ }
+
bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
HWRM_UNLOCK();
HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
- req.ver_maj = RTE_VER_YEAR;
- req.ver_min = RTE_VER_MONTH;
- req.ver_upd = RTE_VER_MINOR;
+ req.ver_maj_8b = RTE_VER_YEAR;
+ req.ver_min_8b = RTE_VER_MONTH;
+ req.ver_upd_8b = RTE_VER_MINOR;
if (BNXT_PF(bp)) {
req.enables |= rte_cpu_to_le_32(
rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
req.async_event_fwd[2] |=
- rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
+ rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
+ ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
else
HWRM_CHECK_RESULT();
- if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
- rc = -EAGAIN;
- goto error;
- }
-
PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
resp->hwrm_fw_rsvd_8b);
- bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
- (resp->hwrm_fw_min_8b << 16) |
- (resp->hwrm_fw_bld_8b << 8) |
+ bp->fw_ver = ((uint32_t)resp->hwrm_fw_maj_8b << 24) |
+ ((uint32_t)resp->hwrm_fw_min_8b << 16) |
+ ((uint32_t)resp->hwrm_fw_bld_8b << 8) |
resp->hwrm_fw_rsvd_8b;
PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
return rc;
}
-int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
+int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
{
int rc;
struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
return 0;
HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
- req.flags = flags;
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
}
}
/* AutoNeg - Advertise speeds specified. */
- if (conf->auto_link_speed_mask &&
+ if ((conf->auto_link_speed_mask || conf->auto_pam4_link_speed_mask) &&
!(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
req.auto_mode =
HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
- req.auto_link_speed_mask =
- conf->auto_link_speed_mask;
- if (conf->auto_pam4_link_speeds) {
+ if (conf->auto_pam4_link_speed_mask) {
enables |=
HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
req.auto_link_pam4_speed_mask =
- conf->auto_pam4_link_speeds;
- } else {
+ rte_cpu_to_le_16(conf->auto_pam4_link_speed_mask);
+ }
+ if (conf->auto_link_speed_mask) {
enables |=
HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
+ req.auto_link_speed_mask =
+ rte_cpu_to_le_16(conf->auto_link_speed_mask);
}
}
if (conf->auto_link_speed &&
link_info->phy_ver[1] = resp->phy_min;
link_info->phy_ver[2] = resp->phy_bld;
link_info->link_signal_mode =
- rte_le_to_cpu_16(resp->active_fec_signal_mode);
+ resp->active_fec_signal_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK;
link_info->force_pam4_link_speed =
rte_le_to_cpu_16(resp->force_pam4_link_speed);
link_info->support_pam4_speeds =
rte_le_to_cpu_16(resp->support_pam4_speeds);
- link_info->auto_pam4_link_speeds =
+ link_info->auto_pam4_link_speed_mask =
rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
link_info->module_status = resp->module_status;
HWRM_UNLOCK();
link_info->support_speeds, link_info->force_link_speed);
PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
link_info->link_signal_mode,
- link_info->auto_pam4_link_speeds,
+ link_info->auto_pam4_link_speed_mask,
link_info->support_pam4_speeds,
link_info->force_pam4_link_speed);
return rc;
struct hwrm_ring_free_input req = {.req_type = 0 };
struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
+ if (ring->fw_ring_id == INVALID_HW_RING_ID)
+ return -EINVAL;
+
HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
req.ring_type = ring_type;
req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ ring->fw_ring_id = INVALID_HW_RING_ID;
if (rc || resp->error_code) {
if (rc == 0 && resp->error_code)
struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
+ /* Don't attempt to re-create the ring group if it is already created */
+ if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
+ return 0;
+
HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
struct hwrm_ring_grp_free_input req = {.req_type = 0 };
struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
+ if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
+ return 0;
+
HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
- if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
return rc;
HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
return rc;
}
-static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
+int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
{
int rc;
struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
+ if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
+ return 0;
+
HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
req.update_period_ms = rte_cpu_to_le_32(0);
struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
+ if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
+ return 0;
+
HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
+ cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
+
return rc;
}
unsigned int i;
struct bnxt_cp_ring_info *cpr;
- for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
+ for (i = 0; i < bp->rx_cp_nr_rings; i++) {
- if (i >= bp->rx_cp_nr_rings) {
- cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
- } else {
- cpr = bp->rx_queues[i]->cp_ring;
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[i].fw_stats_ctx = -1;
- }
- if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
- rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
- cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
- if (rc)
- return rc;
- }
+ cpr = bp->rx_queues[i]->cp_ring;
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[i].fw_stats_ctx = -1;
+ if (cpr == NULL)
+ continue;
+ rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
+ if (rc)
+ return rc;
}
- return 0;
-}
-
-int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
-{
- unsigned int i;
- int rc = 0;
-
- for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
- struct bnxt_tx_queue *txq;
- struct bnxt_rx_queue *rxq;
- struct bnxt_cp_ring_info *cpr;
-
- if (i >= bp->rx_cp_nr_rings) {
- txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
- cpr = txq->cp_ring;
- } else {
- rxq = bp->rx_queues[i];
- cpr = rxq->cp_ring;
- }
-
- rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
+ for (i = 0; i < bp->tx_cp_nr_rings; i++) {
+ cpr = bp->tx_queues[i]->cp_ring;
+ if (cpr == NULL)
+ continue;
+ rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
if (rc)
return rc;
}
- return rc;
+
+ return 0;
}
static int
bnxt_hwrm_ring_free(bp, cp_ring,
HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
INVALID_HW_RING_ID);
- cp_ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
- sizeof(*cpr->cp_desc_ring));
+ memset(cpr->cp_desc_ring, 0,
+ cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
cpr->cp_raw_cons = 0;
}
struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
bnxt_hwrm_ring_free(bp, cp_ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
- INVALID_HW_RING_ID);
- cp_ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
- sizeof(*cpr->cp_desc_ring));
+ HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
+ INVALID_HW_RING_ID);
+ memset(cpr->cp_desc_ring, 0,
+ cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
cpr->cp_raw_cons = 0;
}
void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
{
struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
- struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
- struct bnxt_ring *ring = rxr->rx_ring_struct;
- struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq ? rxq->rx_ring : NULL;
+ struct bnxt_ring *ring = rxr ? rxr->rx_ring_struct : NULL;
+ struct bnxt_cp_ring_info *cpr = rxq ? rxq->cp_ring : NULL;
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
+ if (BNXT_HAS_RING_GRPS(bp))
+ bnxt_hwrm_ring_grp_free(bp, queue_index);
+
+ if (ring != NULL && cpr != NULL)
bnxt_hwrm_ring_free(bp, ring,
HWRM_RING_FREE_INPUT_RING_TYPE_RX,
cpr->cp_ring_struct->fw_ring_id);
- ring->fw_ring_id = INVALID_HW_RING_ID;
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[queue_index].rx_fw_ring_id =
- INVALID_HW_RING_ID;
- }
- ring = rxr->ag_ring_struct;
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
+
+ /* Check agg ring struct explicitly.
+ * bnxt_need_agg_ring() returns the current state of offload flags,
+ * but we may have to deal with agg ring struct before the offload
+ * flags are updated.
+ */
+ if (!bnxt_need_agg_ring(bp->eth_dev) ||
+ (rxr && rxr->ag_ring_struct == NULL))
+ goto no_agg;
+
+ ring = rxr ? rxr->ag_ring_struct : NULL;
+ if (ring != NULL && cpr != NULL) {
bnxt_hwrm_ring_free(bp, ring,
BNXT_CHIP_P5(bp) ?
HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
HWRM_RING_FREE_INPUT_RING_TYPE_RX,
cpr->cp_ring_struct->fw_ring_id);
- if (BNXT_HAS_RING_GRPS(bp))
- bp->grp_info[queue_index].ag_fw_ring_id =
- INVALID_HW_RING_ID;
}
- if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
+
+no_agg:
+ if (cpr != NULL) {
+ bnxt_hwrm_stat_ctx_free(bp, cpr);
bnxt_free_cp_ring(bp, cpr);
+ }
if (BNXT_HAS_RING_GRPS(bp))
bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
{
unsigned int i;
- for (i = 0; i < bp->tx_cp_nr_rings; i++) {
- struct bnxt_tx_queue *txq = bp->tx_queues[i];
- struct bnxt_tx_ring_info *txr = txq->tx_ring;
- struct bnxt_ring *ring = txr->tx_ring_struct;
- struct bnxt_cp_ring_info *cpr = txq->cp_ring;
-
- if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_hwrm_ring_free(bp, ring,
- HWRM_RING_FREE_INPUT_RING_TYPE_TX,
- cpr->cp_ring_struct->fw_ring_id);
- ring->fw_ring_id = INVALID_HW_RING_ID;
- memset(txr->tx_desc_ring, 0,
- txr->tx_ring_struct->ring_size *
- sizeof(*txr->tx_desc_ring));
- memset(txr->tx_buf_ring, 0,
- txr->tx_ring_struct->ring_size *
- sizeof(*txr->tx_buf_ring));
- txr->tx_raw_prod = 0;
- txr->tx_raw_cons = 0;
- }
- if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
- bnxt_free_cp_ring(bp, cpr);
- cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
- }
- }
+ for (i = 0; i < bp->tx_cp_nr_rings; i++)
+ bnxt_free_hwrm_tx_ring(bp, i);
for (i = 0; i < bp->rx_cp_nr_rings; i++)
bnxt_free_hwrm_rx_ring(bp, i);
{
uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
- if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
+ if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
switch (conf_link_speed) {
- case ETH_LINK_SPEED_10M_HD:
- case ETH_LINK_SPEED_100M_HD:
+ case RTE_ETH_LINK_SPEED_10M_HD:
+ case RTE_ETH_LINK_SPEED_100M_HD:
/* FALLTHROUGH */
return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
}
{
uint16_t eth_link_speed = 0;
- if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
- return ETH_LINK_SPEED_AUTONEG;
+ if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
+ return RTE_ETH_LINK_SPEED_AUTONEG;
- switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
- case ETH_LINK_SPEED_100M:
- case ETH_LINK_SPEED_100M_HD:
+ switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
+ case RTE_ETH_LINK_SPEED_100M:
+ case RTE_ETH_LINK_SPEED_100M_HD:
/* FALLTHROUGH */
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
break;
- case ETH_LINK_SPEED_1G:
+ case RTE_ETH_LINK_SPEED_1G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
break;
- case ETH_LINK_SPEED_2_5G:
+ case RTE_ETH_LINK_SPEED_2_5G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
break;
- case ETH_LINK_SPEED_10G:
+ case RTE_ETH_LINK_SPEED_10G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
break;
- case ETH_LINK_SPEED_20G:
+ case RTE_ETH_LINK_SPEED_20G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
break;
- case ETH_LINK_SPEED_25G:
+ case RTE_ETH_LINK_SPEED_25G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
break;
- case ETH_LINK_SPEED_40G:
+ case RTE_ETH_LINK_SPEED_40G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
break;
- case ETH_LINK_SPEED_50G:
+ case RTE_ETH_LINK_SPEED_50G:
eth_link_speed = pam4_link ?
HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
break;
- case ETH_LINK_SPEED_100G:
+ case RTE_ETH_LINK_SPEED_100G:
eth_link_speed = pam4_link ?
HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
break;
- case ETH_LINK_SPEED_200G:
+ case RTE_ETH_LINK_SPEED_200G:
eth_link_speed =
HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
break;
return eth_link_speed;
}
-#define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
- ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
- ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
- ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
- ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
+#define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
+ RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
+ RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
+ RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
+ RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
static int bnxt_validate_link_speed(struct bnxt *bp)
{
uint32_t link_speed_capa;
uint32_t one_speed;
- if (link_speed == ETH_LINK_SPEED_AUTONEG)
+ if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
return 0;
link_speed_capa = bnxt_get_speed_capabilities(bp);
- if (link_speed & ETH_LINK_SPEED_FIXED) {
- one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
+ if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
+ one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
if (one_speed & (one_speed - 1)) {
PMD_DRV_LOG(ERR,
{
uint16_t ret = 0;
- if (link_speed == ETH_LINK_SPEED_AUTONEG) {
+ if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
if (bp->link_info->support_speeds)
return bp->link_info->support_speeds;
link_speed = BNXT_SUPPORTED_SPEEDS;
}
- if (link_speed & ETH_LINK_SPEED_100M)
+ if (link_speed & RTE_ETH_LINK_SPEED_100M)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
- if (link_speed & ETH_LINK_SPEED_100M_HD)
+ if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
- if (link_speed & ETH_LINK_SPEED_1G)
+ if (link_speed & RTE_ETH_LINK_SPEED_1G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
- if (link_speed & ETH_LINK_SPEED_2_5G)
+ if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
- if (link_speed & ETH_LINK_SPEED_10G)
+ if (link_speed & RTE_ETH_LINK_SPEED_10G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
- if (link_speed & ETH_LINK_SPEED_20G)
+ if (link_speed & RTE_ETH_LINK_SPEED_20G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
- if (link_speed & ETH_LINK_SPEED_25G)
+ if (link_speed & RTE_ETH_LINK_SPEED_25G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
- if (link_speed & ETH_LINK_SPEED_40G)
+ if (link_speed & RTE_ETH_LINK_SPEED_40G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
- if (link_speed & ETH_LINK_SPEED_50G)
+ if (link_speed & RTE_ETH_LINK_SPEED_50G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
- if (link_speed & ETH_LINK_SPEED_100G)
+ if (link_speed & RTE_ETH_LINK_SPEED_100G)
ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
- if (link_speed & ETH_LINK_SPEED_200G)
+ if (link_speed & RTE_ETH_LINK_SPEED_200G)
ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
return ret;
}
static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
{
- uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
+ uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
switch (hw_link_speed) {
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
- eth_link_speed = ETH_SPEED_NUM_100M;
+ eth_link_speed = RTE_ETH_SPEED_NUM_100M;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
- eth_link_speed = ETH_SPEED_NUM_1G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_1G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
- eth_link_speed = ETH_SPEED_NUM_2_5G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
- eth_link_speed = ETH_SPEED_NUM_10G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_10G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
- eth_link_speed = ETH_SPEED_NUM_20G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_20G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
- eth_link_speed = ETH_SPEED_NUM_25G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_25G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
- eth_link_speed = ETH_SPEED_NUM_40G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_40G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
- eth_link_speed = ETH_SPEED_NUM_50G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_50G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
- eth_link_speed = ETH_SPEED_NUM_100G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_100G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
- eth_link_speed = ETH_SPEED_NUM_200G;
+ eth_link_speed = RTE_ETH_SPEED_NUM_200G;
break;
case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
default:
static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
{
- uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
+ uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
switch (hw_link_duplex) {
case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
/* FALLTHROUGH */
- eth_link_duplex = ETH_LINK_FULL_DUPLEX;
+ eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
break;
case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
- eth_link_duplex = ETH_LINK_HALF_DUPLEX;
+ eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
break;
default:
PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
link->link_speed =
bnxt_parse_hw_link_speed(link_info->link_speed);
else
- link->link_speed = ETH_SPEED_NUM_NONE;
+ link->link_speed = RTE_ETH_SPEED_NUM_NONE;
link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
link->link_status = link_info->link_up;
link->link_autoneg = link_info->auto_mode ==
HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
- ETH_LINK_FIXED : ETH_LINK_AUTONEG;
+ RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
exit:
return rc;
}
autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
if (BNXT_CHIP_P5(bp) &&
- dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
+ dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
/* 40G is not supported as part of media auto detect.
* The speed should be forced and autoneg disabled
* to configure 40G speed.
/* No auto speeds and no auto_pam4_link. Disable autoneg */
if (bp->link_info->auto_link_speed == 0 &&
bp->link_info->link_signal_mode &&
- bp->link_info->auto_pam4_link_speeds == 0)
+ bp->link_info->auto_pam4_link_speed_mask == 0)
autoneg = 0;
speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
bp->link_info->link_signal_mode);
link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
/* Autoneg can be done only when the FW allows. */
- if (autoneg == 1 && bp->link_info->support_auto_speeds) {
+ if (autoneg == 1 &&
+ (bp->link_info->support_auto_speeds || bp->link_info->support_pam4_auto_speeds)) {
link_req.phy_flags |=
HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
link_req.auto_link_speed_mask =
bnxt_parse_eth_link_speed_mask(bp,
dev_conf->link_speeds);
+ link_req.auto_pam4_link_speed_mask =
+ bp->link_info->auto_pam4_link_speed_mask;
} else {
if (bp->link_info->phy_type ==
HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
else if (bp->link_info->force_pam4_link_speed)
link_req.link_speed =
bp->link_info->force_pam4_link_speed;
- else if (bp->link_info->auto_pam4_link_speeds)
+ else if (bp->link_info->auto_pam4_link_speed_mask)
link_req.link_speed =
- bp->link_info->auto_pam4_link_speeds;
+ bp->link_info->auto_pam4_link_speed_mask;
else if (bp->link_info->support_pam4_speeds)
link_req.link_speed =
bp->link_info->support_pam4_speeds;
* zero. Use the auto_link_speed.
*/
if (bp->link_info->auto_link_speed != 0 &&
- bp->link_info->auto_pam4_link_speeds == 0)
+ bp->link_info->auto_pam4_link_speed_mask == 0)
link_req.link_speed = bp->link_info->auto_link_speed;
}
link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
HWRM_CHECK_RESULT();
- bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
+ bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
svif_info = rte_le_to_cpu_16(resp->svif_info);
if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
}
if (mtu)
- *mtu = rte_le_to_cpu_16(resp->mtu);
+ *mtu = rte_le_to_cpu_16(resp->admin_mtu);
switch (resp->port_partition_type) {
case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
{
struct hwrm_func_qcfg_input req = {0};
struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
+ uint16_t flags;
int rc;
if (!BNXT_VF_IS_TRUSTED(bp))
bp->parent->fid = rte_le_to_cpu_16(resp->fid);
bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
- /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
- if (bp->parent->vnic == 0) {
- PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
- /* Use hard-coded values appropriate for current Wh+ fw. */
- if (bp->parent->fid == 2)
- bp->parent->vnic = 0x100;
- else
- bp->parent->vnic = 1;
+ flags = rte_le_to_cpu_16(resp->flags);
+ /* check for the multi-root support */
+ if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
+ bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
+ PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
}
HWRM_UNLOCK();
uint32_t enables;
int rc;
- enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
+ enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
+ HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
} else if (BNXT_HAS_NQ(bp)) {
enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
- req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
+ req.num_msix = rte_cpu_to_le_16(pf_resc->num_nq_rings);
}
req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
- req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
+ req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
+ req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
- req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
+ req.num_vnics = rte_cpu_to_le_16(pf_resc->num_vnics);
req.fid = rte_cpu_to_le_16(0xffff);
req.enables = rte_cpu_to_le_32(enables);
req->min_rx_rings = req->max_rx_rings;
req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
req->min_l2_ctxs = req->max_l2_ctxs;
- /* TODO: For now, do not support VMDq/RFS on VFs. */
- req->max_vnics = rte_cpu_to_le_16(1);
+ req->max_vnics = rte_cpu_to_le_16(bp->max_vnics / (num_vfs + 1));
req->min_vnics = req->max_vnics;
req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
(num_vfs + 1));
req->min_hw_ring_grps = req->max_hw_ring_grps;
- req->flags =
- rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
+ req->max_msix = rte_cpu_to_le_16(bp->max_nq_rings / (num_vfs + 1));
}
static void
struct hwrm_func_cfg_input *req,
int num_vfs)
{
- req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
+ req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
- req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
- RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
- BNXT_NUM_VLANS);
+ req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
+ RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN *
+ BNXT_NUM_VLANS);
req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
(num_vfs + 1));
bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
+ bp->max_nq_rings -= rte_le_to_cpu_16(resp->alloc_msix);
+ bp->max_vnics -= rte_le_to_cpu_16(resp->alloc_vnics);
HWRM_UNLOCK();
pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
+ pf_resc->num_nq_rings = rte_le_to_cpu_32(resp->alloc_msix);
+ pf_resc->num_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
bp->pf->evb_mode = resp->evb_mode;
HWRM_UNLOCK();
pf_resc->num_rx_rings = bp->max_rx_rings;
pf_resc->num_l2_ctxs = bp->max_l2_ctx;
pf_resc->num_hw_ring_grps = bp->max_ring_grps;
+ pf_resc->num_nq_rings = bp->max_nq_rings;
+ pf_resc->num_vnics = bp->max_vnics;
return;
}
bp->max_l2_ctx % (num_vfs + 1);
pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
bp->max_ring_grps % (num_vfs + 1);
+ pf_resc->num_nq_rings = bp->max_nq_rings / (num_vfs + 1) +
+ bp->max_nq_rings % (num_vfs + 1);
+ pf_resc->num_vnics = bp->max_vnics / (num_vfs + 1) +
+ bp->max_vnics % (num_vfs + 1);
}
int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
int rc;
if (!BNXT_PF(bp)) {
- PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
+ PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
return -EINVAL;
}
bp->max_tx_rings = pf_resc->num_tx_rings;
bp->max_rx_rings = pf_resc->num_rx_rings;
bp->max_ring_grps = pf_resc->num_hw_ring_grps;
+ bp->max_nq_rings = pf_resc->num_nq_rings;
+ bp->max_vnics = pf_resc->num_vnics;
}
static int32_t
bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
- uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
struct bnxt_rx_queue **rxqs = bp->rx_queues;
uint16_t *ring_tbl = vnic->rss_table;
/* Find next active ring. */
for (cnt = 0; cnt < max_rings; cnt++) {
- if (rx_queue_state[k] !=
- RTE_ETH_QUEUE_STATE_STOPPED)
+ if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
break;
if (++k == max_rings)
k = 0;
/* FW returned values are in units of 100msec */
info->driver_polling_freq =
rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
- info->master_func_wait_period =
+ info->primary_func_wait_period =
rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
info->normal_func_wait_period =
rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
- info->master_func_wait_period_after_reset =
+ info->primary_func_wait_period_after_reset =
rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
info->max_bailout_time_after_reset =
rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
return rc;
}
+int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp)
+{
+ struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_cfa_pair_info_input req = {0};
+ int rc = 0;
+
+ if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+ PMD_DRV_LOG(DEBUG,
+ "Not a PF or trusted VF. Command not supported\n");
+ return 0;
+ }
+
+ HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB);
+ snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
+ bp->eth_dev->data->name, rep_bp->vf_id);
+ req.flags =
+ rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+ if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) {
+ HWRM_UNLOCK();
+ return !rc;
+ }
+ HWRM_UNLOCK();
+ return rc;
+}
+
int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
{
struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
return rc;
}
-int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
-{
- struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
- bp->hwrm_cmd_resp_addr;
- struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
- uint32_t flags = 0;
- int rc = 0;
-
- if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
- return 0;
-
- if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
- PMD_DRV_LOG(DEBUG,
- "Not a PF or trusted VF. Command not supported\n");
- return 0;
- }
-
- HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
- rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-
- HWRM_CHECK_RESULT();
- flags = rte_le_to_cpu_32(resp->flags);
- HWRM_UNLOCK();
-
- if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
- bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
- else
- bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
-
- return rc;
-}
-
int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
uint32_t echo_req_data2)
{
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT_SILENT();
-
- if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
- rc = -EAGAIN;
-
HWRM_UNLOCK();
return rc;
return rc;
}
+
+void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
+{
+ struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct bnxt_ring *ring = txr->tx_ring_struct;
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+
+ bnxt_hwrm_ring_free(bp, ring,
+ HWRM_RING_FREE_INPUT_RING_TYPE_TX,
+ cpr->cp_ring_struct->fw_ring_id);
+ txr->tx_raw_prod = 0;
+ txr->tx_raw_cons = 0;
+ memset(txr->tx_desc_ring, 0,
+ txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
+ memset(txr->tx_buf_ring, 0,
+ txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
+
+ bnxt_hwrm_stat_ctx_free(bp, cpr);
+
+ bnxt_free_cp_ring(bp, cpr);
+}
+
+int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
+{
+ struct hwrm_func_cfg_input req = {0};
+ struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc;
+
+ if (!BNXT_PF(bp))
+ return 0;
+
+ HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
+
+ req.fid = rte_cpu_to_le_16(0xffff);
+ req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
+ req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
+int
+bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_vnic_rss_cfg_input req = {0};
+ int nr_ctxs = vnic->num_lb_ctxts;
+ int i, rc = 0;
+
+ for (i = 0; i < nr_ctxs; i++) {
+ HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
+
+ req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+ }
+
+ return rc;
+}
git.droids-corp.org / dpdk.git / blobdiff