net/mlx5: rearrange creation of WQ and CQ object
[dpdk.git] / drivers / net / bnxt / bnxt_hwrm.c
index c1af814..b269526 100644 (file)
@@ -530,6 +530,9 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 
        HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 
+       /* PMD does not support XDP and RoCE */
+       filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
+                       HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
        req.flags = rte_cpu_to_le_32(filter->flags);
 
        enables = filter->enables |
@@ -2264,8 +2267,8 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
                                HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
                                HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
                        HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
-               req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
-               req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
+               req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
+               req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
                req.min_agg_len = rte_cpu_to_le_32(512);
        }
        req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);