bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
bp->max_l2_ctx += bp->max_rx_em_flows;
- /* TODO: For now, do not support VMDq/RFS on VFs. */
- if (BNXT_PF(bp)) {
- if (bp->pf->max_vfs)
- bp->max_vnics = 1;
- else
- bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
- } else {
- bp->max_vnics = 1;
- }
+ bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
+ bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
+
if (BNXT_PF(bp)) {
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
!(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
req.auto_mode =
HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
- req.auto_link_speed_mask =
- conf->auto_link_speed_mask;
- if (conf->auto_pam4_link_speeds) {
+ if (conf->auto_pam4_link_speed_mask &&
+ bp->link_info->link_signal_mode) {
enables |=
HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
req.auto_link_pam4_speed_mask =
- conf->auto_pam4_link_speeds;
+ rte_cpu_to_le_16(conf->auto_pam4_link_speed_mask);
} else {
enables |=
HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
+ req.auto_link_speed_mask =
+ rte_cpu_to_le_16(conf->auto_link_speed_mask);
}
}
if (conf->auto_link_speed &&
rte_le_to_cpu_16(resp->force_pam4_link_speed);
link_info->support_pam4_speeds =
rte_le_to_cpu_16(resp->support_pam4_speeds);
- link_info->auto_pam4_link_speeds =
+ link_info->auto_pam4_link_speed_mask =
rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
link_info->module_status = resp->module_status;
HWRM_UNLOCK();
link_info->support_speeds, link_info->force_link_speed);
PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
link_info->link_signal_mode,
- link_info->auto_pam4_link_speeds,
+ link_info->auto_pam4_link_speed_mask,
link_info->support_pam4_speeds,
link_info->force_pam4_link_speed);
return rc;
/* No auto speeds and no auto_pam4_link. Disable autoneg */
if (bp->link_info->auto_link_speed == 0 &&
bp->link_info->link_signal_mode &&
- bp->link_info->auto_pam4_link_speeds == 0)
+ bp->link_info->auto_pam4_link_speed_mask == 0)
autoneg = 0;
speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
bp->link_info->link_signal_mode);
link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
/* Autoneg can be done only when the FW allows. */
- if (autoneg == 1 && bp->link_info->support_auto_speeds) {
+ if (autoneg == 1 &&
+ (bp->link_info->support_auto_speeds || bp->link_info->support_pam4_auto_speeds)) {
link_req.phy_flags |=
HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
link_req.auto_link_speed_mask =
bnxt_parse_eth_link_speed_mask(bp,
dev_conf->link_speeds);
- link_req.auto_pam4_link_speeds =
- bp->link_info->auto_pam4_link_speeds;
+ link_req.auto_pam4_link_speed_mask =
+ bp->link_info->auto_pam4_link_speed_mask;
} else {
if (bp->link_info->phy_type ==
HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
else if (bp->link_info->force_pam4_link_speed)
link_req.link_speed =
bp->link_info->force_pam4_link_speed;
- else if (bp->link_info->auto_pam4_link_speeds)
+ else if (bp->link_info->auto_pam4_link_speed_mask)
link_req.link_speed =
- bp->link_info->auto_pam4_link_speeds;
+ bp->link_info->auto_pam4_link_speed_mask;
else if (bp->link_info->support_pam4_speeds)
link_req.link_speed =
bp->link_info->support_pam4_speeds;
* zero. Use the auto_link_speed.
*/
if (bp->link_info->auto_link_speed != 0 &&
- bp->link_info->auto_pam4_link_speeds == 0)
+ bp->link_info->auto_pam4_link_speed_mask == 0)
link_req.link_speed = bp->link_info->auto_link_speed;
}
link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
} else if (BNXT_HAS_NQ(bp)) {
enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
- req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
+ req.num_msix = rte_cpu_to_le_16(pf_resc->num_nq_rings);
}
req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
- req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
+ req.num_vnics = rte_cpu_to_le_16(pf_resc->num_vnics);
req.fid = rte_cpu_to_le_16(0xffff);
req.enables = rte_cpu_to_le_32(enables);
req->min_rx_rings = req->max_rx_rings;
req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
req->min_l2_ctxs = req->max_l2_ctxs;
- /* TODO: For now, do not support VMDq/RFS on VFs. */
- req->max_vnics = rte_cpu_to_le_16(1);
+ req->max_vnics = rte_cpu_to_le_16(bp->max_vnics / (num_vfs + 1));
req->min_vnics = req->max_vnics;
req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
(num_vfs + 1));
req->min_hw_ring_grps = req->max_hw_ring_grps;
- req->flags =
- rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
+ req->max_msix = rte_cpu_to_le_16(bp->max_nq_rings / (num_vfs + 1));
}
static void
bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
+ bp->max_nq_rings -= rte_le_to_cpu_16(resp->alloc_msix);
+ bp->max_vnics -= rte_le_to_cpu_16(resp->alloc_vnics);
HWRM_UNLOCK();
pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
+ pf_resc->num_nq_rings = rte_le_to_cpu_32(resp->alloc_msix);
+ pf_resc->num_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
bp->pf->evb_mode = resp->evb_mode;
HWRM_UNLOCK();
pf_resc->num_rx_rings = bp->max_rx_rings;
pf_resc->num_l2_ctxs = bp->max_l2_ctx;
pf_resc->num_hw_ring_grps = bp->max_ring_grps;
+ pf_resc->num_nq_rings = bp->max_nq_rings;
+ pf_resc->num_vnics = bp->max_vnics;
return;
}
bp->max_l2_ctx % (num_vfs + 1);
pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
bp->max_ring_grps % (num_vfs + 1);
+ pf_resc->num_nq_rings = bp->max_nq_rings / (num_vfs + 1) +
+ bp->max_nq_rings % (num_vfs + 1);
+ pf_resc->num_vnics = bp->max_vnics / (num_vfs + 1) +
+ bp->max_vnics % (num_vfs + 1);
}
int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
bp->max_tx_rings = pf_resc->num_tx_rings;
bp->max_rx_rings = pf_resc->num_rx_rings;
bp->max_ring_grps = pf_resc->num_hw_ring_grps;
+ bp->max_nq_rings = pf_resc->num_nq_rings;
+ bp->max_vnics = pf_resc->num_vnics;
}
static int32_t
return rc;
}
-int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
-{
- struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
- bp->hwrm_cmd_resp_addr;
- struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
- uint32_t flags = 0;
- int rc = 0;
-
- if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
- return 0;
-
- if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
- PMD_DRV_LOG(DEBUG,
- "Not a PF or trusted VF. Command not supported\n");
- return 0;
- }
-
- HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
- rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-
- HWRM_CHECK_RESULT();
- flags = rte_le_to_cpu_32(resp->flags);
- HWRM_UNLOCK();
-
- if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
- bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
- else
- bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
-
- return rc;
-}
-
int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
uint32_t echo_req_data2)
{
return rc;
}
+
+int
+bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_vnic_rss_cfg_input req = {0};
+ int nr_ctxs = vnic->num_lb_ctxts;
+ int i, rc = 0;
+
+ for (i = 0; i < nr_ctxs; i++) {
+ HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
+
+ req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
+
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ HWRM_UNLOCK();
+ }
+
+ return rc;
+}