RX_PKT_CMPL_AGG_BUFS_SFT)
/* Number of descriptors to process per inner loop in vector mode. */
-#define RTE_BNXT_DESCS_PER_LOOP 4U
+#define BNXT_RX_DESCS_PER_LOOP_VEC128 4U /* SSE, Neon */
+#define BNXT_RX_DESCS_PER_LOOP_VEC256 8U /* AVX2 */
+
+/* Number of extra Rx mbuf ring entries to allocate for vector mode. */
+#define BNXT_RX_EXTRA_MBUF_ENTRIES \
+ RTE_MAX(BNXT_RX_DESCS_PER_LOOP_VEC128, BNXT_RX_DESCS_PER_LOOP_VEC256)
#define BNXT_OL_FLAGS_TBL_DIM 64
#define BNXT_OL_FLAGS_ERR_TBL_DIM 32
uint16_t rx_raw_prod;
uint16_t ag_raw_prod;
uint16_t rx_cons; /* Needed for representor */
+ uint16_t rx_next_cons;
struct bnxt_db_info rx_db;
struct bnxt_db_info ag_db;
int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
#endif
+#if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
+uint16_t bnxt_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+#endif
void bnxt_set_mark_in_mbuf(struct bnxt *bp,
struct rx_pkt_cmpl_hi *rxcmp1,
struct rte_mbuf *mbuf);
extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
+static inline void bnxt_set_vlan(struct rx_pkt_cmpl_hi *rxcmp1,
+ struct rte_mbuf *mbuf)
+{
+ uint32_t metadata = rte_le_to_cpu_32(rxcmp1->metadata);
+
+ mbuf->vlan_tci = metadata & (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+}
+
/* Stingray2 specific code for RX completion parsing */
#define RX_CMP_VLAN_VALID(rxcmp) \
(((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset & \