cons = raw_cons & (cp_ring_size - 1);
mbcons = (raw_cons / 2) & (rx_ring_size - 1);
- /* Prefetch first four descriptor pairs. */
- rte_prefetch0(&cp_desc_ring[cons + 0]);
- rte_prefetch0(&cp_desc_ring[cons + 4]);
- rte_prefetch0(&cp_desc_ring[cons + 8]);
- rte_prefetch0(&cp_desc_ring[cons + 12]);
+ /* Return immediately if there is not at least one completed packet. */
+ if (!bnxt_cpr_cmp_valid(&cp_desc_ring[cons], raw_cons, cp_ring_size))
+ return 0;
/* Ensure that we do not go past the ends of the rings. */
nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,
_mm256_storeu_si256((void *)&rx_pkts[i + 4], t0);
#endif
- /* Prefetch eight descriptor pairs for next iteration. */
- if (i + BNXT_RX_DESCS_PER_LOOP_VEC256 < nb_pkts) {
- rte_prefetch0(&cp_desc_ring[cons + 16]);
- rte_prefetch0(&cp_desc_ring[cons + 20]);
- rte_prefetch0(&cp_desc_ring[cons + 24]);
- rte_prefetch0(&cp_desc_ring[cons + 28]);
- }
-
/*
* Load eight receive completion descriptors into 256-bit
* registers. Loads are issued in reverse order in order to
cons = RING_CMPL(ring_mask, raw_cons);
txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
- if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
+ if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
break;
nb_tx_pkts += txcmp->opaque;
} while (nb_tx_pkts < ring_mask);
if (nb_tx_pkts) {
- if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)
+ if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
bnxt_tx_cmp_vec_fast(txq, nb_tx_pkts);
else
bnxt_tx_cmp_vec(txq, nb_tx_pkts);