/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2020 Broadcom Inc.
+ * Copyright (c) 2014-2021 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
#define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
#define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
#define HWRM_VNIC_QCAPS UINT32_C(0x4a)
+ /* Updates specific fields in RX VNIC structure */
+ #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
#define HWRM_RING_ALLOC UINT32_C(0x50)
#define HWRM_RING_FREE UINT32_C(0x51)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
+ #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
+ #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
+ #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
#define HWRM_RING_RESET UINT32_C(0x5e)
#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
#define HWRM_RING_GRP_FREE UINT32_C(0x61)
+ #define HWRM_RING_CFG UINT32_C(0x62)
+ #define HWRM_RING_QCFG UINT32_C(0x63)
/* Reserved for future use. */
#define HWRM_RESERVED5 UINT32_C(0x64)
/* Reserved for future use. */
#define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
#define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
#define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
+ #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
+ #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
+ #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
+ #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
#define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
#define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
#define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
#define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
#define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
- #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
+ /* Reserved. */
+ #define HWRM_RESERVED7 UINT32_C(0xba)
+ #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
+ #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
+ #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
+ #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
+ #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
#define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
#define HWRM_FW_ECN_CFG UINT32_C(0xcd)
#define HWRM_FW_ECN_QCFG UINT32_C(0xce)
+ #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
#define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
#define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
/* Tells the fw to collect dsc dump on a given port and lane. */
#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
+ #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
+ #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Experimental - DEPRECATED */
#define HWRM_CFA_TFLIB UINT32_C(0x125)
+ /* Experimental */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
+ /* Experimental */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
#define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
/* Engine CKV - Add a new CKEK used to encrypt keys. */
#define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
/* Queries extended statistics context */
#define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
+ /* Configure SoC packet DMA settings */
+ #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
+ /* Query SoC packet DMA settings */
+ #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
+ /* PTP - Queries configuration of timesync IO pins. */
+ #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
+ /* PTP - Configuration of timesync IO pins. */
+ #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
+ /* PTP - Configuration for disciplining PHC. */
+ #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
+ /* PTP - Queries for PHC timestamps. */
+ #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
+ /* PTP - Extended PTP configuration. */
+ #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
+ /* PTP - Query extended PTP configuration. */
+ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
+ /* The command is used to allocate KTLS crypto key contexts. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
+ /* The is the new API to configure backing stores. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
+ /* The is the new API to query backing store configurations. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
#define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
/* Tells the fw to read the fru memory */
#define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
+ /* Used to provision SoC software images */
+ #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
+ /* Retrieves the SoC status and image provisioning information */
+ #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
+ /* Tells the fw to program the seeprom memory */
+ #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
+ /* Tells the fw to read the seeprom memory */
+ #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
+ /* Tells the fw to get the health of seeprom data */
+ #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
+ /*
+ * The command is used for certificate provisioning to export a
+ * Certificate Signing Request (CSR) from the device.
+ */
+ #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
+ /*
+ * The command is used for certificate provisioning to import a
+ * CA-signed certificate chain to the device.
+ */
+ #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
+ /*
+ * The command is used for certificate provisioning to query the
+ * provisioned state.
+ */
+ #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
+ /*
+ * The command is used to get the hash of the NVM configuration that is
+ * calculated during firmware boot.
+ */
+ #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
+ /* Retrieves the PSOC status and provisioning information. */
+ #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
+ /*
+ * This command allows manufacturing tool to determine which selftests
+ * are available to be run.
+ */
+ #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
+ /*
+ * This command allows manufacturing tool to request which selftests
+ * to run.
+ */
+ #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
/* Experimental */
#define HWRM_TF UINT32_C(0x2bc)
/* Experimental */
/* Experimental */
#define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
/* Experimental */
+ #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
+ /* Experimental */
#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
/* Experimental */
#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
/* Experimental */
+ #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
+ /* Experimental */
+ #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
+ /* Experimental */
+ #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
+ /* Experimental */
#define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
/* Experimental */
#define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
/* Experimental */
#define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
/* Experimental */
+ #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
+ /* Experimental */
+ #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
+ /* Experimental */
#define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
/* Experimental */
#define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
/* Experimental */
#define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
/* Experimental */
+ #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
+ /* Experimental */
+ #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
+ /* Experimental */
+ #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
+ /* Experimental */
+ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
+ /* Experimental */
#define HWRM_SV UINT32_C(0x400)
/* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
#define HWRM_DBG_QCFG UINT32_C(0xff21)
/* Set destination parameters for crashdump medium */
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
+ /* Experimental */
+ #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
+ #define HWRM_NVM_DEFRAG UINT32_C(0xffec)
#define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
/* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
* may try again later.
*/
#define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
+ /*
+ * This error code is reported by Firmware when an operation requested
+ * by the host is not allowed due to a secure lock violation.
+ */
+ #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
+ /*
+ * This error code is reported by Firmware when an operation requested
+ * by a VF cannot be forwarded to the parent PF as required, either
+ * because the PF is down or otherwise doesn't have an appropriate
+ * async completion ring or associated forwarding buffers configured.
+ */
+ #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
-#define HWRM_VERSION_UPDATE 1
+#define HWRM_VERSION_UPDATE 2
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 45
-#define HWRM_VERSION_STR "1.10.1.45"
+#define HWRM_VERSION_RSVD 68
+#define HWRM_VERSION_STR "1.10.2.68"
/****************
* hwrm_ver_get *
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
UINT32_C(0x4000)
+ /*
+ * If set to 1, then firmware supports secure boot.
+ * If set to 0, then firmware doesn't support secure boot.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \
+ UINT32_C(0x8000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
* If set to 1, it will indicate to host drivers that firmware is
* not ready to start full blown HWRM commands. Host drivers should
* re-try HWRM_VER_GET with some timeout period. The timeout period
- * can be selected up to 5 seconds.
+ * can be selected up to 5 seconds. Host drivers should also check
+ * for dev_not_rdy_backing_store to identify if flag is set due to
+ * backing store not been available.
* For Example, PCIe hot-plug:
* Hot plug timing is system dependent. It generally takes up to
- * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
+ * 600 milliseconds for firmware to clear DEV_NOT_RDY flag.
* If set to 0, device is ready to accept all HWRM commands.
*/
- #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
+ #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
+ UINT32_C(0x1)
/*
* If set to 1, external version present.
* If set to 0, external version not present.
*/
- #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
+ #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
+ UINT32_C(0x2)
+ /*
+ * Firmware sets this flag along with dev_not_rdy flag to indicate
+ * host drivers that it has not completed resource initialization
+ * required for data path operations. Host drivers should not send
+ * any HWRM command that requires data path resources. Firmware will
+ * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
+ * those commands once both the flags are cleared.
+ * If this flag and dev_not_rdy flag are set to 0, device is ready
+ * to accept all HWRM commands.
+ */
+ #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
+ UINT32_C(0x4)
uint8_t unused_0[2];
/*
* For backward compatibility this field must be set to 1.
* used with the short cmd request format.
*/
uint16_t max_ext_req_len;
- uint8_t unused_1[5];
+ /*
+ * This field returns the maximum request timeout value in seconds.
+ * For backward compatibility, a value of zero should be interpreted
+ * as the default value of 40 seconds. Drivers should always honor the
+ * maximum timeout, but are permitted to warn if a longer duration than
+ * this default is advertised. Values larger than 40 seconds should
+ * only be used as a stopgap measure to address a device limitation or
+ * for the purposes of test and debugging. The long term goal is for
+ * firmware to significantly reduce this value in the passage of time.
+ */
+ uint16_t max_req_timeout;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
+/* cfa_bds_read_cmd_data_msg (size:128b/16B) */
+struct cfa_bds_read_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /*
+ * This is read command. From 32 to 128B can be read from a table
+ * using this command.
+ */
+ #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
+ #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
+ /* This value selects the table type to be acted upon. */
+ uint8_t table_type;
+ /* This value selects the table type to be acted upon. */
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
+ /* This command acts on the action table of the specified scope. */
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
+ /* This command acts on the exact match table of the specified scope. */
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
+ CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed. A
+ * value of zero is invalid. Maximum value is 4.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ /* This is the 32B index into the selected table to access. */
+ uint32_t table_index;
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+ #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+ /*
+ * This is the 64b host address where you want the data returned to. The
+ * data will be written to the same function as the one that owns the SQ
+ * this command is read from. The bottom two bits of this value must be
+ * zero. The size of the write is controlled by the data_size field.
+ */
+ uint64_t host_address;
+} __rte_packed;
+
+/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
+struct cfa_bds_write_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /*
+ * This is write command. From 32 to 128B can be written to a table
+ * using this command.
+ */
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
+ /* This value selects the table type to be acted upon. */
+ uint8_t write_thru_table_type;
+ /* This value selects the table type to be acted upon. */
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
+ /* This command acts on the action table of the specified scope. */
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
+ /* This command acts on the exact match table of the specified scope. */
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
+ CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
+ /*
+ * Indicates write-through control. Indicates write-through when set,
+ * or write back when cleared.
+ */
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed. A
+ * value of zero is invalid. Maximum value is 4.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ /* This is the 32B index into the selected table to access. */
+ uint32_t table_index;
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+ #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+ uint32_t unused0;
+ uint32_t unused1;
+ /*
+ * This is the data to be written. Data length is determined by the
+ * data_size field. The bd_cnt in the encapsulating BD must also be set
+ * correctly to ensure that the BD is processed correctly and the full
+ * WRITE_CMD message is extracted from the BD.
+ */
+ uint32_t dta[32];
+} __rte_packed;
+
+/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
+struct cfa_bds_read_clr_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /*
+ * This is read-clear command. 32B can be read from a table and
+ * a 16b mask can be used to clear specific 16b units after the
+ * read as an atomic operation.
+ */
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
+ /* This value selects the table type to be acted upon. */
+ uint8_t table_type;
+ /* This value selects the table type to be acted upon. */
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
+ /* This command acts on the action table of the specified scope. */
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
+ /* This command acts on the exact match table of the specified scope. */
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
+ CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed.
+ * Always set the value to 1.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ /* This is the 32B index into the selected table to access. */
+ uint32_t table_index;
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
+ UINT32_C(0x3ffffff)
+ #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+ /*
+ * This is the 64b host address where you want the data returned to. The
+ * data will be written to the same function as the one that owns the SQ
+ * this command is read from. The bottom two bits of this value must be
+ * zero. The size of the write is controlled by the data_size field.
+ */
+ uint64_t host_address;
+ /*
+ * This is active high clear mask for the 32B of data that this command
+ * can read. Bit 0 of the field will clear bits 15:0 of the first word
+ * of data read when set to '1'.
+ */
+ uint16_t clear_mask;
+ uint16_t unused0[3];
+ uint16_t unused1[4];
+} __rte_packed;
+
+/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
+struct cfa_bds_em_insert_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /*
+ * An exact match table insert will be attempted into the table.
+ * If there is a free location in the bucket, the payload will
+ * be written to the bucket.
+ */
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
+ /*
+ * Indicates write-through control. Indicates write-through when set,
+ * or write back when cleared.
+ */
+ uint8_t write_thru;
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
+ /*
+ * Indicates write-through control. Indicates write-through when set,
+ * or write back when cleared.
+ */
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed. A
+ * value of zero is invalid. Maximum value is 4.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ /* This is the 32B index into the selected table to access. */
+ uint32_t table_index;
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
+ UINT32_C(0x3ffffff)
+ #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+ /*
+ * This is the 64b host address where you want the data returned to. The
+ * data will be written to the same function as the one that owns the SQ
+ */
+ uint64_t host_address;
+ /*
+ * This is the Exact Match Lookup Record. Data length is determined by
+ * the data_size field. The bd_cnt in the encapsulating BD must also be
+ */
+ uint32_t dta[32];
+} __rte_packed;
+
+/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
+struct cfa_bds_em_delete_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /* An exact match table delete will be attempted. */
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
+ /*
+ * Indicates write-through control. Indicates write-through when set,
+ * or write back when cleared.
+ */
+ uint8_t write_thru;
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
+ /*
+ * Indicates write-through control. Indicates write-through when set,
+ * or write back when cleared.
+ */
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed. A
+ * value of zero is invalid. Maximum value is 4.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ uint32_t unused0;
+ /*
+ * This is the 64b host address where you want the data returned to. The
+ * data will be written to the same function as the one that owns the SQ
+ */
+ uint64_t host_address;
+ /*
+ * This is the Exact Match Lookup Record. Data length is determined by
+ * the data_size field. The bd_cnt in the encapsulating BD must also be
+ */
+ uint64_t dta;
+ uint32_t unused1[2];
+} __rte_packed;
+
+/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
+struct cfa_bds_invalidate_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /*
+ * The specified table area will be invalidated. If it is needed.
+ * again, it will be read from the backing store.
+ */
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
+ /* This value selects the table type to be acted upon. */
+ uint8_t table_type;
+ /* This value selects the table type to be acted upon. */
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
+ /* This command acts on the action table of the specified scope. */
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
+ UINT32_C(0x0)
+ /* This command acts on the exact match table of the specified scope. */
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
+ UINT32_C(0x1)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
+ CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /* This value specifies the number of cache lines to invalidate. */
+ uint8_t data_size;
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ /* This is the 32B index into the selected table to access. */
+ uint32_t table_index;
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
+ UINT32_C(0x3ffffff)
+ #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
+ uint32_t unused[2];
+} __rte_packed;
+
+/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
+struct cfa_bds_event_collect_cmd_data_msg {
+ /* This value selects the format for the mid-path command for the CFA. */
+ uint8_t opcode;
+ /* Reads notification messages from the Host Notification Queue. */
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
+ UINT32_C(0x6)
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
+ CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
+ uint8_t unused0;
+ /* This value selects which table scope will be accessed. */
+ uint8_t table_scope;
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
+ UINT32_C(0x1f)
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
+ /*
+ * This value identifies the number of 32B units will be accessed. A
+ * value of zero is invalid. Maximum value is 4.
+ */
+ uint8_t data_size;
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
+ #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
+ uint32_t unused1;
+ /*
+ * This is the 64b host address where you want the data returned to. The
+ * data will be written to the same function as the one that owns the SQ
+ */
+ uint64_t host_address;
+} __rte_packed;
+
+/* ce_bds_add_data_msg (size:512b/64B) */
+struct ce_bds_add_data_msg {
+ uint32_t version_algorithm_kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
+ /*
+ * This is the add command. Using this opcode, Host Driver can add
+ * information required for kTLS processing. The information is
+ * updated in the CFCK context.
+ */
+ #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
+ #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
+ CE_BDS_ADD_DATA_MSG_OPCODE_ADD
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated kTLS offloaded connection.
+ */
+ #define CE_BDS_ADD_DATA_MSG_KID_MASK \
+ UINT32_C(0xfffff0)
+ #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
+ /*
+ * Currently only two algorithms are supported, AES_GCM_128 and
+ * AES_GCM_256. Additional bits for future growth.
+ */
+ #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
+ UINT32_C(0xf000000)
+ #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
+ /* AES_GCM_128 Algorithm */
+ #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
+ UINT32_C(0x1000000)
+ /* AES_GCM_256 Algorithm */
+ #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
+ UINT32_C(0x2000000)
+ /*
+ * Version number of TLS connection. HW will provide registers that
+ * converts the 4b encoded version number to 16b of actual version
+ * number in the TLS Header. * Initialized --> By mid-path command *
+ * Updated --> Never though another mid-path command will result in an
+ * update.
+ */
+ #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
+ UINT32_C(0xf0000000)
+ #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
+ /* TLS1.2 Version */
+ #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
+ (UINT32_C(0x0) << 28)
+ /* TLS1.3 Version */
+ #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
+ (UINT32_C(0x1) << 28)
+ #define CE_BDS_ADD_DATA_MSG__LAST \
+ CE_BDS_ADD_DATA_MSG__TLS1_3
+ /*
+ * Command Type in the TLS header. HW will provide registers that
+ * converts the 3b encoded command type to 8b of actual command type in
+ * the TLS Header. * Initialized --> By mid-path command * Updated -->
+ * Never though another mid-path command will result in an update
+ */
+ uint8_t cmd_type;
+ #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
+ #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
+ /* Application */
+ #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
+ #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
+ CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
+ uint8_t unused0[3];
+ /*
+ * Salt is part of the nonce that is used as the Initial Vector (IV) in
+ * AES-GCM cipher suites. These are exchanged as part of the handshake
+ * process and is either the client_write_iv (when the client is
+ * sending) or server_write_iv (when the server is sending). In
+ * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
+ * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
+ * is zero padded to 12B and then xor'ed with the 4B of salt to generate
+ * the 12B of IV. This value is initialized by this mid-path command.
+ */
+ uint32_t salt;
+ uint32_t unused1;
+ /*
+ * This field keeps track of the TCP sequence number that is expected as
+ * the first byte in the next TCP packet. This field is calculated by HW
+ * using the output of the parser. The field is initialized as part of
+ * the Mid-path BD download/update of a kTLS connection. For every TCP
+ * packet processed, TCE HW will update the value to Current packet TCP
+ * sequence number + Current packet TCP Payload Length.
+ */
+ uint32_t pkt_tcp_seq_num;
+ /*
+ * This field maintains the TCP sequence number of the first byte in the
+ * header of the active TLS record. This field is initialized as part of
+ * the Mid-path BD download/update of a kTLS connection. For every
+ * record that is processed, TCE HW copies the value from the
+ * next_tls_header_tcp_seq_num field.
+ */
+ uint32_t tls_header_tcp_seq_num;
+ /*
+ * This is sequence number for the TLS record in a particular session.
+ * In TLS1.2, record sequence number is part of the Associated Data (AD)
+ * in the AEAD algorithm. In TLS1.3, record sequence number is part of
+ * the Initial Vector (IV). The field is initialized as part of the
+ * mid-path BD download/update of a kTLS connection. TCE HW increments
+ * the field after that for every record processed as it parses the TCP
+ * packet.
+ */
+ uint32_t record_seq_num[2];
+ /*
+ * Key used for encrypting or decrypting TLS records. The Key is
+ * exchanged during the hand-shake protocol by the client-server and
+ * provided to HW through this mid-path BD.
+ */
+ uint32_t session_key[8];
+} __rte_packed;
+
+/* ce_bds_delete_data_msg (size:64b/8B) */
+struct ce_bds_delete_data_msg {
+ uint32_t kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
+ /*
+ * This is the delete command. Using this opcode, the host Driver
+ * can remove a key context from the CFCK. If context is deleted
+ * and packets with the same KID come through the pipeline, the
+ * following actions are taken. For transmit packets, no crypto
+ * operation will be performed, payload will be zero'ed out. For
+ * receive packets, no crypto operation will be performed,
+ * payload will be unmodified.
+ */
+ #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
+ #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
+ CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated kTLS offloaded connection.
+ */
+ #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
+ #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
+ uint32_t unused0;
+} __rte_packed;
+
+/* ce_bds_resync_resp_ack_msg (size:128b/16B) */
+struct ce_bds_resync_resp_ack_msg {
+ uint32_t resync_status_kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
+ /*
+ * This command is used by the driver as a response to the resync
+ * request sent by the crypto engine.
+ */
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
+ CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated kTLS offloaded connection.
+ */
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
+ /*
+ * This field indicates if the resync request resulted in a success or
+ * a failure.
+ */
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
+ UINT32_C(0x1000000)
+ /*
+ * An ACK indicates that the driver was able to find the TLS record
+ * associated with TCP sequence number provided by the HW
+ */
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
+ (UINT32_C(0x0) << 24)
+ #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
+ CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
+ /*
+ * This field is the echo of the TCP sequence number provided in the
+ * resync request by the HW. If HW sent multiple resync requests, it
+ * only tracks the latest TCP sequence number. When the response from
+ * the Driver doesn't match the latest request, HW will drop the resync
+ * response.
+ */
+ uint32_t resync_record_tcp_seq_num;
+ /*
+ * This field indicates the TLS record sequence number associated with
+ * the resync request. HW will take this number and add the delta records
+ * it has found since sending the resync request, update the context and
+ * resume decrypting records.
+ */
+ uint32_t resync_record_seq_num[2];
+} __rte_packed;
+
+/* ce_bds_resync_resp_nack_msg (size:64b/8B) */
+struct ce_bds_resync_resp_nack_msg {
+ uint32_t resync_status_kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
+ /*
+ * This command is used by the driver as a response to the resync
+ * request sent by the crypto engine.
+ */
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
+ CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated kTLS offloaded connection.
+ */
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
+ UINT32_C(0xfffff0)
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
+ /*
+ * This field indicates if the resync request resulted in a success or
+ * a failure.
+ */
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
+ UINT32_C(0x1000000)
+ /*
+ * An NAK indicates that the driver wasn't able to find the TLS
+ * record associated with TCP sequence number provided by the HW
+ */
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
+ (UINT32_C(0x1) << 24)
+ #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
+ CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
+ /*
+ * This field is the echo of the TCP sequence number provided in the
+ * resync request by the HW. If HW sent multiple resync requests, it
+ * only tracks the latest TCP sequence number. When the response from
+ * the Driver doesn't match the latest request, HW will drop the resync
+ * response.
+ */
+ uint32_t resync_record_tcp_seq_num;
+} __rte_packed;
+
+/* crypto_presync_bd_cmd (size:256b/32B) */
+struct crypto_presync_bd_cmd {
+ uint8_t flags;
+ /*
+ * Typically, presync BDs are used for packet retransmissions. Source
+ * port sends all the packets in order over the network to destination
+ * port and packets get dropped in the network. The destination port
+ * will request retranmission of dropped packets and source port driver
+ * will send presync BD to setup the transmitter appropriately. It will
+ * provide the start and end TCP sequence number of the data to be
+ * transmitted. HW keeps two sets of context variable, one for in order
+ * traffic and one for retransmission traffic. HW is designed to
+ * transmit everything posted in the presync BD and return to in order
+ * mode after that. No inorder context variables are updated in the
+ * process. There is a special case where packets can be dropped
+ * between the TCP stack and Device Driver (Berkeley Packet Filter for
+ * ex) and HW still needs to transmit rest of the traffic. In this
+ * mode, driver will send a presync BD as if it is a retransmission but
+ * at the end of the transmission, the in order variables need to be
+ * updated. This flag is used by driver to indicate that in order
+ * variables needs to be updated at the end of completing the task
+ * associated with the presync BD.
+ */
+ #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
+ UINT32_C(0x1)
+ uint8_t unused0;
+ uint16_t unused1;
+ /*
+ * This field maintains the TCP sequence number of the first byte in the
+ * Header of the active TLS record. This field is set to 0 during
+ * mid-path BD updates, but is set to correct value when a presync BD is
+ * detected. For every record that is processed, the value from the
+ * next_tls_header_tcp_seq_num field is copied.
+ */
+ uint32_t header_tcp_seq_num;
+ /*
+ * When a retransmitted packet has a TLS authentication TAG present and
+ * the data spans multiple TCP Packets, HW is required to read the entire
+ * record to recalculate the TAG but only transmit what is required. This
+ * field is the start TCP sequence number of the packet(s) that need to
+ * be re-transmitted. This field is initialized to 0 during Mid-path BD
+ * add command and initialized to value provided by the driver when
+ * Pre-sync BD is detected. This field is never updated unless another
+ * Pre-sync BD signaling a new retransmission is scheduled.
+ */
+ uint32_t start_tcp_seq_num;
+ /*
+ * When a retransmitted packet has a TLS authentication TAG present and
+ * the data spans multiple TCP Packets, HW is required to read the
+ * entire record to recalculate the TAG but only transmit what is
+ * required. This field is the end TCP sequence number of the packet(s)
+ * that need to be re-transmitted. This field is initialized to 0 during
+ * Mid-path BD add command and initialized to value provided by the
+ * driver when Pre-sync BD is detected. This field is never updated
+ * unless another Pre-sync BD signaling a new retransmission is
+ * scheduled.
+ */
+ uint32_t end_tcp_seq_num;
+ /*
+ * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
+ * with the SALT). For retrans packets, this field is extracted from the
+ * TLS record, field right after the TLS Header and stored in the
+ * context. This field needs to be stored in context as TCP segmentation
+ * could have split the field into multiple TCP packets. This value is
+ * initialized to 0 when presync BD is detected by taking the value from
+ * the first TLS header. When subsequent TLS Headers are detected, the
+ * value is extracted from packet.
+ */
+ uint32_t explicit_nonce[2];
+ /*
+ * This is sequence number for the TLS record in a particular session. In
+ * TLS1.2, record sequence number is part of the Associated Data (AD) in
+ * the AEAD algorithm. In TLS1.3, record sequence number is part of the
+ * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
+ * download. Is initialized to correct value when a pre-sync BD is
+ * detected. TCE HW increments the field after that for every record
+ * processed as it parses the TCP packet. Subsequent pre-sync BDs
+ * delivering more retransmission instruction will also update this
+ * field.
+ */
+ uint32_t record_seq_num[2];
+} __rte_packed;
+
/* bd_base (size:64b/8B) */
struct bd_base {
uint8_t type;
* RX Producer Assembly Buffer Descriptor.
*/
#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
+ /*
+ * Indicates that this BD is used to issue a command to one of
+ * the mid-path destinations.
+ */
+ #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
+ /*
+ * Indicates that this BD is used to issue a cryptographic pre-
+ * sync command through the fast path and destined for TCE.
+ */
+ #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
/*
* Indicates that this BD is 32B long and is used for
* normal L2 packet transmission.
* used for any data that the driver wants to associate with the
* transmit BD.
*
- * This field must be valid on the first BD of a packet.
+ * This field must be valid on the first BD of a packet. If completion
+ * coalescing is enabled on the TX ring, it is suggested that the driver
+ * populate the opaque field to indicate the specific TX ring with which
+ * the completion is associated, then utilize the opaque and sq_cons_idx
+ * fields in the coalesced completion record to determine the specific
+ * packets that are to be completed on that ring.
*/
uint32_t opaque;
/*
*/
uint16_t len;
/*
- * The opaque data field is pass through to the completion and can be
+ * The opaque data field is passed through to the completion and can be
* used for any data that the driver wants to associate with the
* transmit BD.
*
- * This field must be valid on the first BD of a packet.
+ * This field must be valid on the first BD of a packet. If completion
+ * coalescing is enabled on the TX ring, it is suggested that the driver
+ * populate the opaque field to indicate the specific TX ring with which
+ * the completion is associated, then utilize the opaque and sq_cons_idx
+ * fields in the coalesced completion record to determine the specific
+ * packets that are to be completed on that ring.
*/
uint32_t opaque;
/*
#define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
/*
* If set to 1, the device will record the time at which the packet
- * was actually transmitted at the TX MAC.
+ * was actually transmitted at the TX MAC for 2-step time sync.
*
* This bit must be valid on the first BD of a packet.
*/
* Send Offload) processing for both normal or encapsulated
* packets, which is a form of TCP segmentation. When this bit
* is 1, the hdr_size and mss fields must be valid. The driver
- * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
- * flags since the controller will replace the appropriate
- * checksum fields for segmented packets.
+ * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
+ * tcp_udp_chksum flags since the controller will replace the
+ * appropriate checksum fields for segmented packets.
*
* When this bit is 1, the hdr_size and mss fields must be valid.
*/
* packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
- uint16_t hdr_size;
+ /*
+ * If set to '1', then the timestamp from the BD is used. If cleared
+ * to 0, then TWE provides the timestamp.
+ */
+ #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
+ /*
+ * If set to '1', this operation will cause a trace capture in each
+ * block it passes through.
+ */
+ #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
+ /*
+ * If set to '1', the device will record the time at which the packet
+ * was actually transmitted at the TX MAC for 1-step time sync. This
+ * bit must be valid on the first BD of a packet.
+ */
+ #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
+ /*
+ * If set to '1', the controller replaces the Outer-tunnel IP checksum
+ * field with hardware calculated IP checksum for the IP header of the
+ * packet associated with this descriptor. For outer UDP checksum, it
+ * will be the following behavior for all cases independent of settings
+ * of inner LSO and checksum offload BD flags. If outer UDP checksum
+ * is 0, then do not update it. If outer UDP checksum is non zero, then
+ * the hardware should compute and update it.
+ */
+ #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
+ /*
+ * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
+ * header will not be modified during LSO operations. If set to one
+ * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
+ * incremented for each subsequent segment of an LSO operation. The
+ * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
+ * packet.
+ */
+ #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
+ /*
+ * If set to '1', When set to 1, KTLS encryption will be enabled for
+ * the packet.
+ */
+ #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
+ uint16_t kid_or_ts_low_hdr_size;
/*
* When LSO is '1', this field must contain the offset of the
* TCP payload from the beginning of the packet in as
*
* This value must be valid on the first BD of a packet.
*/
- #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
- #define TX_BD_LONG_HDR_SIZE_SFT 0
- uint32_t mss;
+ #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
+ #define TX_BD_LONG_HDR_SIZE_SFT 0
+ /*
+ * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
+ * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
+ * 20-bit KID.
+ */
+ #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
+ #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
+ uint32_t kid_or_ts_high_mss;
/*
* This is the MSS value that will be used to do the LSO processing.
* The value is the length in bytes of the TCP payload for each
*
* This value must be valid on the first BD of a packet.
*/
- #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
- #define TX_BD_LONG_MSS_SFT 0
- uint16_t unused2;
+ #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
+ #define TX_BD_LONG_MSS_SFT 0
+ /*
+ * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
+ * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
+ * of this field contain the upper 13 bits of the 20-bit KID.
+ */
+ #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
+ #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
+ /*
+ * This value selects bits 25:16 of the CFA action to perform on the
+ * packet. See the cfa_action field for more information.
+ */
+ uint16_t cfa_action_high;
+ #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
+ #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
/*
* This value selects a CFA action to perform on the packet.
* Set this value to zero if no CFA action is desired.
*/
uint32_t cfa_meta;
/* When key=1, This is the VLAN tag VID value. */
- #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
- #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
+ #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
+ #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
/* When key=1, This is the VLAN tag DE value. */
- #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
+ #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
/* When key=1, This is the VLAN tag PRI value. */
- #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
- #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
+ #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
+ #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
/* When key=1, This is the VLAN tag TPID select value. */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
- #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
/* 0x88a8 */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
+ (UINT32_C(0x0) << 16)
/* 0x8100 */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
+ (UINT32_C(0x1) << 16)
/* 0x9100 */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
+ (UINT32_C(0x2) << 16)
/* 0x9200 */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
+ (UINT32_C(0x3) << 16)
/* 0x9300 */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
+ (UINT32_C(0x4) << 16)
/* Value programmed in CFA VLANTPID register. */
- #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
+ #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
+ (UINT32_C(0x5) << 16)
#define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
/* When key=1, This is the VLAN tag TPID select value. */
- #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
- #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
+ #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
+ #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
/*
* This field identifies the type of edit to be performed
* on the packet.
*
* This value must be valid on the first BD of a packet.
*/
- #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
- #define TX_BD_LONG_CFA_META_KEY_SFT 28
+ #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
+ #define TX_BD_LONG_CFA_META_KEY_SFT 28
/* No editing */
- #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
+ #define TX_BD_LONG_CFA_META_KEY_NONE \
+ (UINT32_C(0x0) << 28)
/*
* - meta[17:16] - TPID select value (0 = 0x8100).
* - meta[15:12] - PRI/DE value.
* - meta[11:0] - VID value.
*/
- #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
+ #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
+ (UINT32_C(0x1) << 28)
+ /*
+ * Provide metadata
+ * - Wh+/SR - this option is not supported.
+ * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
+ * is set in the Lookup Table.
+ * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
+ * en_bd_meta is set in the Lookup Table.
+ */
+ #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
+ (UINT32_C(0x2) << 28)
#define TX_BD_LONG_CFA_META_KEY_LAST \
- TX_BD_LONG_CFA_META_KEY_VLAN_TAG
+ TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
} __rte_packed;
/*
/*
* The opaque data field is passed through to the completion and can be
* used for any data that the driver wants to associate with the transmit
- * BD.
+ * BD. This field must be valid on the first BD of a packet. If
+ * completion coalescing is enabled on the TX ring, it is suggested that
+ * the driver populate the opaque field to indicate the specific TX ring
+ * with which the completion is associated, then utilize the opaque and
+ * sq_cons_idx fields in the coalesced completion record to determine
+ * the specific packets that are to be completed on that ring.
*
* This field must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
/*
* If set to 1, the device will record the time at which the packet
- * was actually transmitted at the TX MAC.
+ * was actually transmitted at the TX MAC for 2-step time sync. This
+ * bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
/*
* packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
- uint16_t unused2;
- uint32_t unused3;
- uint16_t unused4;
+ /*
+ * If set to '1', then the timestamp from the BD is used. If cleared
+ * to 0, then TWE provides the timestamp.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
+ /*
+ * If set to '1', this operation will cause a trace capture in each
+ * block it passes through.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
+ /*
+ * If set to '1', the device will record the time at which the packet
+ * was actually transmitted at the TX MAC for 1-step time sync. This
+ * bit must be valid on the first BD of a packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
+ /*
+ * If set to '1', the controller replaces the Outer-tunnel IP checksum
+ * field with hardware calculated IP checksum for the IP header of the
+ * packet associated with this descriptor. For outer UDP checksum, it
+ * will be the following behavior for all cases independent of settings
+ * of inner LSO and checksum offload BD flags. If outer UDP checksum
+ * is 0, then do not update it. If outer UDP checksum is non zero, then
+ * the hardware should compute and update it.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
+ /*
+ * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
+ * header will not be modified during LSO operations. If set to one
+ * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
+ * incremented for each subsequent segment of an LSO operation. The
+ * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
+ * packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
+ /*
+ * If set to '1', When set to 1, KTLS encryption will be enabled for
+ * the packet.
+ */
+ #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
+ uint8_t unused2;
+ uint8_t kid_or_ts_low;
+ #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
+ /*
+ * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
+ * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
+ * the 20-bit KID.
+ */
+ #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
+ #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
+ uint32_t kid_or_ts_high;
+ #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
+ #define TX_BD_LONG_INLINE_UNUSED_SFT 0
+ /*
+ * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
+ * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
+ * of this field contain the upper 13 bits of the 20-bit KID.
+ */
+ #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
+ #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
+ /*
+ * This value selects bits 25:16 of the CFA action to perform on the
+ * packet. See the cfa_action field for more information.
+ */
+ uint16_t cfa_action_high;
+ #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
+ #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
/*
* This value selects a CFA action to perform on the packet.
* Set this value to zero if no CFA action is desired.
*/
uint32_t cfa_meta;
/* When key = 1, this is the VLAN tag VID value. */
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
/* When key = 1, this is the VLAN tag DE value. */
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
+ UINT32_C(0x1000)
/* When key = 1, this is the VLAN tag PRI value. */
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
+ UINT32_C(0xe000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
/* When key = 1, this is the VLAN tag TPID select value. */
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
+ UINT32_C(0x70000)
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
/* 0x88a8 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
(UINT32_C(0x0) << 16)
TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
UINT32_C(0xff80000)
- #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
+ #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
/*
* This field identifies the type of edit to be performed
* on the packet.
*/
#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
UINT32_C(0xf0000000)
- #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
/* No editing */
#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
(UINT32_C(0x0) << 28)
*/
#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
(UINT32_C(0x1) << 28)
+ /*
+ * Provide metadata
+ * - Wh+/SR - this option is not supported.
+ * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
+ * is set in the Lookup Table.
+ * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
+ * en_bd_meta is set in the Lookup Table.
+ */
+ #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
+ (UINT32_C(0x2) << 28)
#define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
- TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
+ TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
} __rte_packed;
/* tx_bd_empty (size:128b/16B) */
uint8_t unused_4[8];
} __rte_packed;
+/* tx_bd_mp_cmd (size:128b/16B) */
+struct tx_bd_mp_cmd {
+ /* Unless otherwise stated, sub-fields of this field are always valid. */
+ uint16_t flags_type;
+ /* This value identifies the type of buffer descriptor. */
+ #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
+ #define TX_BD_MP_CMD_TYPE_SFT 0
+ /*
+ * Indicates that this BD is used to issue a command to one of
+ * the mid-path destinations.
+ */
+ #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
+ #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
+ #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
+ #define TX_BD_MP_CMD_FLAGS_SFT 6
+ /* */
+ #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
+ #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
+ /*
+ * This value indicates the number of 16B BD locations (slots)
+ * consumed in the ring by this mid-path command BD, including the
+ * BD header and the command field.
+ */
+ #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
+ #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
+ /*
+ * This value defines the length of command field in bytes. The maximum
+ * value shall be 496.
+ */
+ uint16_t len;
+ /*
+ * The opaque data field is pass through to the completion and can be
+ * used for any data that the driver wants to associate with this
+ * Tx mid-path command.
+ */
+ uint32_t opaque;
+ uint64_t unused1;
+} __rte_packed;
+
+/* tx_bd_presync_cmd (size:128b/16B) */
+struct tx_bd_presync_cmd {
+ /* Unless otherwise stated, sub-fields of this field are always valid. */
+ uint16_t flags_type;
+ /* This value identifies the type of buffer descriptor. */
+ #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
+ #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
+ /*
+ * Indicates that this BD is used to issue a cryptographic pre-
+ * sync command through the fast path and destined for TCE.
+ */
+ #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
+ #define TX_BD_PRESYNC_CMD_TYPE_LAST \
+ TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
+ #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
+ #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
+ /* */
+ #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
+ #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
+ /*
+ * This value indicates the number of 16B BD locations (slots)
+ * consumed in the ring by this pre-sync command BD, including the
+ * BD header and the command field.
+ */
+ #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
+ #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
+ /*
+ * This value defines the length of command field in bytes. The maximum
+ * value shall be 496.
+ */
+ uint16_t len;
+ /*
+ * The opaque data field is pass through to TCE and can be used for
+ * debug.
+ */
+ uint32_t opaque;
+ /*
+ * This field is the Crypto Context ID to which the retransmit packet is
+ * applied. The KID references the context fields used by the
+ * associated kTLS offloaded connection.
+ */
+ uint32_t kid;
+ /*
+ * The KID value of all-ones is reserved for non-KTLS packets, which
+ * only implies that this value must not be used when filling this
+ * field for crypto packets.
+ */
+ #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
+ #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
+ uint32_t unused_1;
+} __rte_packed;
+
/* rx_prod_pkt_bd (size:128b/16B) */
struct rx_prod_pkt_bd {
/* This value identifies the type of buffer descriptor. */
*/
#define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
/*
+ * This field has been deprecated. There can be no additional
+ * BDs for this packet from this ring.
+ *
+ * Old definition:
* This value is the number of additional buffers in the ring that
* describe the buffer space to be consumed for this packet.
* If the value is zero, then the packet must fit within the
* space described by this BD. If this value is 1 or more, it
* indicates how many additional "buffer" BDs are in the ring
* immediately following this BD to be used for the same
- * network packet.
- *
- * Even if the packet to be placed does not need all the
- * additional buffers, they will be consumed anyway.
+ * network packet. Even if the packet to be placed does not need
+ * all the additional buffers, they will be consumed anyway.
*/
#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
#define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
uint64_t address;
} __rte_packed;
+/* cfa_cmpls_cmp_data_msg (size:128b/16B) */
+struct cfa_cmpls_cmp_data_msg {
+ uint32_t mp_client_dma_length_opcode_status_type;
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
+ #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
+ /* Mid Path Short Completion with length = 16B. */
+ #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
+ UINT32_C(0x1e)
+ #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
+ CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+ /* This value indicates the status for the command. */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
+ /* Completed without error. */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
+ (UINT32_C(0x0) << 6)
+ /* Indicates an unsupported CFA opcode in the command. */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
+ (UINT32_C(0x1) << 6)
+ /*
+ * Indicates a CFA command formatting error. This error can occur on
+ * any of the supported CFA commands.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
+ (UINT32_C(0x2) << 6)
+ /*
+ * Indicates an SVIF-Table scope error. This error can occur on any
+ * of the supported CFA commands.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
+ (UINT32_C(0x3) << 6)
+ /*
+ * Indicates that the table_index is either outside of the
+ * table_scope range set by its EM_SIZE or, for EM Insert, it is in
+ * the static bucket range. This error can occur on EM Insert
+ * commands. It can also occur on Read, Read Clear, Write, and
+ * Invalidate commands if the table_type is EM.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
+ (UINT32_C(0x4) << 6)
+ /*
+ * Cache operation responded with an error. This error can occur on
+ * Read, Read Clear, Write, EM Insert, and EM Delete commands.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
+ (UINT32_C(0x5) << 6)
+ /*
+ * Indicates failure on EM Insert or EM Delete Command. Hash index
+ * and hash msb are returned in table_index and hash_msb fields.
+ * Dma_length is set to 1 if the bucket is also returned (as dma
+ * data).
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
+ (UINT32_C(0x6) << 6)
+ /*
+ * Indicates no notifications were available on an Event Collection
+ * command.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
+ (UINT32_C(0x7) << 6)
+ #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
+ CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
+ /* This is the opcode from the command. */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
+ UINT32_C(0xff000)
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
+ /*
+ * This is read command. From 32 to 128B can be read from a table
+ * using this command.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
+ (UINT32_C(0x0) << 12)
+ /*
+ * This is write command. From 32 to 128B can be written to a table
+ * using this command.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
+ (UINT32_C(0x1) << 12)
+ /*
+ * This is read-clear command. 32B can be read from a table and a 16b
+ * mask can be used to clear specific 16b units after the read as an
+ * atomic operation.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
+ (UINT32_C(0x2) << 12)
+ /*
+ * An exact match table insert will be attempted into the table. If
+ * there is a free location in the bucket, the payload will be
+ * written to the bucket.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
+ (UINT32_C(0x3) << 12)
+ /* An exact match table delete will be attempted. */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
+ (UINT32_C(0x4) << 12)
+ /*
+ * The specified table area will be invalidated. If it is needed
+ * again, it will be read from the backing store.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
+ (UINT32_C(0x5) << 12)
+ /* Reads notification messages from the Host Notification Queue. */
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
+ (UINT32_C(0x6) << 12)
+ #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
+ CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
+ /*
+ * This field indicates the length of the DMA that accompanies the
+ * completion. Specified in units of DWords (32b). Valid values are
+ * between 0 and 128. A value of zero indicates that there is no DMA
+ * that accompanies the completion.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
+ UINT32_C(0xff00000)
+ #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
+ UINT32_C(0xf0000000)
+ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
+ /* TX configurable flow processing block. */
+ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
+ (UINT32_C(0x2) << 28)
+ /* RX configurable flow processing block. */
+ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
+ (UINT32_C(0x3) << 28)
+ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
+ CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque;
+ uint16_t hash_msb_v;
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will
+ * write 1. The odd passes will write 0.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
+ /*
+ * This is the upper 12b of the hash, returned on Exact Match
+ * Insertion/Deletion Commands.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
+ #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
+ /* This is the table type from the command. */
+ uint8_t table_type;
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
+ #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
+ /* This command acts on the action table of the specified scope. */
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
+ /* This command acts on the exact match table of the specified scope. */
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
+ CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
+ uint8_t table_scope;
+ /* This is the table scope from the command. */
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
+ uint32_t table_index;
+ /*
+ * This is the table index from the command (if it exists). However, if
+ * an Exact Match Insertion/Deletion command failed, then this is the
+ * table index of the calculated static hash bucket.
+ */
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
+ #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
+} __rte_packed;
+
+/* CFA Mid-Path 32B DMA Message */
+/* cfa_dma32b_data_msg (size:256b/32B) */
+struct cfa_dma32b_data_msg {
+ /* DMA data value. */
+ uint32_t dta[8];
+} __rte_packed;
+
+/* CFA Mid-Path 64B DMA Message */
+/* cfa_dma64b_data_msg (size:512b/64B) */
+struct cfa_dma64b_data_msg {
+ /* DMA data value. */
+ uint32_t dta[16];
+} __rte_packed;
+
+/* CFA Mid-Path 96B DMA Message */
+/* cfa_dma96b_data_msg (size:768b/96B) */
+struct cfa_dma96b_data_msg {
+ /* DMA data value. */
+ uint32_t dta[24];
+} __rte_packed;
+
+/* CFA Mid-Path 128B DMA Message */
+/* cfa_dma128b_data_msg (size:1024b/128B) */
+struct cfa_dma128b_data_msg {
+ /* DMA data value. */
+ uint32_t dta[32];
+} __rte_packed;
+
+/* ce_cmpls_cmp_data_msg (size:128b/16B) */
+struct ce_cmpls_cmp_data_msg {
+ uint16_t status_subtype_type;
+ /*
+ * This field indicates the exact type of the completion. By
+ * convention, the LSB identifies the length of the record in 16B
+ * units. Even values indicate 16B records. Odd values indicate 32B
+ * records.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
+ #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
+ /* Completion of a Mid Path Command. Length = 16B */
+ #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
+ #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
+ CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+ /*
+ * This value indicates the CE sub-type operation that is being
+ * completed.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
+ /* Completion Response for a Solicited Command. */
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
+ /* Error Completion (Unsolicited). */
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
+ /* Re-Sync Completion (Unsolicited) */
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
+ CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
+ /* This value indicates the status for the command. */
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
+ /* Completed without error. */
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
+ (UINT32_C(0x0) << 10)
+ /* CFCK load error. */
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
+ (UINT32_C(0x1) << 10)
+ /* FID check error. */
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
+ (UINT32_C(0x2) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
+ CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
+ uint8_t unused0;
+ uint8_t mp_clients;
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
+ /* TX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
+ /* RX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
+ CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
+ /*
+ * This is a copy of the opaque field from the mid path BD of this
+ * command.
+ */
+ uint32_t opaque;
+ /* */
+ uint32_t kid_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes will
+ * write 1. The odd passes will write 0.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated kTLS offloaded connection.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
+ #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
+ uint32_t unused2;
+} __rte_packed;
+
/* cmpl_base (size:128b/16B) */
struct cmpl_base {
uint16_t type;
* truncation placement is used, this value represents the placed
* (truncated) length of the packet.
*/
- #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
- #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
+ #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
+ #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
/* This is data from the CFA as indicated by the meta_format field. */
- #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
- #define RX_PKT_V2_CMPL_METADATA1_SFT 12
- /* When meta_format != 0, this value is the VLAN TPID_SEL. */
- #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
- #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
+ #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
+ #define RX_PKT_V2_CMPL_METADATA1_SFT 12
/* When meta_format != 0, this value is the VLAN TPID_SEL. */
- #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
+ /* 0x88a8 */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
+ (UINT32_C(0x0) << 12)
+ /* 0x8100 */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
+ (UINT32_C(0x1) << 12)
+ /* 0x9100 */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
+ (UINT32_C(0x2) << 12)
+ /* 0x9200 */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
+ (UINT32_C(0x3) << 12)
+ /* 0x9300 */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
+ (UINT32_C(0x4) << 12)
+ /* Value programmed in CFA VLANTPID register. */
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
+ (UINT32_C(0x5) << 12)
+ #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
+ RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
+ /* When meta_format != 0, this value is the VLAN valid. */
+ #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
/*
* This value is the RSS hash value calculated for the packet
* based on the mode bits and key value in the VNIC. When vee_cmpl_mode
* with. Use this number to correlate the TPA start completion
* with the TPA end completion.
*/
- #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
- #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
- #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
- #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
+ #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
+ #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
+ #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
+ UINT32_C(0xf000)
+ #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
/* When meta_format != 0, this value is the VLAN TPID_SEL. */
- #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
- #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
+ UINT32_C(0x7000)
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
+ /* 0x88a8 */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
+ (UINT32_C(0x0) << 12)
+ /* 0x8100 */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
+ (UINT32_C(0x1) << 12)
+ /* 0x9100 */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
+ (UINT32_C(0x2) << 12)
+ /* 0x9200 */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
+ (UINT32_C(0x3) << 12)
+ /* 0x9300 */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
+ (UINT32_C(0x4) << 12)
+ /* Value programmed in CFA VLANTPID register. */
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
+ (UINT32_C(0x5) << 12)
+ #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
+ RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
/* When meta_format != 0, this value is the VLAN valid. */
- #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
+ #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
+ UINT32_C(0x8000)
/*
* This value is the RSS hash value calculated for the packet
* based on the mode bits and key value in the VNIC.
* records. Odd values indicate 32B
* records.
*/
- #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
+ #define RX_TPA_V2_END_CMPL_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
/*
* RX L2 TPA End Completion:
* Completion at the end of a TPA operation.
* Length = 32B
*/
- #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
+ #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
+ UINT32_C(0x15)
#define RX_TPA_V2_END_CMPL_TYPE_LAST \
RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
- #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
- #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
+ #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
+ UINT32_C(0xffc0)
+ #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
* error of some type. Type of error is indicated in
* error_flags.
*/
- #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
+ #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
+ UINT32_C(0x40)
/* This field indicates how the packet was placed in the buffer. */
- #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
- #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
+ UINT32_C(0x380)
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
/*
* Jumbo:
* TPA Packet was placed using jumbo algorithm. This means
*/
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
(UINT32_C(0x6) << 7)
+ /*
+ * IOC/Header-Data Separation:
+ * Packet will be placed using In-Order Completion/HDS where
+ * the header is in the first packet buffer. Payload of each
+ * packet will be placed such that each packet starts at the
+ * beginning of an aggregation buffer.
+ */
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
+ (UINT32_C(0x7) << 7)
#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
- RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
- /* unused is 2 b */
- #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
- #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
+ RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
+ /* unused is 1 b */
+ #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
+ UINT32_C(0x400)
+ /*
+ * This bit is '1' if metadata has been added to the end of the
+ * packet in host memory. Metadata starts at the first 32B boundary
+ * after the end of the packet for regular and jumbo placement.
+ * It starts at the first 32B boundary after the end of the header
+ * for HDS placement. The length of the metadata is indicated in the
+ * metadata itself.
+ */
+ #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
+ UINT32_C(0x800)
/*
* This value indicates what the inner packet determined for the
* packet was.
* field is valid and contains the TCP checksum.
* This also indicates that the payload_offset field is valid.
*/
- #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
- #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
+ #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
+ UINT32_C(0xf000)
+ #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
/*
* This value is zero for TPA End completions.
* There is no data in the buffer that corresponds to the opaque
/* Master function selection event */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
UINT32_C(0x9)
+ /*
+ * An event signifying that a ring has been disabled by
+ * hw due to error.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
+ UINT32_C(0xa)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
UINT32_C(0x41)
+ /*
+ * An echo request from the firmware. An echo response is expected by
+ * the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
+ UINT32_C(0x42)
+ /*
+ * An event from firmware indicating who has been selected as the
+ * PHC Master or secondary. Also indicates the last time a failover
+ * happens.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER \
+ UINT32_C(0x43)
+ /*
+ * An event from firmware showing the last PPS timestamp that has been
+ * latched.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \
+ UINT32_C(0x44)
+ /*
+ * An event from firmware indicating that an error has occurred.
+ * The driver should log the event so that an administrator can be
+ * aware that a problem has occurred that may need attention.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ /* Maximum Registrable event id. */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
+ UINT32_C(0x46)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
/* APP configuration change */
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
UINT32_C(0x4)
+ /* DSCP configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \
+ UINT32_C(0x8)
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
UINT32_C(0x8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
- /* Event specific data */
+ /* Event specific data. The data is for internal debug use only. */
uint32_t event_data2;
+ /*
+ * These bits indicate the status as being reported by the firmware.
+ * This value is exactly the same as status code in fw_status register.
+ * If the status code is equal to 0x8000, then the reset is initiated
+ * by the Host using the FW_RESET command when the FW is in a healthy
+ * state. If the status code is not equal to 0x8000, then the reset is
+ * initiated by the FW to recover from the error or FATAL state.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
+ 0
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
/* A non-fatal firmware exception has occurred. */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
(UINT32_C(0x3) << 8)
+ /* Fast reset */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
+ (UINT32_C(0x4) << 8)
+ /*
+ * Reset was a result of a firmware activation. That is, the
+ * fw_activation flag was set in a FW_RESET operation.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \
+ (UINT32_C(0x5) << 8)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
- HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
+ HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
/*
* Minimum time before driver should attempt access - units 100ms ticks.
* Range 0-65535
UINT32_C(0x2)
} __rte_packed;
+/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_ring_monitor_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Ring Monitor Message. */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
+ UINT32_C(0xa)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Type of Ring disabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
+ 0
+ /* tx ring disabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
+ UINT32_C(0x0)
+ /* rx ring disabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
+ UINT32_C(0x1)
+ /* cmpl ring disabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /*
+ * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
+ * then this field will indicate the ring id.
+ */
+ uint32_t event_data1;
+} __rte_packed;
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
/* Event specific data */
uint32_t event_data2;
+ /*
+ * This value indicates the VF ID of the VF whose configuration
+ * is changing if this async. event is sent to the parent PF.
+ * The firmware supports sending this to the parent PF if the
+ * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1.
+ * This value is undefined when the async. event is sent to the
+ * VF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
8
} __rte_packed;
+/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
+struct hwrm_async_event_cmpl_echo_request {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * An echo request from the firmware. An echo response is expected by
+ * the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
+ UINT32_C(0x42)
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
+ /* Event specific data that should be provided in the echo response */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data that should be provided in the echo response */
+ uint32_t event_data1;
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
+struct hwrm_async_event_cmpl_phc_master {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async event is used to notify driver of changes
+ * in PHC master. Only one master function can configure
+ * PHC.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER \
+ UINT32_C(0x43)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
+ /* Event specific data */
+ uint32_t event_data2;
+ /* This field provides the current master function. */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT \
+ 0
+ /* This field provides the current secondary function. */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK \
+ UINT32_C(0xffff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT \
+ 16
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates to the driver the type of PHC event. */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xf)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * Indicates PHC Master selection event. The master fid is
+ * specified in event_data2.phc_master_fid.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER \
+ UINT32_C(0x1)
+ /*
+ * Indicates PHC Secondary selection event. The secondary fid is
+ * specified in event_data2.phc_sec_fid.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY \
+ UINT32_C(0x2)
+ /*
+ * Indicates PHC failover event. Failover happens from
+ * event_data2.phc_master_fid to event_data2.phc_sec_fid.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER \
+ UINT32_C(0x3)
+ #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
+struct hwrm_async_event_cmpl_pps_timestamp {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used to inform
+ * driver of the latest PPS timestamp that has been latched.
+ * When driver enables PPS event, Firmware will generate
+ * PPS timestamps every second, Firmware informs driver
+ * of this timestamp through the async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \
+ UINT32_C(0x44)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the PPS event type */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \
+ UINT32_C(0x1)
+ /* This is an internal event. */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \
+ UINT32_C(0x0)
+ /* This is an external event. */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
+ /*
+ * Indicates the pin number on which the event is
+ * received.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \
+ UINT32_C(0xe)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \
+ 1
+ /*
+ * Contains bits[47:32] of the upper PPS timestamp.
+ * Lower 32 bits are in event_data1. Together they
+ * provide the 48 bit PPS timestamp.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \
+ UINT32_C(0xffff0)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \
+ 4
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Contains the lower 32 bits of the PPS timestamp. */
+ uint32_t event_data1;
+ /* Contains the lower 32 bit PPS timestamp */
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \
+ UINT32_C(0xffffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \
+ 0
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Indicates the type of error being reported. See section on Error
+ * Report event error_types for details on each error.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
+} __rte_packed;
+
/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
struct hwrm_async_event_cmpl_fw_trace_msg {
uint16_t type;
UINT32_C(0x1)
} __rte_packed;
+/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_base {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /* Reserved */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \
+ UINT32_C(0x0)
+ /*
+ * The NIC was subjected to an extended pause storm which caused it
+ * to disable flow control in order to avoid stalling the Tx path.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
+ UINT32_C(0x1)
+ /*
+ * The NIC received an interrupt storm on a TSIO pin being used as
+ * PPS_IN which caused it to disable the interrupt. The signal
+ * should be fixed to be a proper 1 PPS signal before re-enabling
+ * it. The pin number on which this signal was received is stored
+ * in event_data2 as pin_id.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
+ UINT32_C(0x2)
+ /*
+ * There was a low level error with an NVM write or erase.
+ * See nvm_err_type for more details.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \
+ UINT32_C(0x3)
+ /*
+ * This indicates doorbell drop threshold was hit. When this
+ * threshold is crossed, it indicates one or more doorbells for
+ * the function were dropped by hardware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
+ UINT32_C(0x4)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_pause_storm {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * The NIC was subjected to an extended pause storm which caused it
+ * to disable flow control in order to avoid stalling the Tx path.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_invalid_signal {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ /* Indicates the TSIO pin on which invalid signal is detected. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \
+ 0
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * The NIC received an interrupt storm on a TSIO pin being used as
+ * PPS_IN which caused it to disable the interrupt. The signal
+ * should be fixed to be a proper 1 PPS signal before re-enabling
+ * it. The pin number on which this signal was received is stored
+ * in event_data2 as pin_id.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_nvm {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ /* Indicates the address where error was detected */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \
+ UINT32_C(0xffffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \
+ 0
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * There was a low level error with an NVM operation.
+ * See nvm_err_type for more details.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \
+ UINT32_C(0x3)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
+ /* The specific type of NVM error */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \
+ 8
+ /*
+ * There was a low level error with an NVM write operation.
+ * Verification of written data did not match.
+ * event_data2 will be the failing address.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \
+ (UINT32_C(0x1) << 8)
+ /*
+ * There was a low level error with an NVM erase operation.
+ * All the bits were not erased.
+ * event_data2 will be the failing address.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \
+ (UINT32_C(0x2) << 8)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform
+ * the driver that an error has occurred which may need
+ * the attention of the administrator.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \
+ UINT32_C(0x45)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \
+ 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the type of error being reported. */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \
+ 0
+ /*
+ * This indicates doorbell drop threshold was hit. When this
+ * threshold is crossed, it indicates one or more doorbells for
+ * the function were dropped by hardware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \
+ UINT32_C(0x4)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
+} __rte_packed;
+
+/* metadata_base_msg (size:64b/8B) */
+struct metadata_base_msg {
+ uint16_t md_type_link;
+ /* This field classifies the data present in the meta-data. */
+ #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
+ #define METADATA_BASE_MSG_MD_TYPE_SFT 0
+ /* Meta data fields are not valid */
+ #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
+ /*
+ * This setting is used when packets are coming in-order. Depending on
+ * the state of the receive context, the meta-data will carry different
+ * information.
+ */
+ #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
+ /*
+ * With this setting HW passes the TCP sequence number of the TLS
+ * record that it is requesting a resync on in the meta data.
+ */
+ #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
+ #define METADATA_BASE_MSG_MD_TYPE_LAST \
+ METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+ /*
+ * This field indicates where the next metadata block starts. It is
+ * counted in 16B units. A value of zero indicates that there is no
+ * metadata.
+ */
+ #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
+ #define METADATA_BASE_MSG_LINK_SFT 5
+ uint16_t unused0;
+ uint32_t unused1;
+} __rte_packed;
+
+/* tls_metadata_base_msg (size:64b/8B) */
+struct tls_metadata_base_msg {
+ uint32_t md_type_link_flags_kid_lo;
+ /* This field classifies the data present in the meta-data. */
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
+ UINT32_C(0x1f)
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
+ /*
+ * This setting is used when packets are coming in-order. Depending on
+ * the state of the receive context, the meta-data will carry different
+ * information.
+ */
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
+ UINT32_C(0x1)
+ /*
+ * With this setting HW passes the TCP sequence number of the TLS
+ * record that it is requesting a resync on in the meta data.
+ */
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
+ UINT32_C(0x2)
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
+ TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+ /*
+ * This field indicates where the next metadata block starts. It is
+ * counted in 16B units. A value of zero indicates that there is no
+ * metadata.
+ */
+ #define TLS_METADATA_BASE_MSG_LINK_MASK \
+ UINT32_C(0x1e0)
+ #define TLS_METADATA_BASE_MSG_LINK_SFT 5
+ /* These are flags present in the metadata. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
+ UINT32_C(0x1fffe00)
+ #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
+ /*
+ * A value of 1 implies that the packet was decrypted by HW. Otherwise
+ * the packet is passed on as it came in on the wire.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
+ UINT32_C(0x200)
+ /*
+ * This field indicates the state of the ghash field passed in the
+ * meta-data.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
+ UINT32_C(0xc00)
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
+ /*
+ * This enumeration states that the ghash is not valid in the
+ * meta-data.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
+ (UINT32_C(0x0) << 10)
+ /*
+ * This enumeration indicates that this pkt contains the record's
+ * tag and this pkt was received ooo, the partial_ghash field
+ * contains the ghash.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
+ (UINT32_C(0x1) << 10)
+ /*
+ * This enumeration indicates that the current record's tag wasn't
+ * seen and the chip is moving on to the next record, the
+ * partial_ghash field contains the ghash.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
+ (UINT32_C(0x2) << 10)
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
+ TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
+ /* This field indicates the status of tag authentication. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+ UINT32_C(0x3000)
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ /*
+ * This enumeration is set when there is no tags present in the
+ * packet.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ (UINT32_C(0x0) << 12)
+ /*
+ * This enumeration states that there is at least one tag in the
+ * packet and every tag is valid.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
+ (UINT32_C(0x1) << 12)
+ /*
+ * This enumeration states that there is at least one tag in the
+ * packet and at least one of the tag is invalid. The entire packet
+ * is sent decrypted to the host.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
+ (UINT32_C(0x2) << 12)
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+ TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
+ /*
+ * A value of 1 indicates that this packet contains a record that
+ * starts in the packet and extends beyond the packet.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
+ UINT32_C(0x4000)
+ /*
+ * This value indicates the lower 7-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
+ UINT32_C(0xfe000000)
+ #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
+ uint16_t kid_hi;
+ /*
+ * This value indicates the upper 13-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
+ #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
+ uint16_t unused0;
+} __rte_packed;
+
+/* tls_metadata_insync_msg (size:192b/24B) */
+struct tls_metadata_insync_msg {
+ uint32_t md_type_link_flags_kid_lo;
+ /* This field classifies the data present in the meta-data. */
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
+ UINT32_C(0x1f)
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
+ /*
+ * This setting is used when packets are coming in-order. Depending on
+ * the state of the receive context, the meta-data will carry different
+ * information.
+ */
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
+ UINT32_C(0x1)
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
+ TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
+ /*
+ * This field indicates where the next metadata block starts. It is
+ * counted in 16B units. A value of zero indicates that there is no
+ * metadata.
+ */
+ #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
+ UINT32_C(0x1e0)
+ #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
+ /* These are flags present in the metadata. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
+ UINT32_C(0x1fffe00)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
+ /*
+ * A value of 1 implies that the packet was decrypted by HW. Otherwise
+ * the packet is passed on as it came in on the wire.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
+ UINT32_C(0x200)
+ /*
+ * This field indicates the state of the ghash field passed in the
+ * meta-data.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
+ UINT32_C(0xc00)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
+ /*
+ * This enumeration states that the ghash is not valid in the
+ * meta-data.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
+ (UINT32_C(0x0) << 10)
+ /*
+ * This enumeration indicates that this pkt contains the record's
+ * tag and this pkt was received ooo, the partial_ghash field
+ * contains the ghash.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
+ (UINT32_C(0x1) << 10)
+ /*
+ * This enumeration indicates that the current record's tag wasn't
+ * seen and the chip is moving on to the next record, the
+ * partial_ghash field contains the ghash.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
+ (UINT32_C(0x2) << 10)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
+ TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
+ /* This field indicates the status of tag authentication. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+ UINT32_C(0x3000)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ /*
+ * This enumeration is set when there is no tags present in the
+ * packet.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ (UINT32_C(0x0) << 12)
+ /*
+ * This enumeration states that there is at least one tag in the
+ * packet and every tag is valid.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
+ (UINT32_C(0x1) << 12)
+ /*
+ * This enumeration states that there is at least one tag in the
+ * packet and at least one of the tag is invalid. The entire packet
+ * is sent decrypted to the host.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
+ (UINT32_C(0x2) << 12)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+ TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
+ /*
+ * A value of 1 indicates that this packet contains a record that
+ * starts in the packet and extends beyond the packet.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
+ UINT32_C(0x4000)
+ /*
+ * This value indicates the lower 7-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
+ UINT32_C(0xfe000000)
+ #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
+ uint16_t kid_hi;
+ /*
+ * This value indicates the upper 13-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
+ #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
+ /*
+ * This field is only valid when md_type is set to tls_insync. This field
+ * indicates the offset within the current TCP packet where the TLS header
+ * starts. If there are multiple TLS headers in the packet, this provides
+ * the offset of the last TLS header.
+ *
+ * The field is calculated by subtracting TCP sequence number of the first
+ * byte of the TCP payload of the packet from the TCP sequence number of
+ * the last TLS header in the packet.
+ */
+ uint16_t tls_header_offset;
+ /*
+ * This is the sequence Number of the record that was processed by the HW.
+ * If there are multiple records in a packet, this would be the sequence
+ * number of the last record.
+ */
+ uint64_t record_seq_num;
+ /*
+ * This field contains cumulative partial GHASH value of all the packets
+ * decrypted by the HW associated with a TLS record. This field is valid
+ * on when packets belonging to have arrived out-of-order and HW could
+ * not decrypt every packet and authenticate the record. Partial GHASH is
+ * only sent out with packet having the TAG field.
+ */
+ uint64_t partial_ghash;
+} __rte_packed;
+
+/* tls_metadata_resync_msg (size:256b/32B) */
+struct tls_metadata_resync_msg {
+ uint32_t md_type_link_flags_kid_lo;
+ /* This field classifies the data present in the meta-data. */
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
+ UINT32_C(0x1f)
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
+ /*
+ * With this setting HW passes the TCP sequence number of the TLS
+ * record that it is requesting a resync on in the meta data.
+ */
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
+ UINT32_C(0x2)
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
+ TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
+ /*
+ * This field indicates where the next metadata block starts. It is
+ * counted in 16B units. A value of zero indicates that there is no
+ * metadata.
+ */
+ #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
+ UINT32_C(0x1e0)
+ #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
+ /* These are flags present in the metadata. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
+ UINT32_C(0x1fffe00)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
+ /*
+ * A value of 1 implies that the packet was decrypted by HW. Otherwise
+ * the packet is passed on as it came in on the wire.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
+ UINT32_C(0x200)
+ /*
+ * This field indicates the state of the ghash field passed in the
+ * meta-data.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
+ UINT32_C(0xc00)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
+ /*
+ * This enumeration states that the ghash is not valid in the
+ * meta-data.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
+ (UINT32_C(0x0) << 10)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
+ TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
+ /* This field indicates the status of tag authentication. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
+ UINT32_C(0x3000)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ /*
+ * This enumeration is set when there is no tags present in the
+ * packet.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ (UINT32_C(0x0) << 12)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
+ TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
+ /*
+ * A value of 1 indicates that this packet contains a record that
+ * starts in the packet and extends beyond the packet.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
+ UINT32_C(0x4000)
+ /*
+ * This value indicates the lower 7-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
+ UINT32_C(0xfe000000)
+ #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
+ uint16_t kid_hi;
+ /*
+ * This value indicates the upper 13-bit of the Crypto Key ID
+ * associated with this operation.
+ */
+ #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
+ #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
+ /* This field is unused in this context. */
+ uint16_t metadata_0;
+ /*
+ * This field indicates the TCP sequence number of the TLS record that HW
+ * is requesting a resync on from the Driver. HW will keep a count of the
+ * TLS records it found after this record (delta_records). Driver will
+ * provide the TLS Record Sequence Number associated with the record. HW
+ * will add the delta_records to the Record Sequence Number provided by
+ * the driver and get back on sync.
+ */
+ uint32_t resync_record_tcp_seq_num;
+ uint32_t unused0;
+ /* This field is unused in this context. */
+ uint64_t metadata_2;
+ /* This field is unused in this context. */
+ uint64_t metadata_3;
+} __rte_packed;
+
/*******************
* hwrm_func_reset *
*******************/
*/
#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the num_tx_key_ctxs field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the num_rx_key_ctxs field to be
+ * configured.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \
+ UINT32_C(0x2000)
/*
* The maximum transmission unit requested on the function.
* The HWRM should make sure that the mtu of
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
UINT32_C(0x80)
+ /*
+ * If this bit is set to 1, the VF driver is requesting FW to enable
+ * PPP TX PUSH feature on all the TX rings specified in the
+ * num_tx_rings field. By default, the PPP TX push feature is
+ * disabled for all the TX rings of the VF. This flag is ignored if
+ * the num_tx_rings field is not specified or the VF doesn't support
+ * PPP tx push feature.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
+ UINT32_C(0x100)
+ /*
+ * If this bit is set to 1, the VF driver is requesting FW to disable
+ * PPP TX PUSH feature on all the TX rings of the VF. This flag is
+ * ignored if the VF doesn't support PPP tx push feature.
+ */
+ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
+ UINT32_C(0x200)
/* The number of RSS/COS contexts requested for the VF. */
uint16_t num_rsscos_ctxs;
/* The number of completion rings requested for the VF. */
uint16_t num_stat_ctxs;
/* The number of HW ring groups requested for the VF. */
uint16_t num_hw_ring_grps;
- uint8_t unused_0[4];
+ /* Number of Tx Key Contexts requested. */
+ uint16_t num_tx_key_ctxs;
+ /* Number of Rx Key Contexts requested. */
+ uint16_t num_rx_key_ctxs;
} __rte_packed;
/* hwrm_func_vf_cfg_output (size:128b/16B) */
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcaps_output (size:704b/88B) */
+/* hwrm_func_qcaps_output (size:768b/96B) */
struct hwrm_func_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
* (max_tx_rings) to the function.
*/
uint16_t max_sp_tx_rings;
- uint8_t unused_0[2];
+ /*
+ * The maximum number of MSI-X vectors that may be allocated across
+ * all VFs for the function. This is valid only on the PF with SR-IOV
+ * enabled. Returns zero if this command is called on a PF with
+ * SR-IOV disabled or on a VF.
+ */
+ uint16_t max_msix_vfs;
uint32_t flags_ext;
/*
* If 1, the device can be configured to set the ECN bits in the
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
UINT32_C(0x8)
- uint8_t unused_1[3];
+ /* If 1, the proxy mode is supported on this function */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
+ UINT32_C(0x10)
+ /*
+ * If 1, the tx rings source interface override feature is supported
+ * on this function.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
+ UINT32_C(0x20)
+ /*
+ * If 1, the device supports scheduler queues. SCHQs can be managed
+ * using RING_SCHQ_ALLOC/CFG/FREE commands.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
+ UINT32_C(0x40)
+ /*
+ * If set to 1, then this function supports the TX push mode that
+ * uses ping-pong buffers from the push pages.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * If set to 1, then this function doesn't have the privilege to
+ * configure the EVB mode of the port it uses.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * If set to 1, then the HW and FW support the SoC packet DMA
+ * datapath between SoC and NIC. This function can act as the
+ * HWRM communication transport agent on behalf of the SoC SPD
+ * software module. This capability is only advertised to the
+ * SoC PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * If set to 1, then this function supports FW_LIVEPATCH for
+ * firmware livepatch commands.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of fast Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
+ UINT32_C(0x800)
+ /*
+ * When this bit is '1', it indicates that firmware and hardware
+ * are capable of updating tx_metadata via hwrm_ring_cfg command.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
+ UINT32_C(0x1000)
+ /*
+ * If set to 1, then the device can report the action
+ * needed to activate set nvm options.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
+ UINT32_C(0x2000)
+ /*
+ * When this bit is '1', it indicates that the BD metadata feature
+ * is supported for this function.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
+ UINT32_C(0x4000)
+ /*
+ * When this bit is '1', it indicates that the echo request feature
+ * is supported for this function. If the driver registers for the
+ * echo request asynchronous event, then the firmware can send an
+ * unsolicited echo request to the driver and expect an echo
+ * response.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
+ UINT32_C(0x8000)
+ /*
+ * When this bit is '1', it indicates that core firmware supports
+ * NPAR 1.2 on this function.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \
+ UINT32_C(0x10000)
+ /* When this bit is '1', it indicates that PTM feature is supported. */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \
+ UINT32_C(0x20000)
+ /* When this bit is '1', it indicates that PPS feature is supported. */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \
+ UINT32_C(0x40000)
+ /*
+ * When this bit is '1', it indicates that VF config. change
+ * async event is supported on the parent PF if the async.
+ * event is registered by the PF.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \
+ UINT32_C(0x80000)
+ /*
+ * When this bit is '1', the NIC supports configuration of
+ * partition_min_bw and partition_max_bw. Configuration of a
+ * minimum guaranteed bandwidth is only supported if the
+ * min_bw_supported flag is also set.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \
+ UINT32_C(0x100000)
+ /*
+ * When this bit is '1', the FW supports configuration of
+ * PCP and TPID values of the default VLAN.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \
+ UINT32_C(0x200000)
+ /* When this bit is '1', it indicates that HW and FW support KTLS. */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \
+ UINT32_C(0x400000)
+ /*
+ * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG
+ * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions
+ * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive
+ * rate control. Configuration of a minimum guaranteed bandwidth
+ * is only supported if the min_bw_supported flag is also set.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \
+ UINT32_C(0x800000)
+ /*
+ * When this bit is '1', the firmware supports enforcement of
+ * minimum guaranteed bandwidth. A minimum guaranteed bandwidth
+ * could be configured for a partition or for an endpoint. Firmware
+ * only sets this flag if one or both of the ep_rate_control and
+ * partition_bw_supported flags are set.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \
+ UINT32_C(0x1000000)
+ /*
+ * When this bit is '1', HW supports TX coalesced completion
+ * records.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \
+ UINT32_C(0x2000000)
+ /*
+ * When this bit is '1', it indicates the FW has full support
+ * for all backing store types with the BACKING_STORE_CFG/QCFG
+ * V2 APIs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \
+ UINT32_C(0x4000000)
+ /*
+ * When this bit is '1', it indicates the FW forces to use the
+ * BACKING_STORE_CFG/QCFG V2 APIs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \
+ UINT32_C(0x8000000)
+ /* The maximum number of SCHQs supported by this device. */
+ uint8_t max_schqs;
+ uint8_t mpc_chnls_cap;
+ /*
+ * When this bit is '1', it indicates that HW and firmware
+ * supports the use of a MPC channel with destination set
+ * to the TX crypto engine block.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that HW and firmware
+ * supports the use of a MPC channel with destination set
+ * to the RX crypto engine block.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates that HW and firmware
+ * supports the use of a MPC channel with destination set
+ * to the TX configurable flow processing block.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates that HW and firmware
+ * supports the use of a MPC channel with destination set
+ * to the RX configurable flow processing block.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates that HW and firmware
+ * supports the use of a MPC channel with destination set
+ * to the primate processor block.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
+ /*
+ * Maximum number of Key Contexts supported per HWRM
+ * function call for allocating Key Contexts.
+ */
+ uint16_t max_key_ctxs_alloc;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcfg_output (size:768b/96B) */
+/* hwrm_func_qcfg_output (size:896b/112B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
UINT32_C(0x10)
/*
* If set to 1, then multi-host mode is active for this function.
+ * The NIC is attached to two or more independent host systems
+ * through two or more PCIe endpoints.
* If set to 0, then multi-host mode is inactive for this function
* or not applicable for this device.
*/
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
UINT32_C(0x200)
+ /*
+ * If set to 1, then the PPP tx push mode is enabled for all the
+ * reserved TX rings of this function. If set to 0, then PPP tx push
+ * mode is disabled for all the reserved TX rings of this function.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, then the firmware will notify driver using async
+ * event when a ring is disabled due to a Hardware error.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, then the firmware and all currently registered driver
+ * instances support fast reset. The fast reset support will be
+ * updated dynamically based on the driver interface advertisement.
+ * If set to 0, then the adapter is not currently able to initiate
+ * fast reset.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
+ UINT32_C(0x1000)
+ /*
+ * If set to 1, then multi-root mode is active for this function.
+ * The NIC is attached to a single host with a single operating
+ * system, but through two or more PCIe endpoints.
+ * If set to 0, then multi-root mode is inactive for this function
+ * or not applicable for this device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
+ UINT32_C(0x2000)
+ /*
+ * This flag indicates RDMA support for child VFS of
+ * a physical function.
+ * If set to 1, RoCE is supported on all child VFs.
+ * If set to 0, RoCE is disabled on all child VFs.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \
+ UINT32_C(0x4000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
/* The allocated number of vnics to the function. */
uint16_t alloc_vnics;
/*
- * The maximum transmission unit of the function.
- * If the reported mtu value is non-zero then it will used for the
- * rings allocated on this function. otherwise the default
+ * The maximum transmission unit of the function
+ * configured by the admin pf.
+ * If the reported mtu value is non-zero then it will be used for the
+ * rings allocated on this function, otherwise the default
* value is used if ring MTU is not specified.
+ * The driver cannot use any MTU bigger than this value
+ * if it is non-zero.
*/
- uint16_t mtu;
+ uint16_t admin_mtu;
/*
* The maximum receive unit of the function.
* For vnics allocated on this function, this default
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
/* Network Partitioning 2.0 */
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
+ /* Network Partitioning 1.2 */
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
/* Unknown */
#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
UINT32_C(0xff)
uint16_t dflt_vnic_id;
uint16_t max_mtu_configured;
/*
- * Minimum BW allocated for this function.
- * The HWRM will translate this value into byte counter and
- * time interval used for the scheduler inside the device.
- * A value of 0 indicates the minimum bandwidth is not
- * configured.
+ * Minimum guaranteed transmit bandwidth for this function. When
+ * specified for a PF, does not affect traffic from the PF's child VFs.
+ * A value of 0 indicates the minimum bandwidth is not configured.
*/
uint32_t min_bw;
/* The bandwidth value. */
/* Value is in Gb or GB (base 10). */
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
(UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
+ /* Value is in 1/100th of a percentage of link bandwidth. */
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
/* Invalid unit */
#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * Maximum BW allocated for this function.
- * The HWRM will translate this value into byte counter and
- * time interval used for the scheduler inside the device.
- * A value of 0 indicates that the maximum bandwidth is not
- * configured.
+ * Maximum transmit rate for this function. When specified for a PF,
+ * does not affect traffic from the PF's child VFs.
+ * A value of 0 indicates that the maximum bandwidth is not configured.
*/
uint32_t max_bw;
/* The bandwidth value. */
/* Value is in Gb or GB (base 10). */
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
(UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
+ /* Value is in 1/100th of a percentage of link bandwidth. */
#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
/* Invalid unit */
#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
/* This field specifies whether svif is valid or not */
#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
- uint8_t unused_2[7];
+ uint8_t mpc_chnls;
+ /*
+ * When this bit is '1', it indicates that a MPC channel with
+ * destination set to the TX crypto engine block is enabled.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that a MPC channel with
+ * destination set to the RX crypto engine block is enabled.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates that a MPC channel with
+ * destination set to the TX configurable flow processing block is
+ * enabled.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates that a MPC channel with
+ * destination set to the RX configurable flow processing block is
+ * enabled.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates that a MPC channel with
+ * destination set to the primate processor block is enabled.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
+ UINT32_C(0x10)
+ uint8_t unused_2[3];
+ /*
+ * Minimum guaranteed bandwidth for the network partition made up
+ * of the caller physical function and all its child virtual
+ * functions. The rate is specified as a percentage of the bandwidth
+ * of the link the partition is associated with. A value of 0
+ * indicates that no minimum bandwidth is configured.
+ * The format of this field is defined to match min_bw, even though
+ * the partition minimum rate is always specified as a percentage.
+ */
+ uint32_t partition_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
+ 0
+ /*
+ * The granularity of the value (bits or bytes). Firmware never sets
+ * this field.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES
+ /* Always percentage of link bandwidth. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Bandwidth value is in hundredths of a percent of link bandwidth. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
+ /*
+ * The maximum bandwidth that may be used by the network partition
+ * made up of the caller physical function and all its child virtual
+ * functions. The rate is specified as a percentage of the bandwidth
+ * of the link the partition is associated with. A value of 0
+ * indicates that no maximum bandwidth is configured.
+ * The format of this field is defined to match max_bw, even though
+ * the partition bandwidth must be specified as a percentage.
+ */
+ uint32_t partition_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
+ 0
+ /*
+ * The granularity of the value (bits or bytes). Firmware never sets
+ * this field.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES
+ /* Always a percentage of link bandwidth. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in hundredths of a percent of link bandwidth. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
+ /*
+ * The maximum transmission unit of the function
+ * configured by the host pf/vf.
+ * If the reported mtu value is non-zero then it will be used for the
+ * rings allocated on this function, otherwise the default
+ * value is used if ring MTU is not specified.
+ */
+ uint16_t host_mtu;
+ /* Number of Tx Key Contexts allocated. */
+ uint16_t alloc_tx_key_ctxs;
+ /* Number of Rx Key Contexts allocated. */
+ uint16_t alloc_rx_key_ctxs;
+ uint8_t unused_3[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
*****************/
-/* hwrm_func_cfg_input (size:704b/88B) */
+/* hwrm_func_cfg_input (size:896b/112B) */
struct hwrm_func_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* Function ID of the function that is being
* configured.
- * If set to 0xFF... (All Fs), then the the configuration is
+ * If set to 0xFF... (All Fs), then the configuration is
* for the requesting function.
*/
uint16_t fid;
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
UINT32_C(0x4000000)
+ /*
+ * If this bit is set to 1, the PF driver is requesting FW
+ * to enable PPP TX PUSH feature on all the TX rings specified in
+ * the num_tx_rings field. By default, the PPP TX push feature is
+ * disabled for all the TX rings of the function. This flag is
+ * ignored if num_tx_rings field is not specified or the function
+ * doesn't support PPP tx push feature.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
+ UINT32_C(0x8000000)
+ /*
+ * If this bit is set to 1, the PF driver is requesting FW
+ * to disable PPP TX PUSH feature on all the TX rings specified in
+ * the num_tx_rings field. This flag is ignored if num_tx_rings
+ * field is not specified or the function doesn't support PPP tx
+ * push feature.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
+ UINT32_C(0x10000000)
+ /*
+ * If this bit is set to 1, the driver is requesting FW to enable
+ * the BD_METADATA feature for this function. The FW returns error
+ * on this request if the TX_METADATA is enabled for this function.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
+ UINT32_C(0x20000000)
+ /*
+ * If this bit is set to 1, the driver is requesting FW to disable
+ * the BD_METADATA feature for this function. The FW returns error
+ * on this request if the TX_METADATA is enabled for this function.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
+ UINT32_C(0x40000000)
uint32_t enables;
/*
- * This bit must be '1' for the mtu field to be
+ * This bit must be '1' for the admin_mtu field to be
* configured.
*/
- #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \
UINT32_C(0x1)
/*
* This bit must be '1' for the mru field to be
#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
UINT32_C(0x800000)
/*
+ * This bit must be '1' for the schq_id field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
+ UINT32_C(0x1000000)
+ /*
+ * This bit must be '1' for the mpc_chnls field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
+ UINT32_C(0x2000000)
+ /*
+ * This bit must be '1' for the partition_min_bw field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \
+ UINT32_C(0x4000000)
+ /*
+ * This bit must be '1' for the partition_max_bw field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \
+ UINT32_C(0x8000000)
+ /*
+ * This bit must be '1' for the tpid field to be
+ * configured. This bit is only valid when dflt_vlan enable
+ * bit is set.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \
+ UINT32_C(0x10000000)
+ /*
+ * This bit must be '1' for the host_mtu field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \
+ UINT32_C(0x20000000)
+ /*
+ * This bit must be '1' for the number of Tx Key Contexts
+ * field to be configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \
+ UINT32_C(0x40000000)
+ /*
+ * This bit must be '1' for the number of Rx Key Contexts
+ * field to be configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \
+ UINT32_C(0x80000000)
+ /*
+ * This field can be used by the admin PF to configure
+ * mtu of foster PFs.
* The maximum transmission unit of the function.
* The HWRM should make sure that the mtu of
* the function does not exceed the mtu of the physical
* The HWRM should make sure that the mtu of each transmit
* ring that is assigned to a function has a valid mtu.
*/
- uint16_t mtu;
+ uint16_t admin_mtu;
/*
* The maximum receive unit of the function.
* The HWRM should make sure that the mru of
*/
uint32_t dflt_ip_addr[4];
/*
- * Minimum BW allocated for this function.
- * The HWRM will translate this value into byte counter and
- * time interval used for the scheduler inside the device.
+ * Minimum guaranteed transmit bandwidth for this function. When
+ * specified for a PF, does not affect traffic from the PF's child VFs.
+ * A value of 0 indicates the minimum bandwidth is not configured.
*/
uint32_t min_bw;
/* The bandwidth value. */
#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
/*
- * Maximum BW allocated for this function.
- * The HWRM will translate this value into byte counter and
- * time interval used for the scheduler inside the device.
+ * Maximum transmit rate for this function. When specified for a PF,
+ * does not affect traffic from the PF's child VFs.
+ * A value of 0 indicates that the maximum bandwidth is not configured.
*/
uint32_t max_bw;
/* The bandwidth value. */
*/
uint8_t allowed_vlan_pris;
/*
- * The HWRM shall allow a PF driver to change EVB mode for the
- * partition it belongs to.
- * The HWRM shall not allow a VF driver to change the EVB mode.
- * The HWRM shall take into account the switching of EVB mode
- * from one to another and reconfigure hardware resources as
- * appropriately.
- * The switching from VEB to VEPA mode requires
- * the disabling of the loopback traffic. Additionally,
- * source knock outs are handled differently in VEB and VEPA
- * modes.
+ * The evb_mode is configured on a per port basis. The default evb_mode
+ * is configured based on the NVM EVB mode setting upon firmware
+ * initialization. The HWRM allows a PF driver to change EVB mode for a
+ * port used by the PF only when one of the following conditions is
+ * satisfied.
+ * 1. The current operating mode is single function mode.
+ * (ie. one PF per port)
+ * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
+ * EVB mode of the port used by the PAXC PF. None of the X86 PFs
+ * should have privileges.
+ * The HWRM doesn't permit any PFs to change the underlying EVB mode
+ * when running as MHB or NPAR mode in performance NIC configuration.
+ * The HWRM doesn't permit a VF driver to change the EVB mode.
+ * Once the HWRM determines a function doesn't meet the conditions
+ * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
+ * flag in HWRM_FUNC_QCAPS command response for the function.
+ * The HWRM takes into account the switching of EVB mode from one to
+ * another and reconfigure hardware resources as reqiured. The
+ * switching from VEB to VEPA mode requires the disabling of the
+ * loopback traffic. Additionally, source knockouts are handled
+ * differently in VEB and VEPA modes.
*/
uint8_t evb_mode;
/* No Edge Virtual Bridging (EVB) */
* be reserved for this function on the RX side.
*/
uint16_t num_mcast_filters;
+ /* Used by a PF driver to associate a SCHQ with a VF. */
+ uint16_t schq_id;
+ uint16_t mpc_chnls;
+ /*
+ * When this bit is '1', the caller requests to enable a MPC
+ * channel with destination to the TX crypto engine block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
+ /*
+ * When this bit is '1', the caller requests to disable a MPC
+ * channel with destination to the TX crypto engine block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
+ /*
+ * When this bit is '1', the caller requests to enable a MPC
+ * channel with destination to the RX crypto engine block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
+ /*
+ * When this bit is '1', the caller requests to disable a MPC
+ * channel with destination to the RX crypto engine block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
+ /*
+ * When this bit is '1', the caller requests to enable a MPC
+ * channel with destination to the TX configurable flow processing
+ * block. When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
+ UINT32_C(0x10)
+ /*
+ * When this bit is '1', the caller requests to disable a MPC
+ * channel with destination to the TX configurable flow processing
+ * block. When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the caller requests to enable a MPC
+ * channel with destination to the RX configurable flow processing
+ * block. When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', the caller requests to disable a MPC
+ * channel with destination to the RX configurable flow processing
+ * block. When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', the caller requests to enable a MPC
+ * channel with destination to the primate processor block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', the caller requests to disable a MPC
+ * channel with destination to the primate processor block.
+ * When this bit is ‘0’, this flag has no effect.
+ */
+ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
+ UINT32_C(0x200)
+ /*
+ * Minimum guaranteed bandwidth for the network partition made up
+ * of the caller physical function and all its child virtual
+ * functions. The rate is specified as a percentage of the bandwidth
+ * of the link the partition is associated with. A value of 0
+ * indicates that no minimum bandwidth is configured. The sum of the
+ * minimum bandwidths for all partitions on a link must not exceed
+ * 100%.
+ * The format of this field is defined to match min_bw, even though
+ * it does not allow all the options for min_bw at this time.
+ */
+ uint32_t partition_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \
+ 0
+ /*
+ * The granularity of the value (bits or bytes). Firmware ignores
+ * this field.
+ */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \
+ HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES
+ /* Bandwidth units. Must be set to percent1_100. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in hundredths of a percent of link bandwidth. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
+ /*
+ * The maximum bandwidth that may be used by the network partition
+ * made up of the caller physical function and all its child virtual
+ * functions. The rate is specified as a percentage of the bandwidth
+ * of the link the partition is associated with. A value of 0
+ * indicates that no maximum bandwidth is configured.
+ * The format of this field is defined to match max_bw, even though it
+ * does not allow all the options for max_bw at this time.
+ */
+ uint32_t partition_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \
+ 0
+ /*
+ * The granularity of the value (bits or bytes). Firmware ignores
+ * this field.
+ */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \
+ HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES
+ /* Bandwidth units. Must be set to percent1_100. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in hundredths of a percent of link bandwidth. */
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
+ /*
+ * The TPID for the function for which default VLAN
+ * is configured. If the dflt_vlan is not specified
+ * with the TPID, FW returns error. If the TPID is
+ * not specified with dflt_vlan, the default TPID of
+ * 0x8100 will be used. This field is specified in
+ * network byte order.
+ */
+ uint16_t tpid;
+ /*
+ * This field can be used by the host PF to configure
+ * mtu value.
+ * The maximum transmission unit of the function.
+ * The HWRM should make sure that the mtu of
+ * the function does not exceed the mtu of the physical
+ * port that this function is associated with.
+ *
+ * In addition to configuring mtu per function, it is
+ * possible to configure mtu per transmit ring.
+ * By default, the mtu of each transmit ring associated
+ * with a function is equal to the mtu of the function.
+ * The HWRM should make sure that the mtu of each transmit
+ * ring that is assigned to a function has a valid mtu.
+ */
+ uint16_t host_mtu;
+ /* Number of Tx Key Contexts requested. */
+ uint16_t num_tx_key_ctxs;
+ /* Number of Rx Key Contexts requested. */
+ uint16_t num_rx_key_ctxs;
+ uint8_t unused_0[4];
} __rte_packed;
/* hwrm_func_cfg_output (size:128b/16B) */
uint8_t valid;
} __rte_packed;
+/* hwrm_func_cfg_cmd_err (size:64b/8B) */
+struct hwrm_func_cfg_cmd_err {
+ /* command specific error codes for the cmd_err field in hwrm_err_output */
+ uint8_t code;
+ /* Unknown error. */
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /* The partition minimum bandwidth is out of range. */
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \
+ UINT32_C(0x1)
+ /* The minimum bandwidth is more than the maximum bandwidth. */
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \
+ UINT32_C(0x2)
+ /*
+ * The NIC does not support enforcement of a minimum guaranteed
+ * bandwidth for a partition.
+ */
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \
+ UINT32_C(0x3)
+ /* Partition bandwidths must be specified as a percentage. */
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \
+ UINT32_C(0x4)
+ #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \
+ HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
+ uint8_t unused_0[7];
+} __rte_packed;
+
/********************
* hwrm_func_qstats *
********************/
************************/
-/* hwrm_func_qstats_ext_input (size:192b/24B) */
+/* hwrm_func_qstats_ext_input (size:256b/32B) */
struct hwrm_func_qstats_ext_input {
/* The HWRM command request type. */
uint16_t req_type;
#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
- uint8_t unused_0[5];
+ uint8_t unused_0[1];
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the schq_id and traffic_class fields to
+ * be configured.
+ */
+ #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
+ /* Specifies the SCHQ for which to gather statistics */
+ uint16_t schq_id;
+ /*
+ * Specifies the traffic class for which to gather statistics. Valid
+ * values are 0 through (max_configurable_queues - 1), where
+ * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
+ */
+ uint16_t traffic_class;
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_func_qstats_ext_output (size:1472b/184B) */
+/* hwrm_func_qstats_ext_output (size:1536b/192B) */
struct hwrm_func_qstats_ext_output {
/* The specific error status for the command. */
uint16_t error_code;
uint64_t rx_tpa_bytes;
/* Number of TPA errors */
uint64_t rx_tpa_errors;
+ /* Number of TPA errors */
+ uint64_t rx_tpa_events;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
UINT32_C(0x40)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * fast reset capability. Fast reset support will be used by
+ * firmware only if all the driver instances support fast reset
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fast
+ * reset flag set in event data1, then all the drivers have to tear
+ * down their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
+ UINT32_C(0x80)
+ /*
+ * When this bit is 1, the function's driver is indicating the
+ * support of handling the vnic_rss_cfg's INVALID_PARAM error
+ * returned by firmware. Firmware returns error, if host driver
+ * configures the invalid hash_types bit combination for a given
+ * IP version.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \
+ UINT32_C(0x100)
+ /*
+ * When this bit is 1, the function's driver is indicating the
+ * support of handling the NPAR 1.2 feature where the s-tag may be
+ * a value other than 0x8100 or 0x88a8.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
+ UINT32_C(0x200)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_resource_qcaps_output (size:448b/56B) */
+/* hwrm_func_resource_qcaps_output (size:512b/64B) */
struct hwrm_func_resource_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
UINT32_C(0x1)
/*
- * The PF driver should not reserve any resources for each VF until the
+ * The PF driver should not reserve any resources for each VF until
* the VF interface is brought up.
*/
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
*/
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ /* Minimum guaranteed number of Tx Key Contexts */
+ uint16_t min_tx_key_ctxs;
+ /* Maximum non-guaranteed number of Tx Key Contexts */
+ uint16_t max_tx_key_ctxs;
+ /* Minimum guaranteed number of Rx Key Contexts */
+ uint16_t min_rx_key_ctxs;
+ /* Maximum non-guaranteed number of Rx Key Contexts */
+ uint16_t max_rx_key_ctxs;
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __rte_packed;
+/*****************************
+ * hwrm_func_vf_resource_cfg *
+ *****************************/
+
+
+/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
+struct hwrm_func_vf_resource_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* VF ID that is being configured by PF */
+ uint16_t vf_id;
+ /* Maximum guaranteed number of MSI-X vectors for the function */
+ uint16_t max_msix;
+ /* Minimum guaranteed number of RSS/COS contexts */
+ uint16_t min_rsscos_ctx;
+ /* Maximum non-guaranteed number of RSS/COS contexts */
+ uint16_t max_rsscos_ctx;
+ /* Minimum guaranteed number of completion rings */
+ uint16_t min_cmpl_rings;
+ /* Maximum non-guaranteed number of completion rings */
+ uint16_t max_cmpl_rings;
+ /* Minimum guaranteed number of transmit rings */
+ uint16_t min_tx_rings;
+ /* Maximum non-guaranteed number of transmit rings */
+ uint16_t max_tx_rings;
+ /* Minimum guaranteed number of receive rings */
+ uint16_t min_rx_rings;
+ /* Maximum non-guaranteed number of receive rings */
+ uint16_t max_rx_rings;
+ /* Minimum guaranteed number of L2 contexts */
+ uint16_t min_l2_ctxs;
+ /* Maximum non-guaranteed number of L2 contexts */
+ uint16_t max_l2_ctxs;
+ /* Minimum guaranteed number of VNICs */
+ uint16_t min_vnics;
+ /* Maximum non-guaranteed number of VNICs */
+ uint16_t max_vnics;
+ /* Minimum guaranteed number of statistic contexts */
+ uint16_t min_stat_ctx;
+ /* Maximum non-guaranteed number of statistic contexts */
+ uint16_t max_stat_ctx;
+ /* Minimum guaranteed number of ring groups */
+ uint16_t min_hw_ring_grps;
+ /* Maximum non-guaranteed number of ring groups */
+ uint16_t max_hw_ring_grps;
+ uint16_t flags;
+ /*
+ * If this bit is set, all minimum resources requested should be
+ * reserved if minimum >= 1, otherwise return error. In case of
+ * error, keep all existing reservations before the call.
+ */
+ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
+ UINT32_C(0x1)
+ /* Minimum guaranteed number of Tx Key Contexts */
+ uint16_t min_tx_key_ctxs;
+ /* Maximum non-guaranteed number of Tx Key Contexts */
+ uint16_t max_tx_key_ctxs;
+ /* Minimum guaranteed number of Rx Key Contexts */
+ uint16_t min_rx_key_ctxs;
+ /* Maximum non-guaranteed number of Rx Key Contexts */
+ uint16_t max_rx_key_ctxs;
+ uint8_t unused_0[2];
+} __rte_packed;
+
+/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
+struct hwrm_func_vf_resource_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Reserved number of RSS/COS contexts */
+ uint16_t reserved_rsscos_ctx;
+ /* Reserved number of completion rings */
+ uint16_t reserved_cmpl_rings;
+ /* Reserved number of transmit rings */
+ uint16_t reserved_tx_rings;
+ /* Reserved number of receive rings */
+ uint16_t reserved_rx_rings;
+ /* Reserved number of L2 contexts */
+ uint16_t reserved_l2_ctxs;
+ /* Reserved number of VNICs */
+ uint16_t reserved_vnics;
+ /* Reserved number of statistic contexts */
+ uint16_t reserved_stat_ctx;
+ /* Reserved number of ring groups */
+ uint16_t reserved_hw_ring_grps;
+ /* Actual number of Tx Key Contexts reserved */
+ uint16_t reserved_tx_key_ctxs;
+ /* Actual number of Rx Key Contexts reserved */
+ uint16_t reserved_rx_key_ctxs;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/*********************************
* hwrm_func_backing_store_qcaps *
*********************************/
uint64_t resp_addr;
} __rte_packed;
-/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
+/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
struct hwrm_func_backing_store_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
* this many QP context entries, even if RoCE will not be used.
*/
uint16_t qp_min_qp1_entries;
- /* Maximum number of QP context entries that can be used for L2. */
+ /*
+ * Maximum number of QP context entries that can be used for L2 and
+ * mid-path.
+ */
uint16_t qp_max_l2_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t qp_entry_size;
* before the first time context load.
*/
uint8_t ctx_kind_initializer;
- /* Reserved for future. */
- uint32_t rsvd;
- /* Reserved for future. */
- uint16_t rsvd1;
+ /*
+ * Specifies which context kinds need to be initialized with the
+ * ctx_kind_initializer.
+ */
+ uint16_t ctx_init_mask;
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
+ UINT32_C(0x1)
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
+ UINT32_C(0x2)
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
+ UINT32_C(0x4)
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
+ UINT32_C(0x8)
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
+ UINT32_C(0x10)
+ /*
+ * If this bit is '1' then this context type should be initialized
+ * with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
+ UINT32_C(0x20)
+ /*
+ * If this bit is '1' then the Tx KTLS context type should be
+ * initialized with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \
+ UINT32_C(0x40)
+ /*
+ * If this bit is '1' then the Rx KTLS context type should be
+ * initialized with the ctx_kind_initializer at the specified offset.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \
+ UINT32_C(0x80)
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t qp_init_offset;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t srq_init_offset;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t cq_init_offset;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t vnic_init_offset;
/*
* Count of TQM fastpath rings to be used for allocating backing store.
* Backing store configuration must be specified for each TQM ring from
* this count in `backing_store_cfg`.
+ * Only first 8 TQM FP rings will be advertised with this field.
*/
uint8_t tqm_fp_rings_count;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t stat_init_offset;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for this
+ * context type.
+ */
+ uint8_t mrav_init_offset;
+ /*
+ * Count of TQM extended fastpath rings to be used for allocating
+ * backing store beyond 8 rings(rings 9,10,11)
+ * Backing store configuration must be specified for each TQM ring from
+ * this count in `backing_store_cfg`.
+ */
+ uint8_t tqm_fp_rings_count_ext;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for Tx
+ * KTLS context type.
+ */
+ uint8_t tkc_init_offset;
+ /*
+ * Specifies the doubleword offset of ctx_kind_initializer for Rx
+ * KTLS context type.
+ */
+ uint8_t rkc_init_offset;
+ /* Tx KTLS context entry size in bytes. */
+ uint16_t tkc_entry_size;
+ /* Rx KTLS context entry size in bytes. */
+ uint16_t rkc_entry_size;
+ /*
+ * Maximum number of Tx KTLS context entries supported for this
+ * function.
+ */
+ uint32_t tkc_max_entries;
+ /*
+ * Maximum number of Rx KTLS context entries supported for this
+ * function.
+ */
+ uint32_t rkc_max_entries;
+ /*
+ * Number of mid-path TQM rings to be used for allocating
+ * backing stores.
+ */
+ uint8_t mp_tqm_rings_count;
+ /* Reserved for future. */
+ uint8_t rsvd1[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
+/* tqm_fp_ring_cfg (size:128b/16B) */
+struct tqm_fp_ring_cfg {
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
+ TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
+ TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
+ uint8_t unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring_page_dir;
+} __rte_packed;
+
/*******************************
* hwrm_func_backing_store_cfg *
*******************************/
-/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
+/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
struct hwrm_func_backing_store_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the tqm_ring8 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
+ UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the tqm_ring9 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the tqm_ring10 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
+ UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the Tx KTLS context
+ * fields to be configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \
+ UINT32_C(0x80000)
+ /*
+ * This bit must be '1' for the Rx KTLS context
+ * fields to be configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \
+ UINT32_C(0x100000)
/* QPC page size and level. */
uint8_t qpc_pg_size_qpc_lvl;
/* QPC PBL indirect levels. */
uint16_t mrav_entry_size;
/* Number of bytes that have been allocated for each context entry. */
uint16_t tim_entry_size;
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring8_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring8_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring8_page_dir;
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring9_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring9_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring9_page_dir;
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring10_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring10_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring10_page_dir;
+ /* Number of Tx KTLS context entries allocated. */
+ uint32_t tkc_num_entries;
+ /* Number of Rx KTLS context entries allocated. */
+ uint32_t rkc_num_entries;
+ /* Tx KTLS context page directory. */
+ uint64_t tkc_page_dir;
+ /* Rx KTLS context page directory. */
+ uint64_t rkc_page_dir;
+ /* Number of bytes allocated for each Tx KTLS context entry. */
+ uint16_t tkc_entry_size;
+ /* Number of bytes allocated for each Rx KTLS context entry. */
+ uint16_t rkc_entry_size;
+ /* Tx KTLS context page size and level. */
+ uint8_t tkc_pg_size_tkc_lvl;
+ /* Tx KTLS context PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2
+ /* Tx KTLS context page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G
+ /* Rx KTLS context page size and level. */
+ uint8_t rkc_pg_size_rkc_lvl;
+ /* Rx KTLS context PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2
+ /* Rx KTLS context page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G
+ /* Reserved for future. */
+ uint8_t rsvd[2];
} __rte_packed;
/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
uint64_t resp_addr;
} __rte_packed;
-/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
+/* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */
struct hwrm_func_backing_store_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
UINT32_C(0x2)
- uint8_t unused_0[4];
+ uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
UINT32_C(0x1)
/*
* This bit must be '1' for the srq fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
UINT32_C(0x2)
/*
* This bit must be '1' for the cq fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
UINT32_C(0x4)
/*
* This bit must be '1' for the vnic fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
UINT32_C(0x8)
/*
* This bit must be '1' for the stat fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
UINT32_C(0x10)
/*
* This bit must be '1' for the tqm_sp fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
UINT32_C(0x20)
/*
* This bit must be '1' for the tqm_ring0 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
UINT32_C(0x40)
/*
* This bit must be '1' for the tqm_ring1 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
UINT32_C(0x80)
/*
* This bit must be '1' for the tqm_ring2 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
UINT32_C(0x100)
/*
* This bit must be '1' for the tqm_ring3 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
UINT32_C(0x200)
/*
* This bit must be '1' for the tqm_ring4 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
UINT32_C(0x400)
/*
* This bit must be '1' for the tqm_ring5 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
UINT32_C(0x800)
/*
* This bit must be '1' for the tqm_ring6 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
UINT32_C(0x1000)
/*
* This bit must be '1' for the tqm_ring7 fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
UINT32_C(0x2000)
/*
* This bit must be '1' for the mrav fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
UINT32_C(0x4000)
/*
* This bit must be '1' for the tim fields to be
* configured.
*/
- #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the tqm_ring8 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
+ UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the tqm_ring9 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the tqm_ring10 fields to be
+ * configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
+ UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the Tx KTLS context
+ * fields to be configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \
+ UINT32_C(0x80000)
+ /*
+ * This bit must be '1' for the Rx KTLS context
+ * fields to be configured.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \
+ UINT32_C(0x100000)
/* QPC page size and level. */
uint8_t qpc_pg_size_qpc_lvl;
/* QPC PBL indirect levels. */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
- uint8_t unused_1[7];
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring8_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring8_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring8_page_dir;
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring9_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring9_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring9_page_dir;
+ /* TQM ring page size and level. */
+ uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
+ /* TQM ring PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
+ 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
+ /* TQM ring page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
+ 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
+ uint8_t ring10_unused[3];
+ /* Number of TQM ring entries. */
+ uint32_t tqm_ring10_num_entries;
+ /* TQM ring page directory. */
+ uint64_t tqm_ring10_page_dir;
+ /* Number of Tx KTLS context entries. */
+ uint32_t tkc_num_entries;
+ /* Number of Rx KTLS context entries. */
+ uint32_t rkc_num_entries;
+ /* Tx KTLS context page directory. */
+ uint64_t tkc_page_dir;
+ /* Rx KTLS context page directory. */
+ uint64_t rkc_page_dir;
+ /* Tx KTLS context page size and level. */
+ uint8_t tkc_pg_size_tkc_lvl;
+ /* Tx KTLS context PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2
+ /* Tx KTLS context page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G
+ /* Rx KTLS context page size and level. */
+ uint8_t rkc_pg_size_rkc_lvl;
+ /* Rx KTLS context PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \
+ UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2
+ /* Rx KTLS context page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as 1
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/***************************
+ * hwrm_func_echo_response *
+ ***************************/
-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
-struct hwrm_func_vlan_qcfg_input {
+/* hwrm_func_echo_response_input (size:192b/24B) */
+struct hwrm_func_echo_response_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[6];
+ uint32_t event_data1;
+ uint32_t event_data2;
} __rte_packed;
-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
-struct hwrm_func_vlan_qcfg_output {
+/* hwrm_func_echo_response_output (size:128b/16B) */
+struct hwrm_func_echo_response_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint64_t unused_0;
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
- /*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
- /*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd2;
- /* Future use. */
- uint32_t rsvd3;
- uint8_t unused_3[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_func_vlan_cfg *
- **********************/
+/**************************
+ * hwrm_func_ptp_pin_qcfg *
+ **************************/
-/* hwrm_func_vlan_cfg_input (size:384b/48B) */
-struct hwrm_func_vlan_cfg_input {
+/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
+struct hwrm_func_ptp_pin_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[2];
- uint32_t enables;
- /*
- * This bit must be '1' for the stag_vid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
- /*
- * This bit must be '1' for the ctag_vid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
- /*
- * This bit must be '1' for the stag_pcp field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
- /*
- * This bit must be '1' for the ctag_pcp field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
- /*
- * This bit must be '1' for the stag_tpid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
- /*
- * This bit must be '1' for the ctag_tpid field to be
- * configured.
- */
- #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
- /*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
- /*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
- */
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd1;
- /* Future use. */
- uint32_t rsvd2;
- uint8_t unused_3[4];
+ uint8_t unused_0[8];
} __rte_packed;
-/* hwrm_func_vlan_cfg_output (size:128b/16B) */
-struct hwrm_func_vlan_cfg_output {
+/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
+struct hwrm_func_ptp_pin_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * The number of TSIO pins that are configured on this board
+ * Up to 4 pins can be returned in the response.
+ */
+ uint8_t num_pins;
+ /* Pin state */
+ uint8_t state;
+ /*
+ * When this bit is '1', TSIO pin 0 is enabled.
+ * When this bit is '0', TSIO pin 0 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', TSIO pin 1 is enabled.
+ * When this bit is '0', TSIO pin 1 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', TSIO pin 2 is enabled.
+ * When this bit is '0', TSIO pin 2 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', TSIO pin 3 is enabled.
+ * When this bit is '0', TSIO pin 3 is disabled.
+ */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \
+ UINT32_C(0x8)
+ /* Type of function for Pin #0. */
+ uint8_t pin0_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT
+ /* Type of function for Pin #1. */
+ uint8_t pin1_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT
+ /* Type of function for Pin #2. */
+ uint8_t pin2_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
+ /* Type of function for Pin #3. */
+ uint8_t pin3_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
+ uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*******************************
- * hwrm_func_vf_vnic_ids_query *
- *******************************/
+/*************************
+ * hwrm_func_ptp_pin_cfg *
+ *************************/
-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
-struct hwrm_func_vf_vnic_ids_query_input {
+/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
+struct hwrm_func_ptp_pin_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint32_t enables;
/*
- * This value is used to identify a Virtual Function (VF).
- * The scope of VF ID is local within a PF.
+ * This bit must be '1' for the pin0_state field to be
+ * configured.
*/
- uint16_t vf_id;
- uint8_t unused_0[2];
- /* Max number of vnic ids in vnic id table */
- uint32_t max_vnic_id_cnt;
- /* This is the address for VF VNIC ID table */
- uint64_t vnic_id_tbl_addr;
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the pin0_usage field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the pin1_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the pin1_usage field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the pin2_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the pin2_usage field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the pin3_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the pin3_usage field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \
+ UINT32_C(0x80)
+ /* Enable or disable functionality of Pin #0. */
+ uint8_t pin0_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED
+ /* Configure function for TSIO pin#0. */
+ uint8_t pin0_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #1. */
+ uint8_t pin1_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED
+ /* Configure function for TSIO pin#1. */
+ uint8_t pin1_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #2. */
+ uint8_t pin2_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED
+ /* Configure function for TSIO pin#2. */
+ uint8_t pin2_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
+ /* Enable or disable functionality of Pin #3. */
+ uint8_t pin3_state;
+ /* Disabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
+ /* Enabled */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED
+ /* Configure function for TSIO pin#3. */
+ uint8_t pin3_usage;
+ /* No function is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ /* PPS IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ /* PPS OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ /* SYNC IN is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ /* SYNC OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
-struct hwrm_func_vf_vnic_ids_query_output {
+/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_pin_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * Actual number of vnic ids
- *
- * Each VNIC ID is written as a 32-bit number.
- */
- uint32_t vnic_id_cnt;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_func_vf_bw_cfg *
- ***********************/
+/*********************
+ * hwrm_func_ptp_cfg *
+ *********************/
-/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
-struct hwrm_func_vf_bw_cfg_input {
+/* hwrm_func_ptp_cfg_input (size:320b/40B) */
+struct hwrm_func_ptp_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint16_t enables;
/*
- * The number of VF functions that are being configured.
- * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
+ * This bit must be '1' for the ptp_pps_event field to be
+ * configured.
*/
- uint16_t num_vfs;
- uint16_t unused[3];
- /* These 16-bit fields contain the VF fid and the rate scale percentage. */
- uint16_t vfn[48];
- /* The physical VF id the adjustment will be made to. */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \
+ UINT32_C(0x1)
/*
- * This field configures the rate scale percentage of the VF as specified
- * by the physical VF id.
+ * This bit must be '1' for the ptp_freq_adj_dll_source field to be
+ * configured.
*/
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
- /* 0% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
- (UINT32_C(0x0) << 12)
- /* 6.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
- (UINT32_C(0x1) << 12)
- /* 13.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
- (UINT32_C(0x2) << 12)
- /* 20% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
- (UINT32_C(0x3) << 12)
- /* 26.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
- (UINT32_C(0x4) << 12)
- /* 33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
- (UINT32_C(0x5) << 12)
- /* 40% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
- (UINT32_C(0x6) << 12)
- /* 46.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
- (UINT32_C(0x7) << 12)
- /* 53.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
- (UINT32_C(0x8) << 12)
- /* 60% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
- (UINT32_C(0x9) << 12)
- /* 66.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
- (UINT32_C(0xa) << 12)
- /* 53.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
- (UINT32_C(0xb) << 12)
- /* 80% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
- (UINT32_C(0xc) << 12)
- /* 86.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
- (UINT32_C(0xd) << 12)
- /* 93.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
- (UINT32_C(0xe) << 12)
- /* 100% of the max tx rate */
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
- (UINT32_C(0xf) << 12)
- #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
- HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_dll_phase field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_period field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_up field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ext_phase field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \
+ UINT32_C(0x20)
+ /* This field is used to enable interrupt for a specific PPS event. */
+ uint8_t ptp_pps_event;
+ /*
+ * When this bit is set to '1', interrupt is enabled for internal
+ * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does
+ * not configure PPS_OUT on a TSIO pin, then firmware will allocate
+ * PPS_OUT to an unallocated pin.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', interrupt is enabled for external
+ * PPS event. Latches timestamp on PPS_IN TSIO pin.
+ */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \
+ UINT32_C(0x2)
+ /*
+ * This field is used to set the source signal used to discipline
+ * PHC (PTP Hardware Clock)
+ */
+ uint8_t ptp_freq_adj_dll_source;
+ /* No source is selected. Use servo to discipline PHC */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \
+ UINT32_C(0x0)
+ /* TSIO Pin #0 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \
+ UINT32_C(0x1)
+ /* TSIO Pin #1 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \
+ UINT32_C(0x2)
+ /* TSIO Pin #2 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \
+ UINT32_C(0x3)
+ /* TSIO Pin #3 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \
+ UINT32_C(0x4)
+ /* Port #0 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \
+ UINT32_C(0x5)
+ /* Port #1 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \
+ UINT32_C(0x6)
+ /* Port #2 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \
+ UINT32_C(0x7)
+ /* Port #3 is selected as source signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \
+ UINT32_C(0x8)
+ /* Invalid signal. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \
+ UINT32_C(0xff)
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \
+ HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
+ /*
+ * This field is used to provide phase adjustment for DLL
+ * used to discipline PHC (PTP Hardware clock)
+ */
+ uint8_t ptp_freq_adj_dll_phase;
+ /* No Phase adjustment. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \
+ UINT32_C(0x0)
+ /* 4Khz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \
+ UINT32_C(0x1)
+ /* 8Khz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \
+ UINT32_C(0x2)
+ /* 10Mhz sync in frequency. */
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \
+ UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \
+ HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M
+ uint8_t unused_0[3];
+ /*
+ * Period in nanoseconds (ns) for external signal
+ * input.
+ */
+ uint32_t ptp_freq_adj_ext_period;
+ /*
+ * Up time in nanoseconds (ns) of the duty cycle
+ * of the external signal. This value should be
+ * less than ptp_freq_adj_ext_period.
+ */
+ uint32_t ptp_freq_adj_ext_up;
+ /*
+ * Phase value is provided. This field provides the
+ * least significant 32 bits of the phase input. The
+ * most significant 16 bits come from
+ * ptp_freq_adj_ext_phase_upper field. Setting this
+ * field requires setting ptp_freq_adj_ext_period
+ * field as well to identify the external signal
+ * pin.
+ */
+ uint32_t ptp_freq_adj_ext_phase_lower;
+ /*
+ * Phase value is provided. The lower 16 bits of this field is used
+ * with the 32 bit value from ptp_freq_adj_ext_phase_lower
+ * to provide a 48 bit value input for Phase.
+ */
+ uint32_t ptp_freq_adj_ext_phase_upper;
} __rte_packed;
-/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
-struct hwrm_func_vf_bw_cfg_output {
+/* hwrm_func_ptp_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __rte_packed;
-/************************
- * hwrm_func_vf_bw_qcfg *
- ************************/
+/**************************
+ * hwrm_func_ptp_ts_query *
+ **************************/
-/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
-struct hwrm_func_vf_bw_qcfg_input {
+/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
+struct hwrm_func_ptp_ts_query_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * The number of VF functions that are being queried.
- * The inline response space allows the host to query up to 50 VFs'
- * rate scale percentage
- */
- uint16_t num_vfs;
- uint16_t unused[3];
- /* These 16-bit fields contain the VF fid */
- uint16_t vfn[48];
- /* The physical VF id of interest */
- #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
- #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
+ uint32_t flags;
+ /* If set, the response includes PPS event timestamps */
+ #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
+ /* If set, the response includes PTM timestamps */
+ #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
-struct hwrm_func_vf_bw_qcfg_output {
+/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
+struct hwrm_func_ptp_ts_query_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * The number of VF functions that are being queried.
- * The inline response space allows the host to query up to 50 VFs' rate
- * scale percentage
- */
- uint16_t num_vfs;
- uint16_t unused[3];
- /* These 16-bit fields contain the VF fid and the rate scale percentage. */
- uint16_t vfn[48];
- /* The physical VF id the adjustment will be made to. */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
- /*
- * This field configures the rate scale percentage of the VF as specified
- * by the physical VF id.
- */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
- /* 0% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
- (UINT32_C(0x0) << 12)
- /* 6.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
- (UINT32_C(0x1) << 12)
- /* 13.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
- (UINT32_C(0x2) << 12)
- /* 20% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
- (UINT32_C(0x3) << 12)
- /* 26.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
- (UINT32_C(0x4) << 12)
- /* 33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
- (UINT32_C(0x5) << 12)
- /* 40% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
- (UINT32_C(0x6) << 12)
- /* 46.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
- (UINT32_C(0x7) << 12)
- /* 53.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
- (UINT32_C(0x8) << 12)
- /* 60% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
- (UINT32_C(0x9) << 12)
- /* 66.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
- (UINT32_C(0xa) << 12)
- /* 53.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
- (UINT32_C(0xb) << 12)
- /* 80% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
- (UINT32_C(0xc) << 12)
- /* 86.66% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
- (UINT32_C(0xd) << 12)
- /* 93.33% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
- (UINT32_C(0xe) << 12)
- /* 100% of the max tx rate */
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
- (UINT32_C(0xf) << 12)
- #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
- HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
- uint8_t unused_0[7];
+ /* Timestamp value of last PPS event latched. */
+ uint64_t pps_event_ts;
+ /* PTM local timestamp value. */
+ uint64_t ptm_res_local_ts;
+ /* PTM Master timestamp value. */
+ uint64_t ptm_pmstr_ts;
+ /* PTM Master propagation delay */
+ uint32_t ptm_mstr_prop_dly;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/***************************
- * hwrm_func_drv_if_change *
- ***************************/
+/*************************
+ * hwrm_func_ptp_ext_cfg *
+ *************************/
-/* hwrm_func_drv_if_change_input (size:192b/24B) */
-struct hwrm_func_drv_if_change_input {
+/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
+struct hwrm_func_ptp_ext_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
+ uint16_t enables;
/*
- * When this bit is '1', the function driver is indicating
- * that the IF state is changing to UP state. The call should
- * be made at the beginning of the driver's open call before
- * resources are allocated. After making the call, the driver
- * should check the response to see if any resources may have
- * changed (see the response below). If the driver fails
- * the open call, the driver should make this call again with
- * this bit cleared to indicate that the IF state is not UP.
- * During the driver's close call when the IF state is changing
- * to DOWN, the driver should make this call with the bit cleared
- * after all resources have been freed.
+ * This bit must be '1' for the phc_master_fid field to be
+ * configured.
*/
- #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
- uint32_t unused;
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the phc_sec_fid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the phc_sec_mode field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the failover_timer field to be
+ * configured.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \
+ UINT32_C(0x8)
+ /*
+ * This field is used to configure the Master function. Only this
+ * function can modify or condition the PHC. Only driver calls from
+ * this function are allowed to adjust frequency of PHC or configure
+ * PPS functionality.
+ * If driver does not specify this FID, then firmware will auto select
+ * the first function that makes the call to modify PHC as the Master.
+ */
+ uint16_t phc_master_fid;
+ /*
+ * This field is used to configure the secondary function. This
+ * function becomes the Master function in case of failover from
+ * Master function.
+ * If driver does not specify this FID, firmware will auto select
+ * the last non-master function to make a call to condition PHC as
+ * secondary.
+ */
+ uint16_t phc_sec_fid;
+ /*
+ * This field is used to configure conditions under which a function
+ * can become a secondary function.
+ */
+ uint8_t phc_sec_mode;
+ /*
+ * Immediately failover to the current secondary function. If there
+ * is no secondary function available, failover does not happen.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
+ /*
+ * All functions (PF and VF) can be used during auto selection
+ * of a secondary function. This is not used in case of admin
+ * configured secondary function.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
+ /*
+ * Only PF's can be selected as a secondary function during auto
+ * selection. This is not used in case of admin configured secondary
+ * function.
+ */
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \
+ HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY
+ uint8_t unused_0;
+ /*
+ * This field indicates the failover time is milliseconds. If the
+ * timeout expires, firmware will failover PTP configurability from
+ * current master to secondary fid.
+ * 0 - Failover timer is automatically selected based on the last
+ * adjFreq() call. If adjFreq() is not called for 3 * (last interval)
+ * the failover kicks in. For example, if last interval between
+ * adjFreq() calls was 2 seconds and the next adjFreq() is not made for
+ * at least 6 seconds, then secondary takes over as master to condition
+ * PHC. Firmware rounds up the failover timer to be a multiple of 250
+ * ms. Firmware checks every 250 ms to see if timer expired.
+ * 0xFFFFFFFF - If driver specifies this value, then failover never
+ * happens. Admin or auto selected Master will always be used for
+ * conditioning PHC.
+ * X - If driver specifies any other value, this is admin indicated
+ * failover timeout. If no adjFreq() call is made within this timeout
+ * value, then failover happens. This value should be a multiple of
+ * 250 ms. Firmware checks every 250 ms to see if timer expired.
+ */
+ uint32_t failover_timer;
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_func_drv_if_change_output (size:128b/16B) */
-struct hwrm_func_drv_if_change_output {
+/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
+struct hwrm_func_ptp_ext_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t flags;
- /*
- * When this bit is '1', it indicates that the resources reserved
- * for this function may have changed. The driver should check
- * resource capabilities and reserve resources again before
- * allocating resources.
- */
- #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
- UINT32_C(0x1)
- /*
- * When this bit is '1', it indicates that the firmware got changed / reset.
- * The driver should do complete re-initialization when that bit is set.
- */
- #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
- UINT32_C(0x2)
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*******************************
- * hwrm_func_host_pf_ids_query *
- *******************************/
+/**************************
+ * hwrm_func_ptp_ext_qcfg *
+ **************************/
-/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
-struct hwrm_func_host_pf_ids_query_input {
+/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
+struct hwrm_func_ptp_ext_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint8_t host;
- /*
- * # If this bit is set to '1', the query will contain PF(s)
- * belongs to SOC host.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
- /*
- * # If this bit is set to '1', the query will contain PF(s)
- * belongs to EP0 host.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
- /*
- * # If this bit is set to '1', the query will contain PF(s)
- * belongs to EP1 host.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
- /*
- * # If this bit is set to '1', the query will contain PF(s)
- * belongs to EP2 host.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
- /*
- * # If this bit is set to '1', the query will contain PF(s)
- * belongs to EP3 host.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
- /*
- * This provides a filter of what PF(s) will be returned in the
- * query..
- */
- uint8_t filter;
- /*
- * all available PF(s) belong to the host(s) (defined in the
- * host field). This includes the hidden PFs.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
- /*
- * all available PF(s) belong to the host(s) (defined in the
- * host field) that is available for L2 traffic.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
- /*
- * all available PF(s) belong to the host(s) (defined in the
- * host field) that is available for ROCE traffic.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
- HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
- uint8_t unused_1[6];
+ uint8_t unused_0[8];
} __rte_packed;
-/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
-struct hwrm_func_host_pf_ids_query_output {
+/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
+struct hwrm_func_ptp_ext_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This provides the first PF ID of the device. */
- uint16_t first_pf_id;
- uint16_t pf_ordinal_mask;
- /*
- * When this bit is '1', it indicates first PF belongs to one of
- * the hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
- UINT32_C(0x1)
- /*
- * When this bit is '1', it indicates 2nd PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
- UINT32_C(0x2)
- /*
- * When this bit is '1', it indicates 3rd PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
- UINT32_C(0x4)
- /*
- * When this bit is '1', it indicates 4th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
- UINT32_C(0x8)
- /*
- * When this bit is '1', it indicates 5th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
- UINT32_C(0x10)
- /*
- * When this bit is '1', it indicates 6th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
- UINT32_C(0x20)
- /*
- * When this bit is '1', it indicates 7th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
- UINT32_C(0x40)
- /*
- * When this bit is '1', it indicates 8th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
- UINT32_C(0x80)
- /*
- * When this bit is '1', it indicates 9th PF belongs to one of the
- * hosts defined in the input request.
- */
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
- UINT32_C(0x100)
/*
- * When this bit is '1', it indicates 10th PF belongs to one of the
- * hosts defined in the input request.
+ * Firmware returns the current PHC master function. This function
+ * could either be admin selected or auto selected.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
- UINT32_C(0x200)
+ uint16_t phc_master_fid;
/*
- * When this bit is '1', it indicates 11th PF belongs to one of the
- * hosts defined in the input request.
+ * Firmware returns the current PHC secondary function. This function
+ * could either be admin selected or auto selected.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
- UINT32_C(0x400)
+ uint16_t phc_sec_fid;
/*
- * When this bit is '1', it indicates 12th PF belongs to one of the
- * hosts defined in the input request.
+ * Firmware returns the last non-master/non-secondary function to
+ * make a call to condition PHC.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
- UINT32_C(0x800)
+ uint16_t phc_active_fid0;
/*
- * When this bit is '1', it indicates 13th PF belongs to one of the
- * hosts defined in the input request.
+ * Firmware returns the second last non-master/non-secondary function
+ * to make a call to condition PHC.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
- UINT32_C(0x1000)
+ uint16_t phc_active_fid1;
/*
- * When this bit is '1', it indicates 14th PF belongs to one of the
- * hosts defined in the input request.
+ * Timestamp indicating the last time a failover happened. The master
+ * and secondary functions in the failover event is indicated in the
+ * next two fields.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
- UINT32_C(0x2000)
+ uint32_t last_failover_event;
/*
- * When this bit is '1', it indicates 15th PF belongs to one of the
- * hosts defined in the input request.
+ * Last failover happened from this function. This was the master
+ * function at the time of failover.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
- UINT32_C(0x4000)
+ uint16_t from_fid;
/*
- * When this bit is '1', it indicates 16th PF belongs to one of the
- * hosts defined in the input request.
+ * Last failover happened to this function. This was the secondary
+ * function at the time of failover.
*/
- #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
- UINT32_C(0x8000)
- uint8_t unused_1[3];
+ uint16_t to_fid;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*********************
- * hwrm_port_phy_cfg *
- *********************/
+/***************************
+ * hwrm_func_key_ctx_alloc *
+ ***************************/
-/* hwrm_port_phy_cfg_input (size:448b/56B) */
-struct hwrm_port_phy_cfg_input {
+/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */
+struct hwrm_func_key_ctx_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
+ /* Function ID. */
+ uint16_t fid;
+ /* Number of Key Contexts to be allocated. */
+ uint16_t num_key_ctxs;
+ /* DMA buffer size in bytes. */
+ uint32_t dma_bufr_size_bytes;
+ /* Key Context type. */
+ uint8_t key_ctx_type;
+ /* Tx Key Context. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
+ /* Rx KTLS Context. */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
+ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \
+ HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX
+ uint8_t unused_0[7];
+ /* Host DMA address to send back KTLS context IDs. */
+ uint64_t host_dma_addr;
+} __rte_packed;
+
+/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */
+struct hwrm_func_key_ctx_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Actual number of Key Contexts allocated. */
+ uint16_t num_key_ctxs_allocated;
+ uint8_t unused_0[5];
/*
- * When this bit is set to '1', the PHY for the port shall
- * be reset.
- *
- * # If this bit is set to 1, then the HWRM shall reset the
- * PHY after applying PHY configuration changes specified
- * in this command.
- * # In order to guarantee that PHY configuration changes
- * specified in this command take effect, the HWRM
- * client should set this flag to 1.
- * # If this bit is not set to 1, then the HWRM may reset
- * the PHY depending on the current PHY configuration and
- * settings specified in this command.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
- UINT32_C(0x1)
- /* deprecated bit. Do not use!!! */
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
- UINT32_C(0x2)
+ uint8_t valid;
+} __rte_packed;
+
+/**********************************
+ * hwrm_func_backing_store_cfg_v2 *
+ **********************************/
+
+
+/* hwrm_func_backing_store_cfg_v2_input (size:320b/40B) */
+struct hwrm_func_backing_store_cfg_v2_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is set to '1', the link shall be forced to
- * the force_link_speed value.
- *
- * When this bit is set to '1', the HWRM client should
- * not enable any of the auto negotiation related
- * fields represented by auto_XXX fields in this command.
- * When this bit is set to '1' and the HWRM client has
- * enabled a auto_XXX field in this command, then the
- * HWRM shall ignore the enabled auto_XXX field.
- *
- * When this bit is set to zero, the link
- * shall be allowed to autoneg.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
- UINT32_C(0x4)
+ uint16_t cmpl_ring;
/*
- * When this bit is set to '1', the auto-negotiation process
- * shall be restarted on the link.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
- UINT32_C(0x8)
+ uint16_t seq_id;
/*
- * When this bit is set to '1', Energy Efficient Ethernet
- * (EEE) is requested to be enabled on this link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
- UINT32_C(0x10)
+ uint16_t target_id;
/*
- * When this bit is set to '1', Energy Efficient Ethernet
- * (EEE) is requested to be disabled on this link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
- UINT32_C(0x20)
+ uint64_t resp_addr;
+ /* Type of backing store to be configured. */
+ uint16_t type;
+ /* Queue pair. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \
+ UINT32_C(0x0)
+ /* Shared receive queue. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \
+ UINT32_C(0x1)
+ /* Completion queue. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \
+ UINT32_C(0x2)
+ /* Virtual NIC. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \
+ UINT32_C(0x3)
+ /* Statistic context. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \
+ UINT32_C(0x4)
+ /* Slow-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \
+ UINT32_C(0x5)
+ /* Fast-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \
+ UINT32_C(0x6)
+ /* MRAV. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \
+ UINT32_C(0xe)
+ /* TIM. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \
+ UINT32_C(0xf)
+ /* Tx key context. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \
+ UINT32_C(0x13)
+ /* Rx key context. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \
+ UINT32_C(0x14)
+ /* Mid-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \
+ UINT32_C(0x15)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING
/*
- * When this bit is set to '1' and EEE is enabled on this
- * link, then TX LPI is requested to be enabled on the link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- * If EEE is disabled on this port, then this flag shall be
- * ignored by the HWRM.
+ * Instance of the backing store type. It is zero-based,
+ * which means "0" indicates the first instance. For backing
+ * stores with single instance only, leave this field to 0.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
- UINT32_C(0x40)
+ uint16_t instance;
+ /* Control flags. */
+ uint32_t flags;
/*
- * When this bit is set to '1' and EEE is enabled on this
- * link, then TX LPI is requested to be disabled on the link.
- * If EEE is not supported on this port, then this flag
- * shall be ignored by the HWRM.
- * If EEE is disabled on this port, then this flag shall be
- * ignored by the HWRM.
+ * When set, the firmware only uses on-chip resources and
+ * does not expect any backing store to be provided by the
+ * host driver. This mode provides minimal L2 functionality
+ * (e.g. limited L2 resources, no RoCE).
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
- UINT32_C(0x80)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \
+ UINT32_C(0x1)
+ /* Page directory. */
+ uint64_t page_dir;
+ /* Number of entries */
+ uint32_t num_entries;
+ /* Number of bytes allocated for each entry */
+ uint16_t entry_size;
+ /* Page size and pbl level. */
+ uint8_t page_size_pbl_level;
+ /* PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \
+ UINT32_C(0x1)
/*
- * When set to 1, then the HWRM shall enable FEC autonegotitation
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC autonegotiation is not supported, then the HWRM shall ignore this
- * flag.
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
- UINT32_C(0x100)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2
+ /* Page size. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G
+ uint8_t rsvd;
+} __rte_packed;
+
+/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
+struct hwrm_func_backing_store_cfg_v2_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t rsvd0[7];
/*
- * When set to 1, then the HWRM shall disable FEC autonegotiation
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC autonegotiation is not supported, then the HWRM shall ignore this
- * flag.
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been completely
+ * written. When writing a command completion or response to
+ * an internal processor, the order of writes has to be such
+ * that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
- UINT32_C(0x200)
+ uint8_t valid;
+} __rte_packed;
+
+/***********************************
+ * hwrm_func_backing_store_qcfg_v2 *
+ ***********************************/
+
+
+/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
+struct hwrm_func_backing_store_qcfg_v2_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
- * flag.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
- UINT32_C(0x400)
+ uint16_t cmpl_ring;
/*
- * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
- * flag.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
- UINT32_C(0x800)
+ uint16_t seq_id;
/*
- * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
- * flag.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
- UINT32_C(0x1000)
+ uint16_t target_id;
/*
- * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
- * on this port if supported.
- * When set to 0, then this flag shall be ignored.
- * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
- * flag.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
- UINT32_C(0x2000)
+ uint64_t resp_addr;
+ /* Type of backing store to be configured. */
+ uint16_t type;
+ /* Queue pair. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \
+ UINT32_C(0x0)
+ /* Shared receive queue. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \
+ UINT32_C(0x1)
+ /* Completion queue. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \
+ UINT32_C(0x2)
+ /* Virtual NIC. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \
+ UINT32_C(0x3)
+ /* Statistic context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \
+ UINT32_C(0x4)
+ /* Slow-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \
+ UINT32_C(0x5)
+ /* Fast-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \
+ UINT32_C(0x6)
+ /* MRAV. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \
+ UINT32_C(0xe)
+ /* TIM. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \
+ UINT32_C(0xf)
+ /* Tx key context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \
+ UINT32_C(0x13)
+ /* Rx key context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \
+ UINT32_C(0x14)
+ /* Mid-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \
+ UINT32_C(0x15)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING
/*
- * When this bit is set to '1', the link shall be forced to
- * be taken down.
- *
- * # When this bit is set to '1", all other
- * command input settings related to the link speed shall
- * be ignored.
- * Once the link state is forced down, it can be
- * explicitly cleared from that state by setting this flag
- * to '0'.
- * # If this flag is set to '0', then the link shall be
- * cleared from forced down state if the link is in forced
- * down state.
- * There may be conditions (e.g. out-of-band or sideband
- * configuration changes for the link) outside the scope
- * of the HWRM implementation that may clear forced down
- * link state.
+ * Instance of the backing store type. It is zero-based,
+ * which means "0" indicates the first instance. For backing
+ * stores with single instance only, leave this field to 0.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
- UINT32_C(0x4000)
- uint32_t enables;
+ uint16_t instance;
+ uint8_t rsvd[4];
+} __rte_packed;
+
+/* hwrm_func_backing_store_qcfg_v2_output (size:256b/32B) */
+struct hwrm_func_backing_store_qcfg_v2_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Type of backing store to be configured. */
+ uint16_t type;
+ /* Queue pair. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \
+ UINT32_C(0x0)
+ /* Shared receive queue. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \
+ UINT32_C(0x1)
+ /* Completion queue. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \
+ UINT32_C(0x2)
+ /* Virtual NIC. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \
+ UINT32_C(0x3)
+ /* Statistic context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \
+ UINT32_C(0x4)
+ /* Slow-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \
+ UINT32_C(0x5)
+ /* Fast-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \
+ UINT32_C(0x6)
+ /* MRAV. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \
+ UINT32_C(0xe)
+ /* TIM. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \
+ UINT32_C(0xf)
+ /* Tx key context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \
+ UINT32_C(0x13)
+ /* Rx key context. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \
+ UINT32_C(0x14)
+ /* Mid-path TQM ring. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \
+ UINT32_C(0x15)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING
/*
- * This bit must be '1' for the auto_mode field to be
- * configured.
+ * Instance of the backing store type. It is zero-based,
+ * which means "0" indicates the first instance. For backing
+ * stores with single instance only, leave this field to 0.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
+ uint16_t instance;
+ /* Control flags. */
+ uint32_t flags;
+ /* Page directory. */
+ uint64_t page_dir;
+ /* Number of entries */
+ uint32_t num_entries;
+ /* Page size and pbl level. */
+ uint8_t page_size_pbl_level;
+ /* PBL indirect levels. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \
UINT32_C(0x1)
/*
- * This bit must be '1' for the auto_duplex field to be
- * configured.
+ * PBL pointer points to PDE table with each entry pointing to
+ * PTE tables.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \
UINT32_C(0x2)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2
+ /* Page size. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G
+ uint8_t rsvd[2];
/*
- * This bit must be '1' for the auto_pause field to be
- * configured.
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been completely
+ * written. When writing a command completion or response to
+ * an internal processor, the order of writes has to be such
+ * that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
- UINT32_C(0x4)
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
+
+
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the auto_link_speed field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
- UINT32_C(0x8)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the auto_link_speed_mask field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
- UINT32_C(0x10)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the wirespeed field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
- UINT32_C(0x20)
+ uint16_t target_id;
/*
- * This bit must be '1' for the lpbk field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
- UINT32_C(0x40)
+ uint64_t resp_addr;
/*
- * This bit must be '1' for the preemphasis field to be
+ * Function ID of the function that is being
* configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
- UINT32_C(0x80)
+ uint16_t fid;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
+struct hwrm_func_vlan_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint64_t unused_0;
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
/*
- * This bit must be '1' for the force_pause field to be
- * configured.
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
- UINT32_C(0x100)
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
/*
- * This bit must be '1' for the eee_link_speed_mask field to be
- * configured.
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
- UINT32_C(0x200)
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd2;
+ /* Future use. */
+ uint32_t rsvd3;
+ uint8_t unused_3[3];
/*
- * This bit must be '1' for the tx_lpi_timer field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
- UINT32_C(0x400)
- /* Port ID of port that is to be configured. */
- uint16_t port_id;
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_func_vlan_cfg *
+ **********************/
+
+
+/* hwrm_func_vlan_cfg_input (size:384b/48B) */
+struct hwrm_func_vlan_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This is the speed that will be used if the force
- * bit is '1'. If unsupported speed is selected, an error
- * will be generated.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t force_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
+ uint16_t cmpl_ring;
/*
- * This value is used to identify what autoneg mode is
- * used when the link speed is not being forced.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
+ uint16_t seq_id;
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
+ uint16_t target_id;
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
+ uint64_t resp_addr;
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
+ uint16_t fid;
+ uint8_t unused_0[2];
+ uint32_t enables;
/*
- * This is the duplex setting that will be used if the autoneg_mode
- * is "one_speed" or "one_or_below".
+ * This bit must be '1' for the stag_vid field to be
+ * configured.
*/
- uint8_t auto_duplex;
- /* Half Duplex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
- /* Full duplex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
- /* Both Half and Full dupex will be requested. */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
/*
- * This value is used to configure the pause that will be
- * used for autonegotiation.
- * Add text on the usage of auto_pause and force_pause.
+ * This bit must be '1' for the ctag_vid field to be
+ * configured.
*/
- uint8_t auto_pause;
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
/*
- * When this bit is '1', Generation of tx pause messages
- * has been requested. Disabled otherwise.
+ * This bit must be '1' for the stag_pcp field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
- UINT32_C(0x1)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
/*
- * When this bit is '1', Reception of rx pause messages
- * has been requested. Disabled otherwise.
+ * This bit must be '1' for the ctag_pcp field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
- UINT32_C(0x2)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
/*
- * When set to 1, the advertisement of pause is enabled.
- *
- * # When the auto_mode is not set to none and this flag is
- * set to 1, then the auto_pause bits on this port are being
- * advertised and autoneg pause results are being interpreted.
- * # When the auto_mode is not set to none and this
- * flag is set to 0, the pause is forced as indicated in
- * force_pause, and also advertised as auto_pause bits, but
- * the autoneg results are not interpreted since the pause
- * configuration is being forced.
- * # When the auto_mode is set to none and this flag is set to
- * 1, auto_pause bits should be ignored and should be set to 0.
- */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
- UINT32_C(0x4)
- uint8_t unused_0;
- /*
- * This is the speed that will be used if the autoneg_mode
- * is "one_speed" or "one_or_below". If an unsupported speed
- * is selected, an error will be generated.
- */
- uint16_t auto_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
- /*
- * This is a mask of link speeds that will be used if
- * autoneg_mode is "mask". If unsupported speed is enabled
- * an error will be generated.
+ * This bit must be '1' for the stag_tpid field to be
+ * configured.
*/
- uint16_t auto_link_speed_mask;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
- UINT32_C(0x2000)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
- UINT32_C(0x4000)
- /* This value controls the wirespeed feature. */
- uint8_t wirespeed;
- /* Wirespeed feature is disabled. */
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
- /* Wirespeed feature is enabled. */
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
- #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
- HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
- /* This value controls the loopback setting for the PHY. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * This bit must be '1' for the ctag_tpid field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
/*
- * The HW will be configured with external loopback such that
- * host data is sent on the transmitter and based on the external
- * loopback connection the data will be received without modification.
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
- #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
- HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd1;
+ /* Future use. */
+ uint32_t rsvd2;
+ uint8_t unused_3[4];
+} __rte_packed;
+
+/* hwrm_func_vlan_cfg_output (size:128b/16B) */
+struct hwrm_func_vlan_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This value is used to configure the pause that will be
- * used for force mode.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t force_pause;
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_func_vf_vnic_ids_query *
+ *******************************/
+
+
+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
+struct hwrm_func_vf_vnic_ids_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
- uint8_t unused_1;
+ uint16_t seq_id;
/*
- * This value controls the pre-emphasis to be used for the
- * link. Driver should not set this value (use
- * enable.preemphasis = 0) unless driver is sure of setting.
- * Normally HWRM FW will determine proper pre-emphasis.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint32_t preemphasis;
+ uint16_t target_id;
/*
- * Setting for link speed mask that is used to
- * advertise speeds during autonegotiation when EEE is enabled.
- * This field is valid only when EEE is enabled.
- * The speeds specified in this field shall be a subset of
- * speeds specified in auto_link_speed_mask.
- * If EEE is enabled,then at least one speed shall be provided
- * in this mask.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t eee_link_speed_mask;
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- uint8_t unused_2[2];
+ uint64_t resp_addr;
/*
- * Requested setting of TX LPI timer in microseconds.
- * This field is valid only when EEE is enabled and TX LPI is
- * enabled.
+ * This value is used to identify a Virtual Function (VF).
+ * The scope of VF ID is local within a PF.
*/
- uint32_t tx_lpi_timer;
- #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
- uint32_t unused_3;
+ uint16_t vf_id;
+ uint8_t unused_0[2];
+ /* Max number of vnic ids in vnic id table */
+ uint32_t max_vnic_id_cnt;
+ /* This is the address for VF VNIC ID table */
+ uint64_t vnic_id_tbl_addr;
} __rte_packed;
-/* hwrm_port_phy_cfg_output (size:128b/16B) */
-struct hwrm_port_phy_cfg_output {
+/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
+struct hwrm_func_vf_vnic_ids_query_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * Actual number of vnic ids
+ *
+ * Each VNIC ID is written as a 32-bit number.
+ */
+ uint32_t vnic_id_cnt;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
-struct hwrm_port_phy_cfg_cmd_err {
+/***********************
+ * hwrm_func_vf_bw_cfg *
+ ***********************/
+
+
+/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
+struct hwrm_func_vf_bw_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * command specific error codes that goes to
- * the cmd_err field in Common HWRM Error Response.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t code;
- /* Unknown error */
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
- /* Unable to complete operation due to invalid speed */
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * retry the command since the phy is not ready.
- * retry count is returned in opaque_0.
- * This is only valid for the first command and
- * this value will not change for successive calls.
- * but if a 0 is returned at any time then this should
- * be treated as an un recoverable failure,
- *
- * retry interval in milli seconds is returned in opaque_1.
- * This specifies the time that user should wait before
- * issuing the next port_phy_cfg command.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
- #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
- HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The number of VF functions that are being configured.
+ * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
+ */
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid and the rate scale percentage. */
+ uint16_t vfn[48];
+ /* The physical VF id the adjustment will be made to. */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
+ /*
+ * This field configures the rate scale percentage of the VF as specified
+ * by the physical VF id.
+ */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
+ /* 0% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
+ (UINT32_C(0x0) << 12)
+ /* 6.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
+ (UINT32_C(0x1) << 12)
+ /* 13.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
+ (UINT32_C(0x2) << 12)
+ /* 20% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
+ (UINT32_C(0x3) << 12)
+ /* 26.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
+ (UINT32_C(0x4) << 12)
+ /* 33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
+ (UINT32_C(0x5) << 12)
+ /* 40% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
+ (UINT32_C(0x6) << 12)
+ /* 46.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
+ (UINT32_C(0x7) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
+ (UINT32_C(0x8) << 12)
+ /* 60% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
+ (UINT32_C(0x9) << 12)
+ /* 66.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
+ (UINT32_C(0xa) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
+ (UINT32_C(0xb) << 12)
+ /* 80% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
+ (UINT32_C(0xc) << 12)
+ /* 86.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
+ (UINT32_C(0xd) << 12)
+ /* 93.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
+ (UINT32_C(0xe) << 12)
+ /* 100% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
+ (UINT32_C(0xf) << 12)
+ #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
+ HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
+} __rte_packed;
+
+/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
+struct hwrm_func_vf_bw_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_port_phy_qcfg *
- **********************/
+/************************
+ * hwrm_func_vf_bw_qcfg *
+ ************************/
-/* hwrm_port_phy_qcfg_input (size:192b/24B) */
-struct hwrm_port_phy_qcfg_input {
+/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
+struct hwrm_func_vf_bw_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port that is to be queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
+ /*
+ * The number of VF functions that are being queried.
+ * The inline response space allows the host to query up to 50 VFs'
+ * rate scale percentage
+ */
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid */
+ uint16_t vfn[48];
+ /* The physical VF id of interest */
+ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
} __rte_packed;
-/* hwrm_port_phy_qcfg_output (size:768b/96B) */
-struct hwrm_port_phy_qcfg_output {
+/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
+struct hwrm_func_vf_bw_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value indicates the current link status. */
- uint8_t link;
- /* There is no link or cable detected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
- /* There is no link, but a cable has been detected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
- /* There is a link. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
- uint8_t unused_0;
- /* This value indicates the current link speed of the connection. */
- uint16_t link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
- /*
- * This value is indicates the duplex of the current
- * configuration.
- */
- uint8_t duplex_cfg;
- /* Half Duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
- /* Full duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
- /*
- * This value is used to indicate the current
- * pause configuration. When autoneg is enabled, this value
- * represents the autoneg results of pause configuration.
- */
- uint8_t pause;
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * The number of VF functions that are being queried.
+ * The inline response space allows the host to query up to 50 VFs' rate
+ * scale percentage
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
+ uint16_t num_vfs;
+ uint16_t unused[3];
+ /* These 16-bit fields contain the VF fid and the rate scale percentage. */
+ uint16_t vfn[48];
+ /* The physical VF id the adjustment will be made to. */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * This field configures the rate scale percentage of the VF as specified
+ * by the physical VF id.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
- /*
- * The supported speeds for the port. This is a bit mask.
- * For each speed that is supported, the corrresponding
- * bit will be set to '1'.
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
+ /* 0% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
+ (UINT32_C(0x0) << 12)
+ /* 6.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
+ (UINT32_C(0x1) << 12)
+ /* 13.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
+ (UINT32_C(0x2) << 12)
+ /* 20% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
+ (UINT32_C(0x3) << 12)
+ /* 26.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
+ (UINT32_C(0x4) << 12)
+ /* 33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
+ (UINT32_C(0x5) << 12)
+ /* 40% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
+ (UINT32_C(0x6) << 12)
+ /* 46.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
+ (UINT32_C(0x7) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
+ (UINT32_C(0x8) << 12)
+ /* 60% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
+ (UINT32_C(0x9) << 12)
+ /* 66.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
+ (UINT32_C(0xa) << 12)
+ /* 53.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
+ (UINT32_C(0xb) << 12)
+ /* 80% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
+ (UINT32_C(0xc) << 12)
+ /* 86.66% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
+ (UINT32_C(0xd) << 12)
+ /* 93.33% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
+ (UINT32_C(0xe) << 12)
+ /* 100% of the max tx rate */
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
+ (UINT32_C(0xf) << 12)
+ #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
+ HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t support_speeds;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
- UINT32_C(0x2000)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
- UINT32_C(0x4000)
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_func_drv_if_change *
+ ***************************/
+
+
+/* hwrm_func_drv_if_change_input (size:192b/24B) */
+struct hwrm_func_drv_if_change_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Current setting of forced link speed.
- * When the link speed is not being forced, this
- * value shall be set to 0.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t force_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
- UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
- UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
- UINT32_C(0x3e8)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
- UINT32_C(0x7d0)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
- UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
- /* Current setting of auto negotiation mode. */
- uint8_t auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
+ uint16_t seq_id;
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
+ uint16_t target_id;
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
+ uint64_t resp_addr;
+ uint32_t flags;
/*
- * Current setting of pause autonegotiation.
- * Move autoneg_pause flag here.
+ * When this bit is '1', the function driver is indicating
+ * that the IF state is changing to UP state. The call should
+ * be made at the beginning of the driver's open call before
+ * resources are allocated. After making the call, the driver
+ * should check the response to see if any resources may have
+ * changed (see the response below). If the driver fails
+ * the open call, the driver should make this call again with
+ * this bit cleared to indicate that the IF state is not UP.
+ * During the driver's close call when the IF state is changing
+ * to DOWN, the driver should make this call with the bit cleared
+ * after all resources have been freed.
*/
- uint8_t auto_pause;
+ #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
+ uint32_t unused;
+} __rte_packed;
+
+/* hwrm_func_drv_if_change_output (size:128b/16B) */
+struct hwrm_func_drv_if_change_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
/*
- * When this bit is '1', Generation of tx pause messages
- * has been requested. Disabled otherwise.
+ * When this bit is '1', it indicates that the resources reserved
+ * for this function may have changed. The driver should check
+ * resource capabilities and reserve resources again before
+ * allocating resources.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
/*
- * When this bit is '1', Reception of rx pause messages
- * has been requested. Disabled otherwise.
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
UINT32_C(0x2)
+ uint8_t unused_0[3];
/*
- * When set to 1, the advertisement of pause is enabled.
- *
- * # When the auto_mode is not set to none and this flag is
- * set to 1, then the auto_pause bits on this port are being
- * advertised and autoneg pause results are being interpreted.
- * # When the auto_mode is not set to none and this
- * flag is set to 0, the pause is forced as indicated in
- * force_pause, and also advertised as auto_pause bits, but
- * the autoneg results are not interpreted since the pause
- * configuration is being forced.
- * # When the auto_mode is set to none and this flag is set to
- * 1, auto_pause bits should be ignored and should be set to 0.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
- UINT32_C(0x4)
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_func_host_pf_ids_query *
+ *******************************/
+
+
+/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
+struct hwrm_func_host_pf_ids_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Current setting for auto_link_speed. This field is only
- * valid when auto_mode is set to "one_speed" or "one_or_below".
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t auto_link_speed;
- /* 100Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
- /* 1Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
- /* 20Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
- /* 10Mb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
- UINT32_C(0xffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
+ uint16_t cmpl_ring;
/*
- * Current setting for auto_link_speed_mask that is used to
- * advertise speeds during autonegotiation.
- * This field is only valid when auto_mode is set to "mask".
- * The speeds specified in this field shall be a subset of
- * supported speeds on this port.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t auto_link_speed_mask;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t host;
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to SOC host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP0 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP1 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP2 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP3 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
+ /*
+ * This provides a filter of what PF(s) will be returned in the
+ * query..
+ */
+ uint8_t filter;
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field). This includes the hidden PFs.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field) that is available for L2 traffic.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field) that is available for ROCE traffic.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
+ HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
+ uint8_t unused_1[6];
+} __rte_packed;
+
+/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
+struct hwrm_func_host_pf_ids_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This provides the first PF ID of the device. */
+ uint16_t first_pf_id;
+ uint16_t pf_ordinal_mask;
+ /*
+ * When this bit is '1', it indicates first PF belongs to one of
+ * the hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
+ /*
+ * When this bit is '1', it indicates 2nd PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ /*
+ * When this bit is '1', it indicates 3rd PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
+ /*
+ * When this bit is '1', it indicates 4th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
+ /*
+ * When this bit is '1', it indicates 5th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
- UINT32_C(0x2000)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
- UINT32_C(0x4000)
- /* Current setting for wirespeed. */
- uint8_t wirespeed;
- /* Wirespeed feature is disabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
- /* Wirespeed feature is enabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
- /* Current setting for loopback. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * When this bit is '1', it indicates 6th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
+ UINT32_C(0x20)
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * When this bit is '1', it indicates 7th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
+ UINT32_C(0x40)
/*
- * The HW will be configured with external loopback such that
- * host data is sent on the transmitter and based on the external
- * loopback connection the data will be received without modification.
+ * When this bit is '1', it indicates 8th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
+ UINT32_C(0x80)
/*
- * Current setting of forced pause.
- * When the pause configuration is not being forced, then
- * this value shall be set to 0.
+ * When this bit is '1', it indicates 9th PF belongs to one of the
+ * hosts defined in the input request.
*/
- uint8_t force_pause;
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
+ UINT32_C(0x100)
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * When this bit is '1', it indicates 10th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
+ UINT32_C(0x200)
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * When this bit is '1', it indicates 11th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
+ UINT32_C(0x400)
/*
- * This value indicates the current status of the optics module on
- * this port.
+ * When this bit is '1', it indicates 12th PF belongs to one of the
+ * hosts defined in the input request.
*/
- uint8_t module_status;
- /* Module is inserted and accepted */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
- UINT32_C(0x0)
- /* Module is rejected and transmit side Laser is disabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
- UINT32_C(0x1)
- /* Module mismatch warning. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
- UINT32_C(0x2)
- /* Module is rejected and powered down. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
- UINT32_C(0x3)
- /* Module is not inserted. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
- UINT32_C(0x4)
- /* Module is powered down because of over current fault. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
- UINT32_C(0x5)
- /* Module status is not applicable. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
- UINT32_C(0xff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
- /* Current setting for preemphasis. */
- uint32_t preemphasis;
- /* This field represents the major version of the PHY. */
- uint8_t phy_maj;
- /* This field represents the minor version of the PHY. */
- uint8_t phy_min;
- /* This field represents the build version of the PHY. */
- uint8_t phy_bld;
- /* This value represents a PHY type. */
- uint8_t phy_type;
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* BASE-CR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
- UINT32_C(0x1)
- /* BASE-KR4 (Deprecated) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
- UINT32_C(0x2)
- /* BASE-LR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
- UINT32_C(0x3)
- /* BASE-SR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
- UINT32_C(0x4)
- /* BASE-KR2 (Deprecated) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
- UINT32_C(0x5)
- /* BASE-KX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
- UINT32_C(0x6)
- /* BASE-KR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
- UINT32_C(0x7)
- /* BASE-T */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
- UINT32_C(0x8)
- /* EEE capable BASE-T */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
- UINT32_C(0x9)
- /* SGMII connected external PHY */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
- UINT32_C(0xa)
- /* 25G_BASECR_CA_L */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
- UINT32_C(0xb)
- /* 25G_BASECR_CA_S */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
- UINT32_C(0xc)
- /* 25G_BASECR_CA_N */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
- UINT32_C(0xd)
- /* 25G_BASESR */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
- UINT32_C(0xe)
- /* 100G_BASECR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
- UINT32_C(0xf)
- /* 100G_BASESR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
- UINT32_C(0x10)
- /* 100G_BASELR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
- UINT32_C(0x11)
- /* 100G_BASEER4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
- UINT32_C(0x12)
- /* 100G_BASESR10 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
- UINT32_C(0x13)
- /* 40G_BASECR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
- UINT32_C(0x14)
- /* 40G_BASESR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
- UINT32_C(0x15)
- /* 40G_BASELR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
- UINT32_C(0x16)
- /* 40G_BASEER4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
- UINT32_C(0x17)
- /* 40G_ACTIVE_CABLE */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
- UINT32_C(0x18)
- /* 1G_baseT */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
- UINT32_C(0x19)
- /* 1G_baseSX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
- UINT32_C(0x1a)
- /* 1G_baseCX */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
- UINT32_C(0x1b)
- /* 100G_BASECR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
- UINT32_C(0x1c)
- /* 100G_BASESR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
- UINT32_C(0x1d)
- /* 100G_BASELR4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
- UINT32_C(0x1e)
- /* 100G_BASEER4 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
- UINT32_C(0x1f)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
- /* This value represents a media type. */
- uint8_t media_type;
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
- /* Twisted Pair */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
- /* Direct Attached Copper */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
- /* Fiber */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
- /* This value represents a transceiver type. */
- uint8_t xcvr_pkg_type;
- /* PHY and MAC are in the same package */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
- UINT32_C(0x1)
- /* PHY and MAC are in different packages */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
- UINT32_C(0x2)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
- uint8_t eee_config_phy_addr;
- /* This field represents PHY address. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
- UINT32_C(0x1f)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
+ UINT32_C(0x800)
/*
- * This field represents flags related to EEE configuration.
- * These EEE configuration flags are valid only when the
- * auto_mode is not set to none (in other words autonegotiation
- * is enabled).
+ * When this bit is '1', it indicates 13th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
+ UINT32_C(0x1000)
/*
- * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
- * Speeds for autoneg with EEE mode enabled
- * are based on eee_link_speed_mask.
+ * When this bit is '1', it indicates 14th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
- UINT32_C(0x20)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
+ UINT32_C(0x2000)
/*
- * This flag is valid only when eee_enabled is set to 1.
- *
- * # If eee_enabled is set to 0, then EEE mode is disabled
- * and this flag shall be ignored.
- * # If eee_enabled is set to 1 and this flag is set to 1,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * and in use.
- * # If eee_enabled is set to 1 and this flag is set to 0,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * but is currently not in use.
+ * When this bit is '1', it indicates 15th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
- UINT32_C(0x40)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
+ UINT32_C(0x4000)
/*
- * This flag is valid only when eee_enabled is set to 1.
- *
- * # If eee_enabled is set to 0, then EEE mode is disabled
- * and this flag shall be ignored.
- * # If eee_enabled is set to 1 and this flag is set to 1,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * and TX LPI is enabled.
- * # If eee_enabled is set to 1 and this flag is set to 0,
- * then Energy Efficient Ethernet (EEE) mode is enabled
- * but TX LPI is disabled.
+ * When this bit is '1', it indicates 16th PF belongs to one of the
+ * hosts defined in the input request.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
- UINT32_C(0x80)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
+ UINT32_C(0x8000)
+ uint8_t unused_1[3];
/*
- * When set to 1, the parallel detection is used to determine
- * the speed of the link partner.
- *
- * Parallel detection is used when a autonegotiation capable
- * device is connected to a link parter that is not capable
- * of autonegotiation.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t parallel_detect;
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_func_spd_cfg *
+ *********************/
+
+
+/* hwrm_func_spd_cfg_input (size:384b/48B) */
+struct hwrm_func_spd_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When set to 1, the parallel detection is used to determine
- * the speed of the link partner.
- *
- * Parallel detection is used when a autonegotiation capable
- * device is connected to a link parter that is not capable
- * of autonegotiation.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
+ uint16_t cmpl_ring;
/*
- * The advertised speeds for the port by the link partner.
- * Each advertised speed will be set to '1'.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t link_partner_adv_speeds;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
- UINT32_C(0x2000)
+ uint16_t seq_id;
/*
- * The advertised autoneg for the port by the link partner.
- * This field is deprecated and should be set to 0.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint8_t link_partner_adv_auto_mode;
- /* Disable autoneg or autoneg disabled. No speeds are selected. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
- UINT32_C(0x0)
- /* Select all possible speeds for autoneg mode. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
- UINT32_C(0x1)
+ uint16_t target_id;
/*
- * Select only the auto_link_speed speed for autoneg mode. This mode has
- * been DEPRECATED. An HWRM client should not use this mode.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
- UINT32_C(0x2)
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* Set this bit is '1' to enable the SPD datapath forwarding. */
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
+ /* Set this bit is '1' to disable the SPD datapath forwarding. */
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
/*
- * Select the auto_link_speed or any speed below that speed for autoneg.
- * This mode has been DEPRECATED. An HWRM client should not use this mode.
+ * Set this bit is '1' to enable the SPD datapath checksum
+ * feature.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
- UINT32_C(0x3)
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
/*
- * Select the speeds based on the corresponding link speed mask value
- * that is provided.
+ * Set this bit is '1' to disable the SPD datapath checksum
+ * feature.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
- UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
- /* The advertised pause settings on the port by the link partner. */
- uint8_t link_partner_adv_pause;
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
/*
- * When this bit is '1', Generation of tx pause messages
- * is supported. Disabled otherwise.
+ * Set this bit is '1' to enable the SPD datapath debug
+ * feature.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
- UINT32_C(0x1)
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
/*
- * When this bit is '1', Reception of rx pause messages
- * is supported. Disabled otherwise.
+ * Set this bit is '1' to disable the SPD datapath debug
+ * feature.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
- UINT32_C(0x2)
+ #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
+ uint32_t enables;
/*
- * Current setting for link speed mask that is used to
- * advertise speeds during autonegotiation when EEE is enabled.
- * This field is valid only when eee_enabled flags is set to 1.
- * The speeds specified in this field shall be a subset of
- * speeds specified in auto_link_speed_mask.
+ * This bit must be '1' for the ethertype field to be
+ * configured.
*/
- uint16_t adv_eee_link_speed_mask;
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
/*
- * Current setting for link speed mask that is advertised by
- * the link partner when EEE is enabled.
- * This field is valid only when eee_enabled flags is set to 1.
+ * This bit must be '1' for the hash_mode_flags field to be
+ * configured.
*/
- uint16_t link_partner_adv_eee_link_speed_mask;
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
+ #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ /*
+ * This bit must be '1' for the hash_type field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
+ /*
+ * This bit must be '1' for the ring_tbl_addr field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
- UINT32_C(0x40)
- uint32_t xcvr_identifier_type_tx_lpi_timer;
/*
- * Current setting of TX LPI timer in microseconds.
- * This field is valid only when_eee_enabled flag is set to 1
- * and tx_lpi_enabled is set to 1.
+ * This bit must be '1' for the hash_key_tbl_addr field to be
+ * configured.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
- /* This value represents transceiver identifier type. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
- /* Unknown */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
- (UINT32_C(0x0) << 24)
- /* SFP/SFP+/SFP28 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
- (UINT32_C(0x3) << 24)
- /* QSFP+ */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
- (UINT32_C(0xc) << 24)
- /* QSFP+ */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
- (UINT32_C(0xd) << 24)
- /* QSFP28 */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
- (UINT32_C(0x11) << 24)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
+ #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
+ UINT32_C(0x10)
/*
- * This value represents the current configuration of
- * Forward Error Correction (FEC) on the port.
+ * Ethertype value used in the encapsulated SPD packet header.
+ * The user must choose a value that is not conflicting with
+ * publicly defined ethertype values. By default, the ethertype
+ * value of 0xffff is used if there is no user specified value.
*/
- uint16_t fec_cfg;
+ uint16_t ethertype;
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
/*
- * When set to 1, then FEC is not supported on this port. If this flag
- * is set to 1, then all other FEC configuration flags shall be ignored.
- * When set to 0, then FEC is supported as indicated by other
- * configuration flags.
- * If no cable is attached and the HWRM does not yet know the FEC
- * capability, then the HWRM shall set this flag to 1 when reporting
- * FEC capability.
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
/*
- * When set to 1, then FEC autonegotiation is supported on this port.
- * When set to 0, then FEC autonegotiation is not supported on this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
UINT32_C(0x2)
/*
- * When set to 1, then FEC autonegotiation is enabled on this port.
- * When set to 0, then FEC autonegotiation is disabled if supported.
- * This flag should be ignored if FEC autonegotiation is not supported on this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
UINT32_C(0x4)
/*
- * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
- * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
UINT32_C(0x8)
/*
- * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
- * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
- * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
UINT32_C(0x10)
+ uint8_t unused_1;
+ uint32_t hash_type;
/*
- * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
- * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
- UINT32_C(0x20)
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
/*
- * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
- * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
- * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
*/
- #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
- UINT32_C(0x40)
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
/*
- * This value is indicates the duplex of the current
- * connection state.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
*/
- uint8_t duplex_state;
- /* Half Duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
- /* Full duplex connection. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
- #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
- /* Option flags fields. */
- uint8_t option_flags;
- /* When this bit is '1', Media auto detect is enabled. */
- #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
- UINT32_C(0x1)
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
/*
- * Up to 16 bytes of null padded ASCII string representing
- * PHY vendor.
- * If the string is set to null, then the vendor name is not
- * available.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv6
+ * packets.
*/
- char phy_vendor_name[16];
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
/*
- * Up to 16 bytes of null padded ASCII string that
- * identifies vendor specific part number of the PHY.
- * If the string is set to null, then the vendor specific
- * part number is not available.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
*/
- char phy_vendor_partnumber[16];
- uint8_t unused_2[7];
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
/*
- * This field is used in Output records to indicate that the output
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
+ */
+ #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ /* This is the address for rss ring group table */
+ uint64_t ring_grp_tbl_addr;
+ /* This is the address for rss hash key table */
+ uint64_t hash_key_tbl_addr;
+} __rte_packed;
+
+/* hwrm_func_spd_cfg_output (size:128b/16B) */
+struct hwrm_func_spd_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
uint8_t valid;
} __rte_packed;
-/*********************
- * hwrm_port_mac_cfg *
- *********************/
+/**********************
+ * hwrm_func_spd_qcfg *
+ **********************/
-/* hwrm_port_mac_cfg_input (size:384b/48B) */
-struct hwrm_port_mac_cfg_input {
+/* hwrm_func_spd_qcfg_input (size:128b/16B) */
+struct hwrm_func_spd_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_func_spd_qcfg_output (size:512b/64B) */
+struct hwrm_func_spd_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
/*
- * In this field, there are a number of CoS mappings related flags
- * that are used to configure CoS mappings and their corresponding
- * priorities in the hardware.
- * For the priorities of CoS mappings, the HWRM uses the following
- * priority order (high to low) by default:
- * # vlan pri
- * # ip_dscp
- * # tunnel_vlan_pri
- * # default cos
- *
- * A subset of CoS mappings can be enabled.
- * If a priority is not specified for an enabled CoS mapping, the
- * priority will be assigned in the above order for the enabled CoS
- * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
- * enabled and their priorities are not specified, the following
- * priority order (high to low) will be used by the HWRM:
- * # vlan_pri
- * # ip_dscp
- * # default cos
- *
- * vlan_pri CoS mapping together with default CoS with lower priority
- * are enabled by default by the HWRM.
+ * The SPD datapath forwarding is currently enabled when this
+ * flag is set to '1'.
*/
- uint32_t flags;
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
/*
- * When this bit is '1', this command will configure
- * the MAC to match the current link state of the PHY.
- * If the link is not established on the PHY, then this
- * bit has no effect.
+ * The SPD datapath checksum feature is currently enabled when
+ * this flag is set to '1'.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
+ /*
+ * The SPD datapath debug feature is currently enabled when
+ * this flag is set to '1'.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
+ uint32_t hash_type;
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv6
+ * packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ /* This is the value of rss hash key */
+ uint32_t hash_key[10];
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
+ /*
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
+ */
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is requested to be enabled.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
UINT32_C(0x2)
/*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is requested to be enabled.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
UINT32_C(0x4)
/*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * requested to be enabled.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
UINT32_C(0x8)
/*
- * When this bit is '1', the HWRM is requested to
- * enable timestamp capture capability on the receive side
- * of this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
UINT32_C(0x10)
+ uint8_t unused_1;
/*
- * When this bit is '1', the HWRM is requested to
- * disable timestamp capture capability on the receive side
- * of this port.
+ * Ethertype value used in the encapsulated SPD packet header.
+ * The user must choose a value that is not conflicting with
+ * publicly defined ethertype values. By default, the ethertype
+ * value of 0xffff is used if there is no user specified value.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
+ uint16_t ethertype;
+ uint8_t unused_2[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_port_phy_cfg *
+ *********************/
+
+
+/* hwrm_port_phy_cfg_input (size:448b/56B) */
+struct hwrm_port_phy_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When this bit is set to '1', the PHY for the port shall
+ * be reset.
+ *
+ * # If this bit is set to 1, then the HWRM shall reset the
+ * PHY after applying PHY configuration changes specified
+ * in this command.
+ * # In order to guarantee that PHY configuration changes
+ * specified in this command take effect, the HWRM
+ * client should set this flag to 1.
+ * # If this bit is not set to 1, then the HWRM may reset
+ * the PHY depending on the current PHY configuration and
+ * settings specified in this command.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
+ UINT32_C(0x1)
+ /* deprecated bit. Do not use!!! */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
+ UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', and the force_pam4_link_speed
+ * bit in the 'enables' field is '0', the link shall be forced
+ * to the force_link_speed value.
+ *
+ * When this bit is set to '1', and the force_pam4_link_speed
+ * bit in the 'enables' field is '1', the link shall be forced
+ * to the force_pam4_link_speed value.
+ *
+ * When this bit is set to '1', the HWRM client should
+ * not enable any of the auto negotiation related
+ * fields represented by auto_XXX fields in this command.
+ * When this bit is set to '1' and the HWRM client has
+ * enabled a auto_XXX field in this command, then the
+ * HWRM shall ignore the enabled auto_XXX field.
+ *
+ * When this bit is set to zero, the link
+ * shall be allowed to autoneg.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is set to '1', the auto-negotiation process
+ * shall be restarted on the link.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
+ UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', Energy Efficient Ethernet
+ * (EEE) is requested to be enabled on this link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
+ UINT32_C(0x10)
+ /*
+ * When this bit is set to '1', Energy Efficient Ethernet
+ * (EEE) is requested to be disabled on this link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
UINT32_C(0x20)
/*
- * When this bit is '1', the HWRM is requested to
- * enable timestamp capture capability on the transmit side
- * of this port.
+ * When this bit is set to '1' and EEE is enabled on this
+ * link, then TX LPI is requested to be enabled on the link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ * If EEE is disabled on this port, then this flag shall be
+ * ignored by the HWRM.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
UINT32_C(0x40)
/*
- * When this bit is '1', the HWRM is requested to
- * disable timestamp capture capability on the transmit side
- * of this port.
+ * When this bit is set to '1' and EEE is enabled on this
+ * link, then TX LPI is requested to be disabled on the link.
+ * If EEE is not supported on this port, then this flag
+ * shall be ignored by the HWRM.
+ * If EEE is disabled on this port, then this flag shall be
+ * ignored by the HWRM.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
UINT32_C(0x80)
/*
- * When this bit is '1', the Out-Of-Box WoL is requested to
- * be enabled on this port.
+ * When set to 1, then the HWRM shall enable FEC autonegotitation
+ * on this port if supported. When enabled, at least one of the
+ * FEC modes must be advertised by enabling the fec_clause_74_enable,
+ * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
+ * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
+ * of the FEC mode is currently enabled, the HWRM shall choose
+ * a default advertisement setting.
+ * The default advertisement setting can be queried by calling
+ * hwrm_port_phy_qcfg. Note that the link speed must be
+ * in autonegotiation mode for FEC autonegotiation to take effect.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC autonegotiation is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
UINT32_C(0x100)
/*
- * When this bit is '1', the Out-Of-Box WoL is requested to
- * be disabled on this port.
+ * When set to 1, then the HWRM shall disable FEC autonegotiation
+ * on this port and use forced FEC mode. In forced FEC mode, one
+ * or more FEC forced settings under the same clause can be set.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC autonegotiation is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
UINT32_C(0x200)
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is requested to be disabled.
+ * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
+ * on this port if supported, by advertising FEC CLAUSE 74 if
+ * FEC autonegotiation is enabled or force enabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
UINT32_C(0x400)
/*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is requested to be disabled.
+ * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
+ * on this port if supported, by not advertising FEC CLAUSE 74 if
+ * FEC autonegotiation is enabled or force disabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
+ * flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
UINT32_C(0x800)
/*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * requested to be disabled.
+ * When set to 1, then the HWRM shall enable FEC CLAUSE 91
+ * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
+ * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
+ * or force enabled otherwise. In forced FEC mode, this flag
+ * will only take effect if the speed is NRZ. Additional
+ * RS544 or RS272 flags (also under clause 91) may be set for PAM4
+ * in forced FEC mode.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS(528,514) is not supported, then the HWRM shall ignore
+ * this flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
UINT32_C(0x1000)
/*
- * When this bit is set to '1', and the ptp_tx_ts_capture_enable
- * bit is set, then the device uses one step Tx timestamping.
- * This bit is temporary and used for experimental purposes.
+ * When set to 1, then the HWRM shall disable FEC CLAUSE 91
+ * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
+ * not advertising RS(528,514) if FEC autonegotiation is enabled or
+ * force disabled otherwise. When set to 0, then this flag shall be
+ * ignored. If FEC RS(528,514) is not supported, then the HWRM
+ * shall ignore this flag.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
UINT32_C(0x2000)
+ /*
+ * When this bit is set to '1', the link shall be forced to
+ * be taken down.
+ *
+ * # When this bit is set to '1", all other
+ * command input settings related to the link speed shall
+ * be ignored.
+ * Once the link state is forced down, it can be
+ * explicitly cleared from that state by setting this flag
+ * to '0'.
+ * # If this flag is set to '0', then the link shall be
+ * cleared from forced down state if the link is in forced
+ * down state.
+ * There may be conditions (e.g. out-of-band or sideband
+ * configuration changes for the link) outside the scope
+ * of the HWRM implementation that may clear forced down
+ * link state.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
+ UINT32_C(0x4000)
+ /*
+ * When set to 1, then the HWRM shall enable FEC RS544_1XN
+ * on this port if supported, by advertising FEC RS544_1XN if
+ * FEC autonegotiation is enabled or force enabled otherwise.
+ * In forced mode, this flag will only take effect if the speed is
+ * PAM4. If this flag and fec_rs544_ieee_enable are set, the
+ * HWRM shall choose one of the RS544 modes.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
+ * flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
+ UINT32_C(0x8000)
+ /*
+ * When set to 1, then the HWRM shall disable FEC RS544_1XN
+ * on this port if supported, by not advertising FEC RS544_1XN if
+ * FEC autonegotiation is enabled or force disabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
+ * flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
+ UINT32_C(0x10000)
+ /*
+ * When set to 1, then the HWRM shall enable FEC RS(544,514)
+ * on this port if supported, by advertising FEC RS(544,514) if
+ * FEC autonegotiation is enabled or force enabled otherwise.
+ * In forced mode, this flag will only take effect if the speed is
+ * PAM4. If this flag and fec_rs544_1xn_enable are set, the
+ * HWRM shall choose one of the RS544 modes.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS(544,514) is not supported, then the HWRM shall ignore
+ * this flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
+ UINT32_C(0x20000)
+ /*
+ * When set to 1, then the HWRM shall disable FEC RS(544,514)
+ * on this port if supported, by not advertising FEC RS(544,514) if
+ * FEC autonegotiation is enabled or force disabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS(544,514) is not supported, then the HWRM shall ignore
+ * this flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
+ UINT32_C(0x40000)
+ /*
+ * When set to 1, then the HWRM shall enable FEC RS272_1XN
+ * on this port if supported, by advertising FEC RS272_1XN if
+ * FEC autonegotiation is enabled or force enabled otherwise.
+ * In forced mode, this flag will only take effect if the speed is
+ * PAM4. If this flag and fec_rs272_ieee_enable are set, the
+ * HWRM shall choose one of the RS272 modes. Note that RS272
+ * and RS544 modes cannot be set at the same time in forced FEC mode.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
+ * flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
+ UINT32_C(0x80000)
+ /*
+ * When set to 1, then the HWRM shall disable FEC RS272_1XN
+ * on this port if supported, by not advertising FEC RS272_1XN if
+ * FEC autonegotiation is enabled or force disabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS272_1XN is not supported, then the HWRM shall ignore
+ * this flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
+ UINT32_C(0x100000)
+ /*
+ * When set to 1, then the HWRM shall enable FEC RS(272,257)
+ * on this port if supported, by advertising FEC RS(272,257) if
+ * FEC autonegotiation is enabled or force enabled otherwise.
+ * In forced mode, this flag will only take effect if the speed is
+ * PAM4. If this flag and fec_rs272_1xn_enable are set, the
+ * HWRM shall choose one of the RS272 modes. Note that RS272
+ * and RS544 modes cannot be set at the same time in forced FEC mode.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS(272,257) is not supported, then the HWRM shall ignore
+ * this flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
+ UINT32_C(0x200000)
+ /*
+ * When set to 1, then the HWRM shall disable FEC RS(272,257)
+ * on this port if supported, by not advertising FEC RS(272,257) if
+ * FEC autonegotiation is enabled or force disabled otherwise.
+ * When set to 0, then this flag shall be ignored.
+ * If FEC RS(272,257) is not supported, then the HWRM shall ignore
+ * this flag.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
+ UINT32_C(0x400000)
uint32_t enables;
/*
- * This bit must be '1' for the ipg field to be
+ * This bit must be '1' for the auto_mode field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
UINT32_C(0x1)
/*
- * This bit must be '1' for the lpbk field to be
+ * This bit must be '1' for the auto_duplex field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
UINT32_C(0x2)
/*
- * This bit must be '1' for the vlan_pri2cos_map_pri field to be
+ * This bit must be '1' for the auto_pause field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
UINT32_C(0x4)
/*
- * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
+ * This bit must be '1' for the auto_link_speed field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the auto_link_speed_mask field to be
+ * configured.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
UINT32_C(0x10)
/*
- * This bit must be '1' for the dscp2cos_map_pri field to be
+ * This bit must be '1' for the wirespeed field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
UINT32_C(0x20)
/*
- * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
+ * This bit must be '1' for the lpbk field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
UINT32_C(0x40)
/*
- * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
+ * This bit must be '1' for the preemphasis field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
UINT32_C(0x80)
/*
- * This bit must be '1' for the cos_field_cfg field to be
+ * This bit must be '1' for the force_pause field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
UINT32_C(0x100)
/*
- * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * This bit must be '1' for the eee_link_speed_mask field to be
* configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
UINT32_C(0x200)
- /* Port ID of port that is to be configured. */
- uint16_t port_id;
/*
- * This value is used to configure the minimum IPG that will
- * be sent between packets by this port.
+ * This bit must be '1' for the tx_lpi_timer field to be
+ * configured.
*/
- uint8_t ipg;
- /* This value controls the loopback setting for the MAC. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
+ UINT32_C(0x400)
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * This bit must be '1' for the force_pam4_link_speed field to be
+ * configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
+ UINT32_C(0x800)
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * This bit must be '1' for the auto_pam4_link_speed_mask field to
+ * be configured.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
- HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
+ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
+ UINT32_C(0x1000)
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
/*
- * This value controls the priority setting of VLAN PRI to CoS
- * mapping based on VLAN Tags of inner packet headers of
- * tunneled packets or packet headers of non-tunneled packets.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * This is the speed that will be used if the force
+ * bit is '1'. If unsupported speed is selected, an error
+ * will be generated.
*/
- uint8_t vlan_pri2cos_map_pri;
- /* Reserved field. */
- uint8_t reserved1;
+ uint16_t force_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
/*
- * This value controls the priority setting of VLAN PRI to CoS
- * mapping based on VLAN Tags of tunneled header.
- * This mapping only applies when tunneled headers
- * are present.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * This value is used to identify what autoneg mode is
+ * used when the link speed is not being forced.
*/
- uint8_t tunnel_pri2cos_map_pri;
+ uint8_t auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
/*
- * This value controls the priority setting of IP DSCP to CoS
- * mapping based on inner IP header of tunneled packets or
- * IP header of non-tunneled packets.
- *
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being specified.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- uint8_t dscp2pri_map_pri;
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
/*
- * This is a 16-bit bit mask that is used to request a
- * specific configuration of time stamp capture of PTP messages
- * on the receive side of this port.
- * This field shall be ignored if the ptp_rx_ts_capture_enable
- * flag is not set in this command.
- * Otherwise, if bit 'i' is set, then the HWRM is being
- * requested to configure the receive side of the port to
- * capture the time stamp of every received PTP message
- * with messageType field value set to i.
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- uint16_t rx_ts_capture_ptp_msg_type;
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
/*
- * This is a 16-bit bit mask that is used to request a
- * specific configuration of time stamp capture of PTP messages
- * on the transmit side of this port.
- * This field shall be ignored if the ptp_tx_ts_capture_enable
- * flag is not set in this command.
- * Otherwise, if bit 'i' is set, then the HWRM is being
- * requested to configure the transmit side of the port to
- * capture the time stamp of every transmitted PTP message
- * with messageType field value set to i.
+ * Select the speeds based on the corresponding link speed mask values
+ * that are provided. The included speeds are specified in the
+ * auto_link_speed and auto_pam4_link_speed fields.
*/
- uint16_t tx_ts_capture_ptp_msg_type;
- /* Configuration of CoS fields. */
- uint8_t cos_field_cfg;
- /* Reserved */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
+ /*
+ * This is the duplex setting that will be used if the autoneg_mode
+ * is "one_speed" or "one_or_below".
+ */
+ uint8_t auto_duplex;
+ /* Half Duplex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
+ /* Full duplex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
+ /* Both Half and Full duplex will be requested. */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
+ /*
+ * This value is used to configure the pause that will be
+ * used for autonegotiation.
+ * Add text on the usage of auto_pause and force_pause.
+ */
+ uint8_t auto_pause;
+ /*
+ * When this bit is '1', Generation of tx pause messages
+ * has been requested. Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
UINT32_C(0x1)
/*
- * This field is used to specify selection of VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the inner packet headers of tunneled packets or
- * non-tunneled packets.
- * This field is valid only if inner VLAN PRI to CoS mapping
- * is enabled.
- * If VLAN PRI to CoS mapping is not enabled, then this
- * field shall be ignored.
+ * When this bit is '1', Reception of rx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
- UINT32_C(0x6)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
- 1
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
+ UINT32_C(0x2)
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the inner packet headers
+ * When set to 1, the advertisement of pause is enabled.
+ *
+ * # When the auto_mode is not set to none and this flag is
+ * set to 1, then the auto_pause bits on this port are being
+ * advertised and autoneg pause results are being interpreted.
+ * # When the auto_mode is not set to none and this
+ * flag is set to 0, the pause is forced as indicated in
+ * force_pause, and also advertised as auto_pause bits, but
+ * the autoneg results are not interpreted since the pause
+ * configuration is being forced.
+ * # When the auto_mode is set to none and this flag is set to
+ * 1, auto_pause bits should be ignored and should be set to 0.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 1)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
+ UINT32_C(0x4)
+ uint8_t unused_0;
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the inner packet headers.
- * No VLAN PRI shall be selected for this configuration
- * if only one VLAN Tag is present in the inner
- * packet headers.
+ * This is the speed that will be used if the autoneg_mode
+ * is "one_speed" or "one_or_below". If an unsupported speed
+ * is selected, an error will be generated.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 1)
+ uint16_t auto_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the inner packet headers
+ * This is a mask of link speeds that will be used if
+ * autoneg_mode is "mask". If unsupported speed is enabled
+ * an error will be generated.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 1)
- /* Unspecified */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 1)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
+ uint16_t auto_link_speed_mask;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
+ UINT32_C(0x2000)
+ /* This value controls the wirespeed feature. */
+ uint8_t wirespeed;
+ /* Wirespeed feature is disabled. */
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
+ /* Wirespeed feature is enabled. */
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
+ /* This value controls the loopback setting for the PHY. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
/*
- * This field is used to specify selection of tunnel VLAN
- * PRI value based on whether one or two VLAN Tags are
- * present in tunnel headers.
- * This field is valid only if tunnel VLAN PRI to CoS mapping
- * is enabled.
- * If tunnel VLAN PRI to CoS mapping is not enabled, then this
- * field shall be ignored.
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
- UINT32_C(0x18)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
- 3
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the tunnel packet headers
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 3)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the tunnel packet headers.
- * No tunnel VLAN PRI shall be selected for this
- * configuration if only one VLAN Tag is present in
- * the tunnel packet headers.
+ * The HW will be configured with external loopback such that
+ * host data is sent on the transmitter and based on the external
+ * loopback connection the data will be received without modification.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 3)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
+ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the tunnel packet headers
+ * This value is used to configure the pause that will be
+ * used for force mode.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 3)
- /* Unspecified */
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 3)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ uint8_t force_pause;
/*
- * This field shall be used to provide default CoS value
- * that has been configured on this port.
- * This field is valid only if default CoS mapping
- * is enabled.
- * If default CoS mapping is not enabled, then this
- * field shall be ignored.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
- 5
- uint8_t unused_0[3];
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
/*
- * This signed field specifies by how much to adjust the frequency
- * of sync timer updates (measured in parts per billion).
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- int32_t ptp_freq_adj_ppb;
- uint8_t unused_1[4];
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
+ uint8_t unused_1;
+ /*
+ * This value controls the pre-emphasis to be used for the
+ * link. Driver should not set this value (use
+ * enable.preemphasis = 0) unless driver is sure of setting.
+ * Normally HWRM FW will determine proper pre-emphasis.
+ */
+ uint32_t preemphasis;
+ /*
+ * Setting for link speed mask that is used to
+ * advertise speeds during autonegotiation when EEE is enabled.
+ * This field is valid only when EEE is enabled.
+ * The speeds specified in this field shall be a subset of
+ * speeds specified in auto_link_speed_mask.
+ * If EEE is enabled,then at least one speed shall be provided
+ * in this mask.
+ */
+ uint16_t eee_link_speed_mask;
+ /* Reserved */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ /*
+ * This is the speed that will be used if the force and force_pam4
+ * bits are '1'. If unsupported speed is selected, an error
+ * will be generated.
+ */
+ uint16_t force_pam4_link_speed;
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
+ UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
+ UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
+ /*
+ * Requested setting of TX LPI timer in microseconds.
+ * This field is valid only when EEE is enabled and TX LPI is
+ * enabled.
+ */
+ uint32_t tx_lpi_timer;
+ #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
+ /* This field specifies which PAM4 speeds are enabled for auto mode. */
+ uint16_t auto_link_pam4_speed_mask;
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
+ UINT32_C(0x1)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
+ UINT32_C(0x4)
+ uint8_t unused_2[2];
} __rte_packed;
-/* hwrm_port_mac_cfg_output (size:128b/16B) */
-struct hwrm_port_mac_cfg_output {
+/* hwrm_port_phy_cfg_output (size:128b/16B) */
+struct hwrm_port_phy_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be received on the port.
- * This value does not include the number of bytes used by
- * Ethernet header and trailer (CRC).
- */
- uint16_t mru;
- /*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be transmitted on the port.
- * This value does not include the number of bytes used by
- * Ethernet header and trailer (CRC).
- */
- uint16_t mtu;
- /* Current configuration of the IPG value. */
- uint8_t ipg;
- /* Current value of the loopback value. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
- /*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
- */
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
- /*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
- */
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
- uint8_t unused_0;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
+/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
+struct hwrm_port_phy_cfg_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* Unable to complete operation due to invalid speed */
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
+ /*
+ * retry the command since the phy is not ready.
+ * retry count is returned in opaque_0.
+ * This is only valid for the first command and
+ * this value will not change for successive calls.
+ * but if a 0 is returned at any time then this should
+ * be treated as an un recoverable failure,
+ *
+ * retry interval in milli seconds is returned in opaque_1.
+ * This specifies the time that user should wait before
+ * issuing the next port_phy_cfg command.
+ */
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
+ #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
+ HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
+ uint8_t unused_0[7];
+} __rte_packed;
+
/**********************
- * hwrm_port_mac_qcfg *
+ * hwrm_port_phy_qcfg *
**********************/
-/* hwrm_port_mac_qcfg_input (size:192b/24B) */
-struct hwrm_port_mac_qcfg_input {
+/* hwrm_port_phy_qcfg_input (size:192b/24B) */
+struct hwrm_port_phy_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port that is to be configured. */
+ /* Port ID of port that is to be queried. */
uint16_t port_id;
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_mac_qcfg_output (size:256b/32B) */
-struct hwrm_port_mac_qcfg_output {
+/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+struct hwrm_port_phy_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* This value indicates the current link status. */
+ uint8_t link;
+ /* There is no link or cable detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
+ /* There is no link, but a cable has been detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
+ /* There is a link. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
+ uint8_t active_fec_signal_mode;
/*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be received on the port.
- * This value does not include the number of bytes used by the
- * Ethernet header and trailer (CRC).
- */
- uint16_t mru;
- /*
- * This is the configured maximum length of Ethernet packet
- * payload that is allowed to be transmitted on the port.
- * This value does not include the number of bytes used by the
- * Ethernet header and trailer (CRC).
+ * This value indicates the current link signaling mode of the
+ * connection.
*/
- uint16_t mtu;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
+ UINT32_C(0xf)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
+ /* NRZ signaling */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
+ UINT32_C(0x0)
+ /* PAM4 signaling */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
+ UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
+ /* This value indicates the current active FEC mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
+ /* No active FEC */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
+ (UINT32_C(0x0) << 4)
+ /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
+ (UINT32_C(0x1) << 4)
+ /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
+ (UINT32_C(0x2) << 4)
+ /* FEC RS544_1XN active, autonegoatiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
+ (UINT32_C(0x3) << 4)
+ /* FEC RS(544,528) active, autonegoatiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
+ (UINT32_C(0x4) << 4)
+ /* FEC RS272_1XN active, autonegotiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
+ (UINT32_C(0x5) << 4)
+ /* FEC RS(272,257) active, autonegoatiated or forced. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
+ (UINT32_C(0x6) << 4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
/*
- * The minimum IPG that will
- * be sent between packets by this port.
+ * This value indicates the current link speed of the connection.
+ * The signal_mode field indicates if the link is using
+ * NRZ or PAM4 signaling.
*/
- uint8_t ipg;
- /* The loopback setting for the MAC. */
- uint8_t lpbk;
- /* No loopback is selected. Normal operation. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
+ uint16_t link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
/*
- * The HW will be configured with local loopback such that
- * host data is sent back to the host without modification.
+ * This value is indicates the duplex of the current
+ * configuration.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
+ uint8_t duplex_cfg;
+ /* Half Duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
+ /* Full duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
/*
- * The HW will be configured with remote loopback such that
- * port logic will send packets back out the transmitter that
- * are received.
+ * This value is used to indicate the current
+ * pause configuration. When autoneg is enabled, this value
+ * represents the autoneg results of pause configuration.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
+ uint8_t pause;
/*
- * Priority setting for VLAN PRI to CoS mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- uint8_t vlan_pri2cos_map_pri;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
/*
- * In this field, a number of CoS mappings related flags
- * are used to indicate configured CoS mappings.
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- uint8_t flags;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
/*
- * When this bit is set to '1', the inner VLAN PRI to CoS mapping
- * is enabled.
+ * The supported speeds for the port. This is a bit mask.
+ * For each speed that is supported, the corresponding
+ * bit will be set to '1'.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ uint16_t support_speeds;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
UINT32_C(0x1)
- /*
- * When this bit is set to '1', tunnel VLAN PRI field to
- * CoS mapping is enabled.
- */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
UINT32_C(0x2)
- /*
- * When this bit is set to '1', the IP DSCP to CoS mapping is
- * enabled.
- */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
UINT32_C(0x4)
- /*
- * When this bit is '1', the Out-Of-Box WoL is enabled on this
- * port.
- */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
UINT32_C(0x8)
- /* When this bit is '1', PTP is enabled for RX on this port. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
UINT32_C(0x10)
- /* When this bit is '1', PTP is enabled for TX on this port. */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
+ UINT32_C(0x2000)
/*
- * Priority setting for tunnel VLAN PRI to CoS mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
- */
- uint8_t tunnel_pri2cos_map_pri;
- /*
- * Priority setting for DSCP to PRI mapping.
- * # Each XXX_pri variable shall have a unique priority value
- * when it is being used.
- * # When comparing priorities of mappings, higher value
- * indicates higher priority.
- * For example, a value of 0-3 is returned where 0 is being
- * the lowest priority and 3 is being the highest priority.
- * # If the correspoding CoS mapping is not enabled, then this
- * field should be ignored.
- * # This value indicates the normalized priority value retained
- * in the HWRM.
- */
- uint8_t dscp2pri_map_pri;
- /*
- * This is a 16-bit bit mask that represents the
- * current configuration of time stamp capture of PTP messages
- * on the receive side of this port.
- * If bit 'i' is set, then the receive side of the port
- * is configured to capture the time stamp of every
- * received PTP message with messageType field value set
- * to i.
- * If all bits are set to 0 (i.e. field value set 0),
- * then the receive side of the port is not configured
- * to capture timestamp for PTP messages.
- * If all bits are set to 1, then the receive side of the
- * port is configured to capture timestamp for all PTP
- * messages.
- */
- uint16_t rx_ts_capture_ptp_msg_type;
- /*
- * This is a 16-bit bit mask that represents the
- * current configuration of time stamp capture of PTP messages
- * on the transmit side of this port.
- * If bit 'i' is set, then the transmit side of the port
- * is configured to capture the time stamp of every
- * received PTP message with messageType field value set
- * to i.
- * If all bits are set to 0 (i.e. field value set 0),
- * then the transmit side of the port is not configured
- * to capture timestamp for PTP messages.
- * If all bits are set to 1, then the transmit side of the
- * port is configured to capture timestamp for all PTP
- * messages.
- */
- uint16_t tx_ts_capture_ptp_msg_type;
- /* Configuration of CoS fields. */
- uint8_t cos_field_cfg;
- /* Reserved */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
- UINT32_C(0x1)
- /*
- * This field is used for selecting VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the inner packet headers of tunneled packets or
- * non-tunneled packets.
+ * Current setting of forced link speed.
+ * When the link speed is not being forced, this
+ * value shall be set to 0.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
- UINT32_C(0x6)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
- 1
+ uint16_t force_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
+ UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
+ UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
+ UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
+ UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
+ /* Current setting of auto negotiation mode. */
+ uint8_t auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the inner packet headers
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the inner packet headers.
- * No VLAN PRI is selected for this configuration
- * if only one VLAN Tag is present in the inner
- * packet headers.
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the inner packet headers
+ * Select the speeds based on the corresponding link speed mask value
+ * that is provided.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 1)
- /* Unspecified */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 1)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
/*
- * This field is used for selecting tunnel VLAN PRI value
- * based on whether one or two VLAN Tags are present in
- * the tunnel headers of tunneled packets. This selection
- * does not apply to non-tunneled packets.
+ * Current setting of pause autonegotiation.
+ * Move autoneg_pause flag here.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
- UINT32_C(0x18)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
- 3
+ uint8_t auto_pause;
/*
- * Select inner VLAN PRI when 1 or 2 VLAN Tags are
- * present in the tunnel packet headers
+ * When this bit is '1', Generation of tx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
- (UINT32_C(0x0) << 3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
+ UINT32_C(0x1)
/*
- * Select outer VLAN Tag PRI when 2 VLAN Tags are
- * present in the tunnel packet headers.
- * No VLAN PRI is selected for this configuration
- * if only one VLAN Tag is present in the tunnel
- * packet headers.
+ * When this bit is '1', Reception of rx pause messages
+ * has been requested. Disabled otherwise.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
- (UINT32_C(0x1) << 3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
+ UINT32_C(0x2)
/*
- * Select outermost VLAN PRI when 1 or 2 VLAN Tags
- * are present in the tunnel packet headers
+ * When set to 1, the advertisement of pause is enabled.
+ *
+ * # When the auto_mode is not set to none and this flag is
+ * set to 1, then the auto_pause bits on this port are being
+ * advertised and autoneg pause results are being interpreted.
+ * # When the auto_mode is not set to none and this
+ * flag is set to 0, the pause is forced as indicated in
+ * force_pause, and also advertised as auto_pause bits, but
+ * the autoneg results are not interpreted since the pause
+ * configuration is being forced.
+ * # When the auto_mode is set to none and this flag is set to
+ * 1, auto_pause bits should be ignored and should be set to 0.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
- (UINT32_C(0x2) << 3)
- /* Unspecified */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
- (UINT32_C(0x3) << 3)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
- HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
+ UINT32_C(0x4)
/*
- * This field is used to provide default CoS value that
- * has been configured on this port.
+ * Current setting for auto_link_speed. This field is only
+ * valid when auto_mode is set to "one_speed" or "one_or_below".
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
- UINT32_C(0xe0)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
- 5
- uint8_t unused_1;
- uint16_t port_svif_info;
+ uint16_t auto_link_speed;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
+ UINT32_C(0xffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
/*
- * This field specifies the source virtual interface of the port being
- * queried. Drivers can use this to program port svif field in the
- * L2 context table
+ * Current setting for auto_link_speed_mask that is used to
+ * advertise speeds during autonegotiation.
+ * This field is only valid when auto_mode is set to "mask".
+ * The speeds specified in this field shall be a subset of
+ * supported speeds on this port.
*/
- #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
- UINT32_C(0x7fff)
- #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
- /* This field specifies whether port_svif is valid or not */
- #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
- UINT32_C(0x8000)
- uint8_t unused_2[5];
+ uint16_t auto_link_speed_mask;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
+ UINT32_C(0x2000)
+ /* Current setting for wirespeed. */
+ uint8_t wirespeed;
+ /* Wirespeed feature is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
+ /* Wirespeed feature is enabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
+ /* Current setting for loopback. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint8_t valid;
-} __rte_packed;
-
-/**************************
- * hwrm_port_mac_ptp_qcfg *
- **************************/
-
-
-/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
-struct hwrm_port_mac_ptp_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * The HW will be configured with external loopback such that
+ * host data is sent on the transmitter and based on the external
+ * loopback connection the data will be received without modification.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Current setting of forced pause.
+ * When the pause configuration is not being forced, then
+ * this value shall be set to 0.
*/
- uint16_t target_id;
+ uint8_t force_pause;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
-} __rte_packed;
-
-/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
-struct hwrm_port_mac_ptp_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
/*
- * In this field, a number of PTP related flags
- * are used to indicate configured PTP capabilities.
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- uint8_t flags;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
/*
- * When this bit is set to '1', the PTP related registers are
- * directly accessible by the host.
+ * This value indicates the current status of the optics module on
+ * this port.
*/
- #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
+ uint8_t module_status;
+ /* Module is inserted and accepted */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
+ UINT32_C(0x0)
+ /* Module is rejected and transmit side Laser is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
UINT32_C(0x1)
- /*
- * When this bit is set to '1', the device supports one-step
- * Tx timestamping.
- */
- #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ /* Module mismatch warning. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
+ UINT32_C(0x2)
+ /* Module is rejected and powered down. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
+ UINT32_C(0x3)
+ /* Module is not inserted. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
UINT32_C(0x4)
- /*
- * When this bit is set to '1', the PTP information is accessible
- * via HWRM commands.
- */
- #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
+ /* Module is powered down because of over current fault. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
+ UINT32_C(0x5)
+ /* Module status is not applicable. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
+ UINT32_C(0xff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
+ /* Current setting for preemphasis. */
+ uint32_t preemphasis;
+ /* This field represents the major version of the PHY. */
+ uint8_t phy_maj;
+ /* This field represents the minor version of the PHY. */
+ uint8_t phy_min;
+ /* This field represents the build version of the PHY. */
+ uint8_t phy_bld;
+ /* This value represents a PHY type. */
+ uint8_t phy_type;
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* BASE-CR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
+ UINT32_C(0x1)
+ /* BASE-KR4 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
+ UINT32_C(0x2)
+ /* BASE-LR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
+ UINT32_C(0x3)
+ /* BASE-SR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
+ UINT32_C(0x4)
+ /* BASE-KR2 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
+ UINT32_C(0x5)
+ /* BASE-KX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
+ UINT32_C(0x6)
+ /* BASE-KR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
+ UINT32_C(0x7)
+ /* BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
UINT32_C(0x8)
- uint8_t unused_0[3];
- /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
- uint32_t rx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
- uint32_t rx_ts_reg_off_upper;
- /* Offset of the PTP register for the sequence ID for RX. */
- uint32_t rx_ts_reg_off_seq_id;
- /* Offset of the first PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_0;
- /* Offset of the second PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_1;
- /* Offset of the third PTP source ID for RX. */
- uint32_t rx_ts_reg_off_src_id_2;
- /* Offset of the domain ID for RX. */
- uint32_t rx_ts_reg_off_domain_id;
- /* Offset of the PTP FIFO register for RX. */
- uint32_t rx_ts_reg_off_fifo;
- /* Offset of the PTP advance FIFO register for RX. */
- uint32_t rx_ts_reg_off_fifo_adv;
- /* PTP timestamp granularity for RX. */
- uint32_t rx_ts_reg_off_granularity;
- /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
- uint32_t tx_ts_reg_off_lower;
- /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
- uint32_t tx_ts_reg_off_upper;
- /* Offset of the PTP register for the sequence ID for TX. */
- uint32_t tx_ts_reg_off_seq_id;
- /* Offset of the PTP FIFO register for TX. */
- uint32_t tx_ts_reg_off_fifo;
- /* PTP timestamp granularity for TX. */
- uint32_t tx_ts_reg_off_granularity;
- uint8_t unused_1[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/* Port Tx Statistics Format */
-/* tx_port_stats (size:3264b/408B) */
-struct tx_port_stats {
- /* Total Number of 64 Bytes frames transmitted */
- uint64_t tx_64b_frames;
- /* Total Number of 65-127 Bytes frames transmitted */
- uint64_t tx_65b_127b_frames;
- /* Total Number of 128-255 Bytes frames transmitted */
- uint64_t tx_128b_255b_frames;
- /* Total Number of 256-511 Bytes frames transmitted */
- uint64_t tx_256b_511b_frames;
- /* Total Number of 512-1023 Bytes frames transmitted */
- uint64_t tx_512b_1023b_frames;
- /* Total Number of 1024-1518 Bytes frames transmitted */
- uint64_t tx_1024b_1518b_frames;
- /*
- * Total Number of each good VLAN (exludes FCS errors)
- * frame transmitted which is 1519 to 1522 bytes in length
- * inclusive (excluding framing bits but including FCS bytes).
- */
- uint64_t tx_good_vlan_frames;
- /* Total Number of 1519-2047 Bytes frames transmitted */
- uint64_t tx_1519b_2047b_frames;
- /* Total Number of 2048-4095 Bytes frames transmitted */
- uint64_t tx_2048b_4095b_frames;
- /* Total Number of 4096-9216 Bytes frames transmitted */
- uint64_t tx_4096b_9216b_frames;
- /* Total Number of 9217-16383 Bytes frames transmitted */
- uint64_t tx_9217b_16383b_frames;
- /* Total Number of good frames transmitted */
- uint64_t tx_good_frames;
- /* Total Number of frames transmitted */
- uint64_t tx_total_frames;
- /* Total number of unicast frames transmitted */
- uint64_t tx_ucast_frames;
- /* Total number of multicast frames transmitted */
- uint64_t tx_mcast_frames;
- /* Total number of broadcast frames transmitted */
- uint64_t tx_bcast_frames;
- /* Total number of PAUSE control frames transmitted */
- uint64_t tx_pause_frames;
+ /* EEE capable BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
+ UINT32_C(0x9)
+ /* SGMII connected external PHY */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
+ UINT32_C(0xa)
+ /* 25G_BASECR_CA_L */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
+ UINT32_C(0xb)
+ /* 25G_BASECR_CA_S */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
+ UINT32_C(0xc)
+ /* 25G_BASECR_CA_N */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
+ UINT32_C(0xd)
+ /* 25G_BASESR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
+ UINT32_C(0xe)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
+ UINT32_C(0xf)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
+ UINT32_C(0x10)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
+ UINT32_C(0x11)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
+ UINT32_C(0x12)
+ /* 100G_BASESR10 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
+ UINT32_C(0x13)
+ /* 40G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
+ UINT32_C(0x14)
+ /* 40G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
+ UINT32_C(0x15)
+ /* 40G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
+ UINT32_C(0x16)
+ /* 40G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
+ UINT32_C(0x17)
+ /* 40G_ACTIVE_CABLE */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
+ UINT32_C(0x18)
+ /* 1G_baseT */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
+ UINT32_C(0x19)
+ /* 1G_baseSX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
+ UINT32_C(0x1a)
+ /* 1G_baseCX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
+ UINT32_C(0x1b)
+ /* 200G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 200G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 200G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 200G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
+ /* 50G_BASECR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \
+ UINT32_C(0x20)
+ /* 50G_BASESR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \
+ UINT32_C(0x21)
+ /* 50G_BASELR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \
+ UINT32_C(0x22)
+ /* 50G_BASEER */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \
+ UINT32_C(0x23)
+ /* 100G_BASECR2 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \
+ UINT32_C(0x24)
+ /* 100G_BASESR2 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \
+ UINT32_C(0x25)
+ /* 100G_BASELR2 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \
+ UINT32_C(0x26)
+ /* 100G_BASEER2 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \
+ UINT32_C(0x27)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2
+ /* This value represents a media type. */
+ uint8_t media_type;
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
+ /* Twisted Pair */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
+ /* Direct Attached Copper */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
+ /* Fiber */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
+ /* This value represents a transceiver type. */
+ uint8_t xcvr_pkg_type;
+ /* PHY and MAC are in the same package */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
+ UINT32_C(0x1)
+ /* PHY and MAC are in different packages */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
+ uint8_t eee_config_phy_addr;
+ /* This field represents PHY address. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
+ UINT32_C(0x1f)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
/*
- * Total number of PFC/per-priority PAUSE
- * control frames transmitted
+ * This field represents flags related to EEE configuration.
+ * These EEE configuration flags are valid only when the
+ * auto_mode is not set to none (in other words autonegotiation
+ * is enabled).
*/
- uint64_t tx_pfc_frames;
- /* Total number of jabber frames transmitted */
- uint64_t tx_jabber_frames;
- /* Total number of frames transmitted with FCS error */
- uint64_t tx_fcs_err_frames;
- /* Total number of control frames transmitted */
- uint64_t tx_control_frames;
- /* Total number of over-sized frames transmitted */
- uint64_t tx_oversz_frames;
- /* Total number of frames with single deferral */
- uint64_t tx_single_dfrl_frames;
- /* Total number of frames with multiple deferrals */
- uint64_t tx_multi_dfrl_frames;
- /* Total number of frames with single collision */
- uint64_t tx_single_coll_frames;
- /* Total number of frames with multiple collisions */
- uint64_t tx_multi_coll_frames;
- /* Total number of frames with late collisions */
- uint64_t tx_late_coll_frames;
- /* Total number of frames with excessive collisions */
- uint64_t tx_excessive_coll_frames;
- /* Total number of fragmented frames transmitted */
- uint64_t tx_frag_frames;
- /* Total number of transmit errors */
- uint64_t tx_err;
- /* Total number of single VLAN tagged frames transmitted */
- uint64_t tx_tagged_frames;
- /* Total number of double VLAN tagged frames transmitted */
- uint64_t tx_dbl_tagged_frames;
- /* Total number of runt frames transmitted */
- uint64_t tx_runt_frames;
- /* Total number of TX FIFO under runs */
- uint64_t tx_fifo_underruns;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 0 transmitted
+ * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
+ * Speeds for autoneg with EEE mode enabled
+ * are based on eee_link_speed_mask.
*/
- uint64_t tx_pfc_ena_frames_pri0;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
+ UINT32_C(0x20)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 1 transmitted
+ * This flag is valid only when eee_enabled is set to 1.
+ *
+ * # If eee_enabled is set to 0, then EEE mode is disabled
+ * and this flag shall be ignored.
+ * # If eee_enabled is set to 1 and this flag is set to 1,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * and in use.
+ * # If eee_enabled is set to 1 and this flag is set to 0,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * but is currently not in use.
*/
- uint64_t tx_pfc_ena_frames_pri1;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
+ UINT32_C(0x40)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 2 transmitted
+ * This flag is valid only when eee_enabled is set to 1.
+ *
+ * # If eee_enabled is set to 0, then EEE mode is disabled
+ * and this flag shall be ignored.
+ * # If eee_enabled is set to 1 and this flag is set to 1,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * and TX LPI is enabled.
+ * # If eee_enabled is set to 1 and this flag is set to 0,
+ * then Energy Efficient Ethernet (EEE) mode is enabled
+ * but TX LPI is disabled.
*/
- uint64_t tx_pfc_ena_frames_pri2;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
+ UINT32_C(0x80)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 3 transmitted
+ * When set to 1, the parallel detection is used to determine
+ * the speed of the link partner.
+ *
+ * Parallel detection is used when a autonegotiation capable
+ * device is connected to a link partner that is not capable
+ * of autonegotiation.
*/
- uint64_t tx_pfc_ena_frames_pri3;
+ uint8_t parallel_detect;
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 4 transmitted
+ * When set to 1, the parallel detection is used to determine
+ * the speed of the link partner.
+ *
+ * Parallel detection is used when a autonegotiation capable
+ * device is connected to a link partner that is not capable
+ * of autonegotiation.
*/
- uint64_t tx_pfc_ena_frames_pri4;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 5 transmitted
+ * The advertised speeds for the port by the link partner.
+ * Each advertised speed will be set to '1'.
*/
- uint64_t tx_pfc_ena_frames_pri5;
+ uint16_t link_partner_adv_speeds;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
+ UINT32_C(0x10)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
+ UINT32_C(0x2000)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 6 transmitted
+ * The advertised autoneg for the port by the link partner.
+ * This field is deprecated and should be set to 0.
*/
- uint64_t tx_pfc_ena_frames_pri6;
+ uint8_t link_partner_adv_auto_mode;
+ /* Disable autoneg or autoneg disabled. No speeds are selected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
+ UINT32_C(0x0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
+ UINT32_C(0x1)
/*
- * Total number of PFC frames with PFC enabled bit for
- * Pri 7 transmitted
+ * Select only the auto_link_speed speed for autoneg mode. This mode has
+ * been DEPRECATED. An HWRM client should not use this mode.
*/
- uint64_t tx_pfc_ena_frames_pri7;
- /* Total number of EEE LPI Events on TX */
- uint64_t tx_eee_lpi_events;
- /* EEE LPI Duration Counter on TX */
- uint64_t tx_eee_lpi_duration;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
+ UINT32_C(0x2)
/*
- * Total number of Link Level Flow Control (LLFC) messages
- * transmitted
+ * Select the auto_link_speed or any speed below that speed for autoneg.
+ * This mode has been DEPRECATED. An HWRM client should not use this mode.
*/
- uint64_t tx_llfc_logical_msgs;
- /* Total number of HCFC messages transmitted */
- uint64_t tx_hcfc_msgs;
- /* Total number of TX collisions */
- uint64_t tx_total_collisions;
- /* Total number of transmitted bytes */
- uint64_t tx_bytes;
- /* Total number of end-to-end HOL frames */
- uint64_t tx_xthol_frames;
- /* Total Tx Drops per Port reported by STATS block */
- uint64_t tx_stat_discard;
- /* Total Tx Error Drops per Port reported by STATS block */
- uint64_t tx_stat_error;
-} __rte_packed;
-
-/* Port Rx Statistics Format */
-/* rx_port_stats (size:4224b/528B) */
-struct rx_port_stats {
- /* Total Number of 64 Bytes frames received */
- uint64_t rx_64b_frames;
- /* Total Number of 65-127 Bytes frames received */
- uint64_t rx_65b_127b_frames;
- /* Total Number of 128-255 Bytes frames received */
- uint64_t rx_128b_255b_frames;
- /* Total Number of 256-511 Bytes frames received */
- uint64_t rx_256b_511b_frames;
- /* Total Number of 512-1023 Bytes frames received */
- uint64_t rx_512b_1023b_frames;
- /* Total Number of 1024-1518 Bytes frames received */
- uint64_t rx_1024b_1518b_frames;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
+ UINT32_C(0x3)
/*
- * Total Number of each good VLAN (exludes FCS errors)
- * frame received which is 1519 to 1522 bytes in length
- * inclusive (excluding framing bits but including FCS bytes).
+ * Select the speeds based on the corresponding link speed mask value
+ * that is provided.
*/
- uint64_t rx_good_vlan_frames;
- /* Total Number of 1519-2047 Bytes frames received */
- uint64_t rx_1519b_2047b_frames;
- /* Total Number of 2048-4095 Bytes frames received */
- uint64_t rx_2048b_4095b_frames;
- /* Total Number of 4096-9216 Bytes frames received */
- uint64_t rx_4096b_9216b_frames;
- /* Total Number of 9217-16383 Bytes frames received */
- uint64_t rx_9217b_16383b_frames;
- /* Total number of frames received */
- uint64_t rx_total_frames;
- /* Total number of unicast frames received */
- uint64_t rx_ucast_frames;
- /* Total number of multicast frames received */
- uint64_t rx_mcast_frames;
- /* Total number of broadcast frames received */
- uint64_t rx_bcast_frames;
- /* Total number of received frames with FCS error */
- uint64_t rx_fcs_err_frames;
- /* Total number of control frames received */
- uint64_t rx_ctrl_frames;
- /* Total number of PAUSE frames received */
- uint64_t rx_pause_frames;
- /* Total number of PFC frames received */
- uint64_t rx_pfc_frames;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
+ UINT32_C(0x4)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
+ /* The advertised pause settings on the port by the link partner. */
+ uint8_t link_partner_adv_pause;
/*
- * Total number of frames received with an unsupported
- * opcode
+ * When this bit is '1', Generation of tx pause messages
+ * is supported. Disabled otherwise.
*/
- uint64_t rx_unsupported_opcode_frames;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
+ UINT32_C(0x1)
/*
- * Total number of frames received with an unsupported
- * DA for pause and PFC
+ * When this bit is '1', Reception of rx pause messages
+ * is supported. Disabled otherwise.
*/
- uint64_t rx_unsupported_da_pausepfc_frames;
- /* Total number of frames received with an unsupported SA */
- uint64_t rx_wrong_sa_frames;
- /* Total number of received packets with alignment error */
- uint64_t rx_align_err_frames;
- /* Total number of received frames with out-of-range length */
- uint64_t rx_oor_len_frames;
- /* Total number of received frames with error termination */
- uint64_t rx_code_err_frames;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
+ UINT32_C(0x2)
/*
- * Total number of received frames with a false carrier is
- * detected during idle, as defined by RX_ER samples active
- * and RXD is 0xE. The event is reported along with the
- * statistics generated on the next received frame. Only
- * one false carrier condition can be detected and logged
- * between frames.
- *
- * Carrier event, valid for 10M/100M speed modes only.
+ * Current setting for link speed mask that is used to
+ * advertise speeds during autonegotiation when EEE is enabled.
+ * This field is valid only when eee_enabled flags is set to 1.
+ * The speeds specified in this field shall be a subset of
+ * speeds specified in auto_link_speed_mask.
*/
- uint64_t rx_false_carrier_frames;
- /* Total number of over-sized frames received */
- uint64_t rx_ovrsz_frames;
- /* Total number of jabber packets received */
- uint64_t rx_jbr_frames;
- /* Total number of received frames with MTU error */
- uint64_t rx_mtu_err_frames;
- /* Total number of received frames with CRC match */
- uint64_t rx_match_crc_frames;
- /* Total number of frames received promiscuously */
- uint64_t rx_promiscuous_frames;
+ uint16_t adv_eee_link_speed_mask;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
/*
- * Total number of received frames with one or two VLAN
- * tags
+ * Current setting for link speed mask that is advertised by
+ * the link partner when EEE is enabled.
+ * This field is valid only when eee_enabled flags is set to 1.
*/
- uint64_t rx_tagged_frames;
- /* Total number of received frames with two VLAN tags */
- uint64_t rx_double_tagged_frames;
- /* Total number of truncated frames received */
- uint64_t rx_trunc_frames;
- /* Total number of good frames (without errors) received */
- uint64_t rx_good_frames;
+ uint16_t link_partner_adv_eee_link_speed_mask;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ uint32_t xcvr_identifier_type_tx_lpi_timer;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 0
+ * Current setting of TX LPI timer in microseconds.
+ * This field is valid only when_eee_enabled flag is set to 1
+ * and tx_lpi_enabled is set to 1.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri0;
- /*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 1
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
+ /* This value represents transceiver identifier type. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
+ (UINT32_C(0x0) << 24)
+ /* SFP/SFP+/SFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
+ (UINT32_C(0x3) << 24)
+ /* QSFP+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
+ (UINT32_C(0xc) << 24)
+ /* QSFP+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
+ (UINT32_C(0xd) << 24)
+ /* QSFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
+ (UINT32_C(0x11) << 24)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
+ /*
+ * This value represents the current configuration of
+ * Forward Error Correction (FEC) on the port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri1;
+ uint16_t fec_cfg;
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 2
+ * When set to 1, then FEC is not supported on this port. If this flag
+ * is set to 1, then all other FEC configuration flags shall be ignored.
+ * When set to 0, then FEC is supported as indicated by other
+ * configuration flags.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri2;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
+ UINT32_C(0x1)
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 3
+ * When set to 1, then FEC autonegotiation is supported on this port.
+ * When set to 0, then FEC autonegotiation is not supported on this port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri3;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
+ UINT32_C(0x2)
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 4
+ * When set to 1, then FEC autonegotiation is enabled on this port.
+ * When set to 0, then FEC autonegotiation is disabled if supported.
+ * This flag should be ignored if FEC autonegotiation is not supported on this port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri4;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
+ UINT32_C(0x4)
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 5
+ * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
+ * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri5;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
+ UINT32_C(0x8)
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 6
+ * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
+ * port. This means that FEC CLAUSE 74 is either advertised if
+ * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
+ * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
+ * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri6;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
+ UINT32_C(0x10)
/*
- * Total number of received PFC frames with transition from
- * XON to XOFF on Pri 7
+ * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
+ * NRZ) is supported on this port.
+ * When set to 0, then FEC RS(528,418) is not supported on this port.
*/
- uint64_t rx_pfc_xon2xoff_frames_pri7;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
+ UINT32_C(0x20)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 0
+ * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
+ * NRZ) is enabled on this port. This means that FEC RS(528,514) is
+ * either advertised if FEC autonegotiation is enabled or FEC
+ * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
+ * is disabled if supported.
+ * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri0;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
+ UINT32_C(0x40)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 1
+ * When set to 1, then FEC RS544_1XN is supported on this port.
+ * When set to 0, then FEC RS544_1XN is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri1;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
+ UINT32_C(0x80)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 2
+ * When set to 1, then RS544_1XN is enabled on this
+ * port. This means that FEC RS544_1XN is either advertised if
+ * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
+ * When set to 0, then FEC RS544_1XN is disabled if supported.
+ * This flag should be ignored if FEC RS544_1XN is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri2;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
+ UINT32_C(0x100)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 3
+ * When set to 1, then FEC RS(544,514) is supported on this port.
+ * When set to 0, then FEC RS(544,514) is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri3;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
+ UINT32_C(0x200)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 4
+ * When set to 1, then RS(544,514) is enabled on this
+ * port. This means that FEC RS(544,514) is either advertised if
+ * FEC autonegotiation is enabled or FEC RS(544,514) is force
+ * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
+ * This flag should be ignored if FEC RS(544,514) is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri4;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
+ UINT32_C(0x400)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 5
+ * When set to 1, then FEC RS272_1XN is supported on this port.
+ * When set to 0, then FEC RS272_1XN is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri5;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
+ UINT32_C(0x800)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 6
+ * When set to 1, then RS272_1XN is enabled on this
+ * port. This means that FEC RS272_1XN is either advertised if
+ * FEC autonegotiation is enabled or FEC RS272_1XN is force
+ * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
+ * This flag should be ignored if FEC RS272_1XN is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri6;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
+ UINT32_C(0x1000)
/*
- * Total number of received PFC frames with PFC enabled
- * bit for Pri 7
+ * When set to 1, then FEC RS(272,514) is supported on this port.
+ * When set to 0, then FEC RS(272,514) is not supported on this port.
*/
- uint64_t rx_pfc_ena_frames_pri7;
- /* Total Number of frames received with SCH CRC error */
- uint64_t rx_sch_crc_err_frames;
- /* Total Number of under-sized frames received */
- uint64_t rx_undrsz_frames;
- /* Total Number of fragmented frames received */
- uint64_t rx_frag_frames;
- /* Total number of RX EEE LPI Events */
- uint64_t rx_eee_lpi_events;
- /* EEE LPI Duration Counter on RX */
- uint64_t rx_eee_lpi_duration;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
+ UINT32_C(0x2000)
/*
- * Total number of physical type Link Level Flow Control
- * (LLFC) messages received
+ * When set to 1, then RS(272,257) is enabled on this
+ * port. This means that FEC RS(272,257) is either advertised if
+ * FEC autonegotiation is enabled or FEC RS(272,257) is force
+ * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
+ * This flag should be ignored if FEC RS(272,257) is not supported on this port.
*/
- uint64_t rx_llfc_physical_msgs;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
+ UINT32_C(0x4000)
/*
- * Total number of logical type Link Level Flow Control
- * (LLFC) messages received
+ * This value is indicates the duplex of the current
+ * connection state.
*/
- uint64_t rx_llfc_logical_msgs;
+ uint8_t duplex_state;
+ /* Half Duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
+ /* Full duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
+ /* Option flags fields. */
+ uint8_t option_flags;
+ /* When this bit is '1', Media auto detect is enabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
+ UINT32_C(0x1)
/*
- * Total number of logical type Link Level Flow Control
- * (LLFC) messages received with CRC error
+ * When this bit is '1', active_fec_signal_mode can be
+ * trusted.
*/
- uint64_t rx_llfc_msgs_with_crc_err;
- /* Total number of HCFC messages received */
- uint64_t rx_hcfc_msgs;
- /* Total number of HCFC messages received with CRC error */
- uint64_t rx_hcfc_msgs_with_crc_err;
- /* Total number of received bytes */
- uint64_t rx_bytes;
- /* Total number of bytes received in runt frames */
- uint64_t rx_runt_bytes;
- /* Total number of runt frames received */
- uint64_t rx_runt_frames;
- /* Total Rx Discards per Port reported by STATS block */
- uint64_t rx_stat_discard;
- uint64_t rx_stat_err;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
+ UINT32_C(0x2)
+ /*
+ * Up to 16 bytes of null padded ASCII string representing
+ * PHY vendor.
+ * If the string is set to null, then the vendor name is not
+ * available.
+ */
+ char phy_vendor_name[16];
+ /*
+ * Up to 16 bytes of null padded ASCII string that
+ * identifies vendor specific part number of the PHY.
+ * If the string is set to null, then the vendor specific
+ * part number is not available.
+ */
+ char phy_vendor_partnumber[16];
+ /*
+ * The supported PAM4 speeds for the port. This is a bit mask.
+ * For each speed that is supported, the corresponding
+ * bit will be set to '1'.
+ */
+ uint16_t support_pam4_speeds;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
+ UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
+ UINT32_C(0x4)
+ /*
+ * Current setting of forced PAM4 link speed.
+ * When the link speed is not being forced, this
+ * value shall be set to 0.
+ */
+ uint16_t force_pam4_link_speed;
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
+ UINT32_C(0x1f4)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
+ UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
+ HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
+ /*
+ * Current setting for auto_pam4_link_speed_mask that is used to
+ * advertise speeds during autonegotiation.
+ * This field is only valid when auto_mode is set to "mask".
+ * The speeds specified in this field shall be a subset of
+ * supported speeds on this port.
+ */
+ uint16_t auto_pam4_link_speed_mask;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
+ UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
+ UINT32_C(0x4)
+ /*
+ * The advertised PAM4 speeds for the port by the link partner.
+ * Each advertised speed will be set to '1'.
+ */
+ uint8_t link_partner_pam4_adv_speeds;
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
+ UINT32_C(0x1)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
+ UINT32_C(0x2)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
+ UINT32_C(0x4)
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __rte_packed;
-/********************
- * hwrm_port_qstats *
- ********************/
+/*********************
+ * hwrm_port_mac_cfg *
+ *********************/
-/* hwrm_port_qstats_input (size:320b/40B) */
-struct hwrm_port_qstats_input {
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
+struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * This bit is set to 1 when request is for a counter mask,
- * representing the width of each of the stats counters, rather
- * than counters themselves.
+ * In this field, there are a number of CoS mappings related flags
+ * that are used to configure CoS mappings and their corresponding
+ * priorities in the hardware.
+ * For the priorities of CoS mappings, the HWRM uses the following
+ * priority order (high to low) by default:
+ * # vlan pri
+ * # ip_dscp
+ * # tunnel_vlan_pri
+ * # default cos
+ *
+ * A subset of CoS mappings can be enabled.
+ * If a priority is not specified for an enabled CoS mapping, the
+ * priority will be assigned in the above order for the enabled CoS
+ * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
+ * enabled and their priorities are not specified, the following
+ * priority order (high to low) will be used by the HWRM:
+ * # vlan_pri
+ * # ip_dscp
+ * # default cos
+ *
+ * vlan_pri CoS mapping together with default CoS with lower priority
+ * are enabled by default by the HWRM.
*/
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
- uint8_t unused_0[5];
+ uint32_t flags;
/*
- * This is the host address where
- * Tx port statistics will be stored
+ * When this bit is '1', this command will configure
+ * the MAC to match the current link state of the PHY.
+ * If the link is not established on the PHY, then this
+ * bit has no effect.
*/
- uint64_t tx_stat_host_addr;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
+ UINT32_C(0x1)
/*
- * This is the host address where
- * Rx port statistics will be stored
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is requested to be enabled.
*/
- uint64_t rx_stat_host_addr;
-} __rte_packed;
-
-/* hwrm_port_qstats_output (size:128b/16B) */
-struct hwrm_port_qstats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* The size of TX port statistics block in bytes. */
- uint16_t tx_stat_size;
- /* The size of RX port statistics block in bytes. */
- uint16_t rx_stat_size;
- uint8_t unused_0[3];
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ UINT32_C(0x2)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is requested to be enabled.
*/
- uint8_t valid;
-} __rte_packed;
-
-/* Port Tx Statistics extended Format */
-/* tx_port_stats_ext (size:2048b/256B) */
-struct tx_port_stats_ext {
- /* Total number of tx bytes count on cos queue 0 */
- uint64_t tx_bytes_cos0;
- /* Total number of tx bytes count on cos queue 1 */
- uint64_t tx_bytes_cos1;
- /* Total number of tx bytes count on cos queue 2 */
- uint64_t tx_bytes_cos2;
- /* Total number of tx bytes count on cos queue 3 */
- uint64_t tx_bytes_cos3;
- /* Total number of tx bytes count on cos queue 4 */
- uint64_t tx_bytes_cos4;
- /* Total number of tx bytes count on cos queue 5 */
- uint64_t tx_bytes_cos5;
- /* Total number of tx bytes count on cos queue 6 */
- uint64_t tx_bytes_cos6;
- /* Total number of tx bytes count on cos queue 7 */
- uint64_t tx_bytes_cos7;
- /* Total number of tx packets count on cos queue 0 */
- uint64_t tx_packets_cos0;
- /* Total number of tx packets count on cos queue 1 */
- uint64_t tx_packets_cos1;
- /* Total number of tx packets count on cos queue 2 */
- uint64_t tx_packets_cos2;
- /* Total number of tx packets count on cos queue 3 */
- uint64_t tx_packets_cos3;
- /* Total number of tx packets count on cos queue 4 */
- uint64_t tx_packets_cos4;
- /* Total number of tx packets count on cos queue 5 */
- uint64_t tx_packets_cos5;
- /* Total number of tx packets count on cos queue 6 */
- uint64_t tx_packets_cos6;
- /* Total number of tx packets count on cos queue 7 */
- uint64_t tx_packets_cos7;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
- uint64_t pfc_pri0_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
- uint64_t pfc_pri0_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
- uint64_t pfc_pri1_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
- uint64_t pfc_pri1_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
- uint64_t pfc_pri2_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
- uint64_t pfc_pri2_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
- uint64_t pfc_pri3_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
- uint64_t pfc_pri3_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
- uint64_t pfc_pri4_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
- uint64_t pfc_pri4_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
- uint64_t pfc_pri5_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
- uint64_t pfc_pri5_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
- uint64_t pfc_pri6_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
- uint64_t pfc_pri6_tx_transitions;
- /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
- uint64_t pfc_pri7_tx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
- uint64_t pfc_pri7_tx_transitions;
-} __rte_packed;
-
-/* Port Rx Statistics extended Format */
-/* rx_port_stats_ext (size:3648b/456B) */
-struct rx_port_stats_ext {
- /* Number of times link state changed to down */
- uint64_t link_down_events;
- /* Number of times the idle rings with pause bit are found */
- uint64_t continuous_pause_events;
- /* Number of times the active rings pause bit resumed back */
- uint64_t resume_pause_events;
- /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
- uint64_t continuous_roce_pause_events;
- /* Number of times, the ROCE cos queue PFC is enabled back */
- uint64_t resume_roce_pause_events;
- /* Total number of rx bytes count on cos queue 0 */
- uint64_t rx_bytes_cos0;
- /* Total number of rx bytes count on cos queue 1 */
- uint64_t rx_bytes_cos1;
- /* Total number of rx bytes count on cos queue 2 */
- uint64_t rx_bytes_cos2;
- /* Total number of rx bytes count on cos queue 3 */
- uint64_t rx_bytes_cos3;
- /* Total number of rx bytes count on cos queue 4 */
- uint64_t rx_bytes_cos4;
- /* Total number of rx bytes count on cos queue 5 */
- uint64_t rx_bytes_cos5;
- /* Total number of rx bytes count on cos queue 6 */
- uint64_t rx_bytes_cos6;
- /* Total number of rx bytes count on cos queue 7 */
- uint64_t rx_bytes_cos7;
- /* Total number of rx packets count on cos queue 0 */
- uint64_t rx_packets_cos0;
- /* Total number of rx packets count on cos queue 1 */
- uint64_t rx_packets_cos1;
- /* Total number of rx packets count on cos queue 2 */
- uint64_t rx_packets_cos2;
- /* Total number of rx packets count on cos queue 3 */
- uint64_t rx_packets_cos3;
- /* Total number of rx packets count on cos queue 4 */
- uint64_t rx_packets_cos4;
- /* Total number of rx packets count on cos queue 5 */
- uint64_t rx_packets_cos5;
- /* Total number of rx packets count on cos queue 6 */
- uint64_t rx_packets_cos6;
- /* Total number of rx packets count on cos queue 7 */
- uint64_t rx_packets_cos7;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
- uint64_t pfc_pri0_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
- uint64_t pfc_pri0_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
- uint64_t pfc_pri1_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
- uint64_t pfc_pri1_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
- uint64_t pfc_pri2_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
- uint64_t pfc_pri2_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
- uint64_t pfc_pri3_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
- uint64_t pfc_pri3_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
- uint64_t pfc_pri4_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
- uint64_t pfc_pri4_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
- uint64_t pfc_pri5_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
- uint64_t pfc_pri5_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
- uint64_t pfc_pri6_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
- uint64_t pfc_pri6_rx_transitions;
- /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
- uint64_t pfc_pri7_rx_duration_us;
- /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
- uint64_t pfc_pri7_rx_transitions;
- /* Total number of received bits */
- uint64_t rx_bits;
- /* The number of events where the port receive buffer was over 85% full */
- uint64_t rx_buffer_passed_threshold;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ UINT32_C(0x4)
/*
- * The number of symbol errors that wasn't corrected by FEC correction
- * alogirithm
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * requested to be enabled.
*/
- uint64_t rx_pcs_symbol_err;
- /* The number of corrected bits on the port according to active FEC */
- uint64_t rx_corrected_bits;
- /* Total number of rx discard bytes count on cos queue 0 */
- uint64_t rx_discard_bytes_cos0;
- /* Total number of rx discard bytes count on cos queue 1 */
- uint64_t rx_discard_bytes_cos1;
- /* Total number of rx discard bytes count on cos queue 2 */
- uint64_t rx_discard_bytes_cos2;
- /* Total number of rx discard bytes count on cos queue 3 */
- uint64_t rx_discard_bytes_cos3;
- /* Total number of rx discard bytes count on cos queue 4 */
- uint64_t rx_discard_bytes_cos4;
- /* Total number of rx discard bytes count on cos queue 5 */
- uint64_t rx_discard_bytes_cos5;
- /* Total number of rx discard bytes count on cos queue 6 */
- uint64_t rx_discard_bytes_cos6;
- /* Total number of rx discard bytes count on cos queue 7 */
- uint64_t rx_discard_bytes_cos7;
- /* Total number of rx discard packets count on cos queue 0 */
- uint64_t rx_discard_packets_cos0;
- /* Total number of rx discard packets count on cos queue 1 */
- uint64_t rx_discard_packets_cos1;
- /* Total number of rx discard packets count on cos queue 2 */
- uint64_t rx_discard_packets_cos2;
- /* Total number of rx discard packets count on cos queue 3 */
- uint64_t rx_discard_packets_cos3;
- /* Total number of rx discard packets count on cos queue 4 */
- uint64_t rx_discard_packets_cos4;
- /* Total number of rx discard packets count on cos queue 5 */
- uint64_t rx_discard_packets_cos5;
- /* Total number of rx discard packets count on cos queue 6 */
- uint64_t rx_discard_packets_cos6;
- /* Total number of rx discard packets count on cos queue 7 */
- uint64_t rx_discard_packets_cos7;
-} __rte_packed;
-
-/*
- * Port Rx Statistics extended PFC WatchDog Format.
- * StormDetect and StormRevert event determination is based
- * on an integration period and a percentage threshold.
- * StormDetect event - when percentage of XOFF frames received
- * within an integration period exceeds the configured threshold.
- * StormRevert event - when percentage of XON frames received
- * within an integration period exceeds the configured threshold.
- * Actual number of XOFF/XON frames for the events to be triggered
- * depends on both configured integration period and sampling rate.
- * The statistics in this structure represent counts of specified
- * events from the moment the feature (PFC WatchDog) is enabled via
- * hwrm_queue_pfc_enable_cfg call.
- */
-/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
-struct rx_port_stats_ext_pfc_wd {
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ UINT32_C(0x8)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 0
- */
- uint64_t rx_pfc_watchdog_storms_detected_pri0;
- /*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 1
+ * When this bit is '1', the HWRM is requested to
+ * enable timestamp capture capability on the receive side
+ * of this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri1;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x10)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 2
+ * When this bit is '1', the HWRM is requested to
+ * disable timestamp capture capability on the receive side
+ * of this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri2;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
+ UINT32_C(0x20)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 3
+ * When this bit is '1', the HWRM is requested to
+ * enable timestamp capture capability on the transmit side
+ * of this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri3;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x40)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 4
+ * When this bit is '1', the HWRM is requested to
+ * disable timestamp capture capability on the transmit side
+ * of this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri4;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
+ UINT32_C(0x80)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 5
+ * When this bit is '1', the Out-Of-Box WoL is requested to
+ * be enabled on this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri5;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
+ UINT32_C(0x100)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 6
+ * When this bit is '1', the Out-Of-Box WoL is requested to
+ * be disabled on this port.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri6;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
+ UINT32_C(0x200)
/*
- * Total number of PFC WatchDog StormDetect events detected
- * for Pri 7
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is requested to be disabled.
*/
- uint64_t rx_pfc_watchdog_storms_detected_pri7;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
+ UINT32_C(0x400)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 0
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is requested to be disabled.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri0;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
+ UINT32_C(0x800)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 1
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * requested to be disabled.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri1;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
+ UINT32_C(0x1000)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 2
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri2;
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
+ uint32_t enables;
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 3
+ * This bit must be '1' for the ipg field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri3;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
+ UINT32_C(0x1)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 4
+ * This bit must be '1' for the lpbk field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri4;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
+ UINT32_C(0x2)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 5
+ * This bit must be '1' for the vlan_pri2cos_map_pri field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri5;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
+ UINT32_C(0x4)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 6
+ * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri6;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
+ UINT32_C(0x10)
/*
- * Total number of PFC WatchDog StormRevert events detected
- * for Pri 7
+ * This bit must be '1' for the dscp2cos_map_pri field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_reverted_pri7;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
+ UINT32_C(0x20)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 0
+ * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
+ UINT32_C(0x40)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 1
+ * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
+ UINT32_C(0x80)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 2
+ * This bit must be '1' for the cos_field_cfg field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
+ UINT32_C(0x100)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 3
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 4
+ * This bit must be '1' for the ptp_adj_phase field to be
+ * configured.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \
+ UINT32_C(0x400)
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 5
+ * This value is used to configure the minimum IPG that will
+ * be sent between packets by this port.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
+ uint8_t ipg;
+ /* This value controls the loopback setting for the MAC. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 6
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * Total number of packets received during PFC watchdog storm
- * for pri 7
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 0
+ * This value controls the priority setting of VLAN PRI to CoS
+ * mapping based on VLAN Tags of inner packet headers of
+ * tunneled packets or packet headers of non-tunneled packets.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
+ uint8_t vlan_pri2cos_map_pri;
+ /* Reserved field. */
+ uint8_t reserved1;
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 1
+ * This value controls the priority setting of VLAN PRI to CoS
+ * mapping based on VLAN Tags of tunneled header.
+ * This mapping only applies when tunneled headers
+ * are present.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
+ uint8_t tunnel_pri2cos_map_pri;
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 2
+ * This value controls the priority setting of IP DSCP to CoS
+ * mapping based on inner IP header of tunneled packets or
+ * IP header of non-tunneled packets.
+ *
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being specified.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
+ uint8_t dscp2pri_map_pri;
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 3
+ * This is a 16-bit bit mask that is used to request a
+ * specific configuration of time stamp capture of PTP messages
+ * on the receive side of this port.
+ * This field shall be ignored if the ptp_rx_ts_capture_enable
+ * flag is not set in this command.
+ * Otherwise, if bit 'i' is set, then the HWRM is being
+ * requested to configure the receive side of the port to
+ * capture the time stamp of every received PTP message
+ * with messageType field value set to i.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
+ uint16_t rx_ts_capture_ptp_msg_type;
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 4
+ * This is a 16-bit bit mask that is used to request a
+ * specific configuration of time stamp capture of PTP messages
+ * on the transmit side of this port.
+ * This field shall be ignored if the ptp_tx_ts_capture_enable
+ * flag is not set in this command.
+ * Otherwise, if bit 'i' is set, then the HWRM is being
+ * requested to configure the transmit side of the port to
+ * capture the time stamp of every transmitted PTP message
+ * with messageType field value set to i.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
+ uint16_t tx_ts_capture_ptp_msg_type;
+ /* Configuration of CoS fields. */
+ uint8_t cos_field_cfg;
+ /* Reserved */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
+ UINT32_C(0x1)
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 5
+ * This field is used to specify selection of VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the inner packet headers of tunneled packets or
+ * non-tunneled packets.
+ * This field is valid only if inner VLAN PRI to CoS mapping
+ * is enabled.
+ * If VLAN PRI to CoS mapping is not enabled, then this
+ * field shall be ignored.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x6)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
+ 1
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 6
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the inner packet headers
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 1)
/*
- * Total number of bytes received during PFC watchdog storm
- * for pri 7
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the inner packet headers.
+ * No VLAN PRI shall be selected for this configuration
+ * if only one VLAN Tag is present in the inner
+ * packet headers.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 1)
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 0
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the inner packet headers
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 1)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 1)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 1
+ * This field is used to specify selection of tunnel VLAN
+ * PRI value based on whether one or two VLAN Tags are
+ * present in tunnel headers.
+ * This field is valid only if tunnel VLAN PRI to CoS mapping
+ * is enabled.
+ * If tunnel VLAN PRI to CoS mapping is not enabled, then this
+ * field shall be ignored.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x18)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
+ 3
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 2
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the tunnel packet headers
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 3)
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 3
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the tunnel packet headers.
+ * No tunnel VLAN PRI shall be selected for this
+ * configuration if only one VLAN Tag is present in
+ * the tunnel packet headers.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 3)
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 4
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the tunnel packet headers
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 3)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 3)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 5
+ * This field shall be used to provide default CoS value
+ * that has been configured on this port.
+ * This field is valid only if default CoS mapping
+ * is enabled.
+ * If default CoS mapping is not enabled, then this
+ * field shall be ignored.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
+ 5
+ uint8_t unused_0[3];
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 6
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
+ int32_t ptp_freq_adj_ppb;
/*
- * Total number of packets dropped on rx during PFC watchdog storm
- * for pri 7
+ * This unsigned field specifies the phase offset to be applied
+ * to the PHC (PTP Hardware Clock). This field is specified in
+ * nanoseconds.
*/
- uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
+ uint32_t ptp_adj_phase;
+} __rte_packed;
+
+/* hwrm_port_mac_cfg_output (size:128b/16B) */
+struct hwrm_port_mac_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 0
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be received on the port.
+ * This value does not include the number of bytes used by
+ * Ethernet header and trailer (CRC).
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
+ uint16_t mru;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 1
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be transmitted on the port.
+ * This value does not include the number of bytes used by
+ * Ethernet header and trailer (CRC).
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
+ uint16_t mtu;
+ /* Current configuration of the IPG value. */
+ uint8_t ipg;
+ /* Current value of the loopback value. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 2
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 3
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
+ uint8_t unused_0;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 4
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_port_mac_qcfg *
+ **********************/
+
+
+/* hwrm_port_mac_qcfg_input (size:192b/24B) */
+struct hwrm_port_mac_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 5
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
+ uint16_t cmpl_ring;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 6
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
+ uint16_t seq_id;
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 7
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
+ uint16_t target_id;
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 0
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
+ uint64_t resp_addr;
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_port_mac_qcfg_output (size:256b/32B) */
+struct hwrm_port_mac_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 1
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be received on the port.
+ * This value does not include the number of bytes used by the
+ * Ethernet header and trailer (CRC).
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
+ uint16_t mru;
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 2
+ * This is the configured maximum length of Ethernet packet
+ * payload that is allowed to be transmitted on the port.
+ * This value does not include the number of bytes used by the
+ * Ethernet header and trailer (CRC).
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
+ uint16_t mtu;
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 3
+ * The minimum IPG that will
+ * be sent between packets by this port.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
+ uint8_t ipg;
+ /* The loopback setting for the MAC. */
+ uint8_t lpbk;
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 4
+ * The HW will be configured with local loopback such that
+ * host data is sent back to the host without modification.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
/*
- * Number of packets received during last PFC watchdog storm
- * for pri 5
+ * The HW will be configured with remote loopback such that
+ * port logic will send packets back out the transmitter that
+ * are received.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
- /*
- * Number of packets received during last PFC watchdog storm
- * for pri 6
- */
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
- /*
- * Number of packets received during last PFC watchdog storm
- * for pri 7
- */
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
- /*
- * Number of bytes received during last PFC watchdog storm
- * for pri 0
- */
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
- /*
- * Number of bytes received during last PFC watchdog storm
- * for pri 1
- */
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
- /*
- * Number of bytes received during last PFC watchdog storm
- * for pri 2
- */
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
/*
- * Number of bytes received during last PFC watchdog storm
- * for pri 3
+ * Priority setting for VLAN PRI to CoS mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the corresponding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
+ uint8_t vlan_pri2cos_map_pri;
/*
- * Number of bytes received during last PFC watchdog storm
- * for pri 4
+ * In this field, a number of CoS mappings related flags
+ * are used to indicate configured CoS mappings.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
+ uint8_t flags;
/*
- * Number of bytes received during last PFC watchdog storm
- * for pri 5
+ * When this bit is set to '1', the inner VLAN PRI to CoS mapping
+ * is enabled.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
+ UINT32_C(0x1)
/*
- * Number of bytes received during last PFC watchdog storm
- * for pri 6
+ * When this bit is set to '1', tunnel VLAN PRI field to
+ * CoS mapping is enabled.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
+ UINT32_C(0x2)
/*
- * Number of bytes received during last PFC watchdog storm
- * for pri 7
+ * When this bit is set to '1', the IP DSCP to CoS mapping is
+ * enabled.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
+ UINT32_C(0x4)
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 0
+ * When this bit is '1', the Out-Of-Box WoL is enabled on this
+ * port.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
+ UINT32_C(0x8)
+ /* When this bit is '1', PTP is enabled for RX on this port. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x10)
+ /* When this bit is '1', PTP is enabled for TX on this port. */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
+ UINT32_C(0x20)
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 1
+ * Priority setting for tunnel VLAN PRI to CoS mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the corresponding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
+ uint8_t tunnel_pri2cos_map_pri;
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 2
+ * Priority setting for DSCP to PRI mapping.
+ * # Each XXX_pri variable shall have a unique priority value
+ * when it is being used.
+ * # When comparing priorities of mappings, higher value
+ * indicates higher priority.
+ * For example, a value of 0-3 is returned where 0 is being
+ * the lowest priority and 3 is being the highest priority.
+ * # If the corresponding CoS mapping is not enabled, then this
+ * field should be ignored.
+ * # This value indicates the normalized priority value retained
+ * in the HWRM.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
+ uint8_t dscp2pri_map_pri;
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 3
+ * This is a 16-bit bit mask that represents the
+ * current configuration of time stamp capture of PTP messages
+ * on the receive side of this port.
+ * If bit 'i' is set, then the receive side of the port
+ * is configured to capture the time stamp of every
+ * received PTP message with messageType field value set
+ * to i.
+ * If all bits are set to 0 (i.e. field value set 0),
+ * then the receive side of the port is not configured
+ * to capture timestamp for PTP messages.
+ * If all bits are set to 1, then the receive side of the
+ * port is configured to capture timestamp for all PTP
+ * messages.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
+ uint16_t rx_ts_capture_ptp_msg_type;
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 4
+ * This is a 16-bit bit mask that represents the
+ * current configuration of time stamp capture of PTP messages
+ * on the transmit side of this port.
+ * If bit 'i' is set, then the transmit side of the port
+ * is configured to capture the time stamp of every
+ * received PTP message with messageType field value set
+ * to i.
+ * If all bits are set to 0 (i.e. field value set 0),
+ * then the transmit side of the port is not configured
+ * to capture timestamp for PTP messages.
+ * If all bits are set to 1, then the transmit side of the
+ * port is configured to capture timestamp for all PTP
+ * messages.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
+ uint16_t tx_ts_capture_ptp_msg_type;
+ /* Configuration of CoS fields. */
+ uint8_t cos_field_cfg;
+ /* Reserved */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
+ UINT32_C(0x1)
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 5
+ * This field is used for selecting VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the inner packet headers of tunneled packets or
+ * non-tunneled packets.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x6)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
+ 1
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 6
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the inner packet headers
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 1)
/*
- * Number of packets dropped on rx during last PFC watchdog storm
- * for pri 7
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the inner packet headers.
+ * No VLAN PRI is selected for this configuration
+ * if only one VLAN Tag is present in the inner
+ * packet headers.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 1)
/*
- * Total number of bytes dropped on rx during PFC watchdog storm
- * for pri 0
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the inner packet headers
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 1)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 1)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 1
+ * This field is used for selecting tunnel VLAN PRI value
+ * based on whether one or two VLAN Tags are present in
+ * the tunnel headers of tunneled packets. This selection
+ * does not apply to non-tunneled packets.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
+ UINT32_C(0x18)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
+ 3
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 2
+ * Select inner VLAN PRI when 1 or 2 VLAN Tags are
+ * present in the tunnel packet headers
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
+ (UINT32_C(0x0) << 3)
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 3
+ * Select outer VLAN Tag PRI when 2 VLAN Tags are
+ * present in the tunnel packet headers.
+ * No VLAN PRI is selected for this configuration
+ * if only one VLAN Tag is present in the tunnel
+ * packet headers.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
+ (UINT32_C(0x1) << 3)
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 4
+ * Select outermost VLAN PRI when 1 or 2 VLAN Tags
+ * are present in the tunnel packet headers
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
+ (UINT32_C(0x2) << 3)
+ /* Unspecified */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
+ (UINT32_C(0x3) << 3)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
+ HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 5
+ * This field is used to provide default CoS value that
+ * has been configured on this port.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
+ 5
+ uint8_t unused_1;
+ uint16_t port_svif_info;
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 6
+ * This field specifies the source virtual interface of the port being
+ * queried. Drivers can use this to program port svif field in the
+ * L2 context table
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
+ UINT32_C(0x7fff)
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
+ /* This field specifies whether port_svif is valid or not */
+ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
+ UINT32_C(0x8000)
+ uint8_t unused_2[5];
/*
- * Number of bytes dropped on rx during last PFC watchdog storm
- * for pri 7
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
+ uint8_t valid;
} __rte_packed;
-/************************
- * hwrm_port_qstats_ext *
- ************************/
+/**************************
+ * hwrm_port_mac_ptp_qcfg *
+ **************************/
-/* hwrm_port_qstats_ext_input (size:320b/40B) */
-struct hwrm_port_qstats_ext_input {
+/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
+struct hwrm_port_mac_ptp_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint64_t resp_addr;
/* Port ID of port that is being queried. */
uint16_t port_id;
- /*
- * The size of TX port extended
- * statistics block in bytes.
- */
- uint16_t tx_stat_size;
- /*
- * The size of RX port extended
- * statistics block in bytes
- */
- uint16_t rx_stat_size;
- uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
- /*
- * This bit is set to 1 when request is for the counter mask,
- * representing width of each of the stats counters, rather than
- * counters themselves.
- */
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
- uint8_t unused_0;
- /*
- * This is the host address where
- * Tx port statistics will be stored
- */
- uint64_t tx_stat_host_addr;
- /*
- * This is the host address where
- * Rx port statistics will be stored
- */
- uint64_t rx_stat_host_addr;
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_qstats_ext_output (size:128b/16B) */
-struct hwrm_port_qstats_ext_output {
+/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
+struct hwrm_port_mac_ptp_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The size of TX port statistics block in bytes. */
- uint16_t tx_stat_size;
- /* The size of RX port statistics block in bytes. */
- uint16_t rx_stat_size;
- /* Total number of active cos queues available. */
- uint16_t total_active_cos_queues;
- uint8_t flags;
/*
- * If set to 1, then this field indicates that clear
- * roce specific counters is supported.
+ * In this field, a number of PTP related flags
+ * are used to indicate configured PTP capabilities.
*/
- #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
- UINT32_C(0x1)
+ uint8_t flags;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is set to '1', the PTP related registers are
+ * directly accessible by the host.
*/
- uint8_t valid;
-} __rte_packed;
-
-/*******************************
- * hwrm_port_qstats_ext_pfc_wd *
- *******************************/
-
-
-/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
-struct hwrm_port_qstats_ext_pfc_wd_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
+ UINT32_C(0x1)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * When this bit is set to '1', the PTP information is accessible
+ * via HWRM commands.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
+ UINT32_C(0x8)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * When this bit is set to '1', two specific registers for current
+ * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are
+ * directly accessible by the host.
*/
- uint16_t target_id;
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \
+ UINT32_C(0x10)
+ uint8_t unused_0[3];
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Offset of the PTP register for the lower 32 bits of timestamp
+ * for RX.
*/
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
+ uint32_t rx_ts_reg_off_lower;
/*
- * The size of rx_port_stats_ext_pfc_wd
- * block in bytes
+ * Offset of the PTP register for the upper 32 bits of timestamp
+ * for RX.
*/
- uint16_t pfc_wd_stat_size;
- uint8_t unused_0[4];
+ uint32_t rx_ts_reg_off_upper;
+ /* Offset of the PTP register for the sequence ID for RX. */
+ uint32_t rx_ts_reg_off_seq_id;
+ /* Offset of the first PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_0;
+ /* Offset of the second PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_1;
+ /* Offset of the third PTP source ID for RX. */
+ uint32_t rx_ts_reg_off_src_id_2;
+ /* Offset of the domain ID for RX. */
+ uint32_t rx_ts_reg_off_domain_id;
+ /* Offset of the PTP FIFO register for RX. */
+ uint32_t rx_ts_reg_off_fifo;
+ /* Offset of the PTP advance FIFO register for RX. */
+ uint32_t rx_ts_reg_off_fifo_adv;
+ /* PTP timestamp granularity for RX. */
+ uint32_t rx_ts_reg_off_granularity;
/*
- * This is the host address where
- * rx_port_stats_ext_pfc_wd will be stored
+ * Offset of the PTP register for the lower 32 bits of timestamp
+ * for TX.
*/
- uint64_t pfc_wd_stat_host_addr;
-} __rte_packed;
-
-/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
-struct hwrm_port_qstats_ext_pfc_wd_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ uint32_t tx_ts_reg_off_lower;
/*
- * The size of rx_port_stats_ext_pfc_wd
- * statistics block in bytes.
+ * Offset of the PTP register for the upper 32 bits of timestamp
+ * for TX.
*/
- uint16_t pfc_wd_stat_size;
- uint8_t flags;
+ uint32_t tx_ts_reg_off_upper;
+ /* Offset of the PTP register for the sequence ID for TX. */
+ uint32_t tx_ts_reg_off_seq_id;
+ /* Offset of the PTP FIFO register for TX. */
+ uint32_t tx_ts_reg_off_fifo;
+ /* PTP timestamp granularity for TX. */
+ uint32_t tx_ts_reg_off_granularity;
+ /* Offset of register to get lower 32 bits of current time. */
+ uint32_t ts_ref_clock_reg_lower;
+ /* Offset of register to get upper 32 bits of current time. */
+ uint32_t ts_ref_clock_reg_upper;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
- uint8_t unused_0[4];
} __rte_packed;
-/*************************
- * hwrm_port_lpbk_qstats *
- *************************/
-
-
-/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
-struct hwrm_port_lpbk_qstats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
+/* Port Tx Statistics Format */
+/* tx_port_stats (size:3264b/408B) */
+struct tx_port_stats {
+ /* Total Number of 64 Bytes frames transmitted */
+ uint64_t tx_64b_frames;
+ /* Total Number of 65-127 Bytes frames transmitted */
+ uint64_t tx_65b_127b_frames;
+ /* Total Number of 128-255 Bytes frames transmitted */
+ uint64_t tx_128b_255b_frames;
+ /* Total Number of 256-511 Bytes frames transmitted */
+ uint64_t tx_256b_511b_frames;
+ /* Total Number of 512-1023 Bytes frames transmitted */
+ uint64_t tx_512b_1023b_frames;
+ /* Total Number of 1024-1518 Bytes frames transmitted */
+ uint64_t tx_1024b_1518b_frames;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Total Number of each good VLAN (excludes FCS errors)
+ * frame transmitted which is 1519 to 1522 bytes in length
+ * inclusive (excluding framing bits but including FCS bytes).
*/
- uint16_t target_id;
+ uint64_t tx_good_vlan_frames;
+ /* Total Number of 1519-2047 Bytes frames transmitted */
+ uint64_t tx_1519b_2047b_frames;
+ /* Total Number of 2048-4095 Bytes frames transmitted */
+ uint64_t tx_2048b_4095b_frames;
+ /* Total Number of 4096-9216 Bytes frames transmitted */
+ uint64_t tx_4096b_9216b_frames;
+ /* Total Number of 9217-16383 Bytes frames transmitted */
+ uint64_t tx_9217b_16383b_frames;
+ /* Total Number of good frames transmitted */
+ uint64_t tx_good_frames;
+ /* Total Number of frames transmitted */
+ uint64_t tx_total_frames;
+ /* Total number of unicast frames transmitted */
+ uint64_t tx_ucast_frames;
+ /* Total number of multicast frames transmitted */
+ uint64_t tx_mcast_frames;
+ /* Total number of broadcast frames transmitted */
+ uint64_t tx_bcast_frames;
+ /* Total number of PAUSE control frames transmitted */
+ uint64_t tx_pause_frames;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of PFC/per-priority PAUSE
+ * control frames transmitted
*/
- uint64_t resp_addr;
-} __rte_packed;
-
-/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
-struct hwrm_port_lpbk_qstats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Number of transmitted unicast frames */
- uint64_t lpbk_ucast_frames;
- /* Number of transmitted multicast frames */
- uint64_t lpbk_mcast_frames;
- /* Number of transmitted broadcast frames */
- uint64_t lpbk_bcast_frames;
- /* Number of transmitted bytes for unicast traffic */
- uint64_t lpbk_ucast_bytes;
- /* Number of transmitted bytes for multicast traffic */
- uint64_t lpbk_mcast_bytes;
- /* Number of transmitted bytes for broadcast traffic */
- uint64_t lpbk_bcast_bytes;
- /* Total Tx Drops for loopback traffic reported by STATS block */
- uint64_t tx_stat_discard;
- /* Total Tx Error Drops for loopback traffic reported by STATS block */
- uint64_t tx_stat_error;
- /* Total Rx Drops for loopback traffic reported by STATS block */
- uint64_t rx_stat_discard;
- /* Total Rx Error Drops for loopback traffic reported by STATS block */
- uint64_t rx_stat_error;
- uint8_t unused_0[7];
+ uint64_t tx_pfc_frames;
+ /* Total number of jabber frames transmitted */
+ uint64_t tx_jabber_frames;
+ /* Total number of frames transmitted with FCS error */
+ uint64_t tx_fcs_err_frames;
+ /* Total number of control frames transmitted */
+ uint64_t tx_control_frames;
+ /* Total number of over-sized frames transmitted */
+ uint64_t tx_oversz_frames;
+ /* Total number of frames with single deferral */
+ uint64_t tx_single_dfrl_frames;
+ /* Total number of frames with multiple deferrals */
+ uint64_t tx_multi_dfrl_frames;
+ /* Total number of frames with single collision */
+ uint64_t tx_single_coll_frames;
+ /* Total number of frames with multiple collisions */
+ uint64_t tx_multi_coll_frames;
+ /* Total number of frames with late collisions */
+ uint64_t tx_late_coll_frames;
+ /* Total number of frames with excessive collisions */
+ uint64_t tx_excessive_coll_frames;
+ /* Total number of fragmented frames transmitted */
+ uint64_t tx_frag_frames;
+ /* Total number of transmit errors */
+ uint64_t tx_err;
+ /* Total number of single VLAN tagged frames transmitted */
+ uint64_t tx_tagged_frames;
+ /* Total number of double VLAN tagged frames transmitted */
+ uint64_t tx_dbl_tagged_frames;
+ /* Total number of runt frames transmitted */
+ uint64_t tx_runt_frames;
+ /* Total number of TX FIFO under runs */
+ uint64_t tx_fifo_underruns;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 0 transmitted
*/
- uint8_t valid;
-} __rte_packed;
-
-/************************
- * hwrm_port_ecn_qstats *
- ************************/
-
-
-/* hwrm_port_ecn_qstats_input (size:192b/24B) */
-struct hwrm_port_ecn_qstats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t tx_pfc_ena_frames_pri0;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 1 transmitted
*/
- uint16_t cmpl_ring;
+ uint64_t tx_pfc_ena_frames_pri1;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 2 transmitted
*/
- uint16_t seq_id;
+ uint64_t tx_pfc_ena_frames_pri2;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 3 transmitted
*/
- uint16_t target_id;
+ uint64_t tx_pfc_ena_frames_pri3;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 4 transmitted
*/
- uint64_t resp_addr;
+ uint64_t tx_pfc_ena_frames_pri4;
/*
- * Port ID of port that is being queried. Unused if NIC is in
- * multi-host mode.
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 5 transmitted
*/
- uint16_t port_id;
- uint8_t unused_0[6];
+ uint64_t tx_pfc_ena_frames_pri5;
+ /*
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 6 transmitted
+ */
+ uint64_t tx_pfc_ena_frames_pri6;
+ /*
+ * Total number of PFC frames with PFC enabled bit for
+ * Pri 7 transmitted
+ */
+ uint64_t tx_pfc_ena_frames_pri7;
+ /* Total number of EEE LPI Events on TX */
+ uint64_t tx_eee_lpi_events;
+ /* EEE LPI Duration Counter on TX */
+ uint64_t tx_eee_lpi_duration;
+ /*
+ * Total number of Link Level Flow Control (LLFC) messages
+ * transmitted
+ */
+ uint64_t tx_llfc_logical_msgs;
+ /* Total number of HCFC messages transmitted */
+ uint64_t tx_hcfc_msgs;
+ /* Total number of TX collisions */
+ uint64_t tx_total_collisions;
+ /* Total number of transmitted bytes */
+ uint64_t tx_bytes;
+ /* Total number of end-to-end HOL frames */
+ uint64_t tx_xthol_frames;
+ /* Total Tx Drops per Port reported by STATS block */
+ uint64_t tx_stat_discard;
+ /* Total Tx Error Drops per Port reported by STATS block */
+ uint64_t tx_stat_error;
} __rte_packed;
-/* hwrm_port_ecn_qstats_output (size:384b/48B) */
-struct hwrm_port_ecn_qstats_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Number of packets marked in CoS queue 0. */
- uint32_t mark_cnt_cos0;
- /* Number of packets marked in CoS queue 1. */
- uint32_t mark_cnt_cos1;
- /* Number of packets marked in CoS queue 2. */
- uint32_t mark_cnt_cos2;
- /* Number of packets marked in CoS queue 3. */
- uint32_t mark_cnt_cos3;
- /* Number of packets marked in CoS queue 4. */
- uint32_t mark_cnt_cos4;
- /* Number of packets marked in CoS queue 5. */
- uint32_t mark_cnt_cos5;
- /* Number of packets marked in CoS queue 6. */
- uint32_t mark_cnt_cos6;
- /* Number of packets marked in CoS queue 7. */
- uint32_t mark_cnt_cos7;
+/* Port Rx Statistics Format */
+/* rx_port_stats (size:4224b/528B) */
+struct rx_port_stats {
+ /* Total Number of 64 Bytes frames received */
+ uint64_t rx_64b_frames;
+ /* Total Number of 65-127 Bytes frames received */
+ uint64_t rx_65b_127b_frames;
+ /* Total Number of 128-255 Bytes frames received */
+ uint64_t rx_128b_255b_frames;
+ /* Total Number of 256-511 Bytes frames received */
+ uint64_t rx_256b_511b_frames;
+ /* Total Number of 512-1023 Bytes frames received */
+ uint64_t rx_512b_1023b_frames;
+ /* Total Number of 1024-1518 Bytes frames received */
+ uint64_t rx_1024b_1518b_frames;
/*
- * Bitmask that indicates which CoS queues have ECN marking enabled.
- * Bit i corresponds to CoS queue i.
+ * Total Number of each good VLAN (excludes FCS errors)
+ * frame received which is 1519 to 1522 bytes in length
+ * inclusive (excluding framing bits but including FCS bytes).
*/
- uint8_t mark_en;
- uint8_t unused_0[6];
+ uint64_t rx_good_vlan_frames;
+ /* Total Number of 1519-2047 Bytes frames received */
+ uint64_t rx_1519b_2047b_frames;
+ /* Total Number of 2048-4095 Bytes frames received */
+ uint64_t rx_2048b_4095b_frames;
+ /* Total Number of 4096-9216 Bytes frames received */
+ uint64_t rx_4096b_9216b_frames;
+ /* Total Number of 9217-16383 Bytes frames received */
+ uint64_t rx_9217b_16383b_frames;
+ /* Total number of frames received */
+ uint64_t rx_total_frames;
+ /* Total number of unicast frames received */
+ uint64_t rx_ucast_frames;
+ /* Total number of multicast frames received */
+ uint64_t rx_mcast_frames;
+ /* Total number of broadcast frames received */
+ uint64_t rx_bcast_frames;
+ /* Total number of received frames with FCS error */
+ uint64_t rx_fcs_err_frames;
+ /* Total number of control frames received */
+ uint64_t rx_ctrl_frames;
+ /* Total number of PAUSE frames received */
+ uint64_t rx_pause_frames;
+ /* Total number of PFC frames received */
+ uint64_t rx_pfc_frames;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of frames received with an unsupported
+ * opcode
*/
- uint8_t valid;
+ uint64_t rx_unsupported_opcode_frames;
+ /*
+ * Total number of frames received with an unsupported
+ * DA for pause and PFC
+ */
+ uint64_t rx_unsupported_da_pausepfc_frames;
+ /* Total number of frames received with an unsupported SA */
+ uint64_t rx_wrong_sa_frames;
+ /* Total number of received packets with alignment error */
+ uint64_t rx_align_err_frames;
+ /* Total number of received frames with out-of-range length */
+ uint64_t rx_oor_len_frames;
+ /* Total number of received frames with error termination */
+ uint64_t rx_code_err_frames;
+ /*
+ * Total number of received frames with a false carrier is
+ * detected during idle, as defined by RX_ER samples active
+ * and RXD is 0xE. The event is reported along with the
+ * statistics generated on the next received frame. Only
+ * one false carrier condition can be detected and logged
+ * between frames.
+ *
+ * Carrier event, valid for 10M/100M speed modes only.
+ */
+ uint64_t rx_false_carrier_frames;
+ /* Total number of over-sized frames received */
+ uint64_t rx_ovrsz_frames;
+ /* Total number of jabber packets received */
+ uint64_t rx_jbr_frames;
+ /* Total number of received frames with MTU error */
+ uint64_t rx_mtu_err_frames;
+ /* Total number of received frames with CRC match */
+ uint64_t rx_match_crc_frames;
+ /* Total number of frames received promiscuously */
+ uint64_t rx_promiscuous_frames;
+ /*
+ * Total number of received frames with one or two VLAN
+ * tags
+ */
+ uint64_t rx_tagged_frames;
+ /* Total number of received frames with two VLAN tags */
+ uint64_t rx_double_tagged_frames;
+ /* Total number of truncated frames received */
+ uint64_t rx_trunc_frames;
+ /* Total number of good frames (without errors) received */
+ uint64_t rx_good_frames;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 0
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri0;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 1
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri1;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 2
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri2;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 3
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri3;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 4
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri4;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 5
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri5;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 6
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri6;
+ /*
+ * Total number of received PFC frames with transition from
+ * XON to XOFF on Pri 7
+ */
+ uint64_t rx_pfc_xon2xoff_frames_pri7;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 0
+ */
+ uint64_t rx_pfc_ena_frames_pri0;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 1
+ */
+ uint64_t rx_pfc_ena_frames_pri1;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 2
+ */
+ uint64_t rx_pfc_ena_frames_pri2;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 3
+ */
+ uint64_t rx_pfc_ena_frames_pri3;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 4
+ */
+ uint64_t rx_pfc_ena_frames_pri4;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 5
+ */
+ uint64_t rx_pfc_ena_frames_pri5;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 6
+ */
+ uint64_t rx_pfc_ena_frames_pri6;
+ /*
+ * Total number of received PFC frames with PFC enabled
+ * bit for Pri 7
+ */
+ uint64_t rx_pfc_ena_frames_pri7;
+ /* Total Number of frames received with SCH CRC error */
+ uint64_t rx_sch_crc_err_frames;
+ /* Total Number of under-sized frames received */
+ uint64_t rx_undrsz_frames;
+ /* Total Number of fragmented frames received */
+ uint64_t rx_frag_frames;
+ /* Total number of RX EEE LPI Events */
+ uint64_t rx_eee_lpi_events;
+ /* EEE LPI Duration Counter on RX */
+ uint64_t rx_eee_lpi_duration;
+ /*
+ * Total number of physical type Link Level Flow Control
+ * (LLFC) messages received
+ */
+ uint64_t rx_llfc_physical_msgs;
+ /*
+ * Total number of logical type Link Level Flow Control
+ * (LLFC) messages received
+ */
+ uint64_t rx_llfc_logical_msgs;
+ /*
+ * Total number of logical type Link Level Flow Control
+ * (LLFC) messages received with CRC error
+ */
+ uint64_t rx_llfc_msgs_with_crc_err;
+ /* Total number of HCFC messages received */
+ uint64_t rx_hcfc_msgs;
+ /* Total number of HCFC messages received with CRC error */
+ uint64_t rx_hcfc_msgs_with_crc_err;
+ /* Total number of received bytes */
+ uint64_t rx_bytes;
+ /* Total number of bytes received in runt frames */
+ uint64_t rx_runt_bytes;
+ /* Total number of runt frames received */
+ uint64_t rx_runt_frames;
+ /* Total Rx Discards per Port reported by STATS block */
+ uint64_t rx_stat_discard;
+ uint64_t rx_stat_err;
} __rte_packed;
-/***********************
- * hwrm_port_clr_stats *
- ***********************/
+/********************
+ * hwrm_port_qstats *
+ ********************/
-/* hwrm_port_clr_stats_input (size:192b/24B) */
-struct hwrm_port_clr_stats_input {
+/* hwrm_port_qstats_input (size:320b/40B) */
+struct hwrm_port_qstats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
/* Port ID of port that is being queried. */
uint16_t port_id;
uint8_t flags;
+ /* This value is not used to avoid backward compatibility issues. */
+ #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * If set to 1, then this field indicates clear the following RoCE
- * specific counters.
- * RoCE associated TX/RX cos counters
- * CNP associated TX/RX cos counters
- * RoCE/CNP specific TX/RX flow counters
- * Firmware will determine the RoCE/CNP cos queue based on qos profile.
- * This flag is honored only when RoCE is enabled on that port.
+ * This bit is set to 1 when request is for a counter mask,
+ * representing the width of each of the stats counters, rather
+ * than counters themselves.
*/
- #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
+ #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
+ #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
+ HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
uint8_t unused_0[5];
+ /*
+ * This is the host address where
+ * Tx port statistics will be stored
+ */
+ uint64_t tx_stat_host_addr;
+ /*
+ * This is the host address where
+ * Rx port statistics will be stored
+ */
+ uint64_t rx_stat_host_addr;
} __rte_packed;
-/* hwrm_port_clr_stats_output (size:128b/16B) */
-struct hwrm_port_clr_stats_output {
+/* hwrm_port_qstats_output (size:128b/16B) */
+struct hwrm_port_qstats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The size of TX port statistics block in bytes. */
+ uint16_t tx_stat_size;
+ /* The size of RX port statistics block in bytes. */
+ uint16_t rx_stat_size;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_port_phy_qcaps *
- ***********************/
-
+/* Port Tx Statistics extended Format */
+/* tx_port_stats_ext (size:2048b/256B) */
+struct tx_port_stats_ext {
+ /* Total number of tx bytes count on cos queue 0 */
+ uint64_t tx_bytes_cos0;
+ /* Total number of tx bytes count on cos queue 1 */
+ uint64_t tx_bytes_cos1;
+ /* Total number of tx bytes count on cos queue 2 */
+ uint64_t tx_bytes_cos2;
+ /* Total number of tx bytes count on cos queue 3 */
+ uint64_t tx_bytes_cos3;
+ /* Total number of tx bytes count on cos queue 4 */
+ uint64_t tx_bytes_cos4;
+ /* Total number of tx bytes count on cos queue 5 */
+ uint64_t tx_bytes_cos5;
+ /* Total number of tx bytes count on cos queue 6 */
+ uint64_t tx_bytes_cos6;
+ /* Total number of tx bytes count on cos queue 7 */
+ uint64_t tx_bytes_cos7;
+ /* Total number of tx packets count on cos queue 0 */
+ uint64_t tx_packets_cos0;
+ /* Total number of tx packets count on cos queue 1 */
+ uint64_t tx_packets_cos1;
+ /* Total number of tx packets count on cos queue 2 */
+ uint64_t tx_packets_cos2;
+ /* Total number of tx packets count on cos queue 3 */
+ uint64_t tx_packets_cos3;
+ /* Total number of tx packets count on cos queue 4 */
+ uint64_t tx_packets_cos4;
+ /* Total number of tx packets count on cos queue 5 */
+ uint64_t tx_packets_cos5;
+ /* Total number of tx packets count on cos queue 6 */
+ uint64_t tx_packets_cos6;
+ /* Total number of tx packets count on cos queue 7 */
+ uint64_t tx_packets_cos7;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
+ uint64_t pfc_pri0_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
+ uint64_t pfc_pri0_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
+ uint64_t pfc_pri1_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
+ uint64_t pfc_pri1_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
+ uint64_t pfc_pri2_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
+ uint64_t pfc_pri2_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
+ uint64_t pfc_pri3_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
+ uint64_t pfc_pri3_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
+ uint64_t pfc_pri4_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
+ uint64_t pfc_pri4_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
+ uint64_t pfc_pri5_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
+ uint64_t pfc_pri5_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
+ uint64_t pfc_pri6_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
+ uint64_t pfc_pri6_tx_transitions;
+ /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
+ uint64_t pfc_pri7_tx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
+ uint64_t pfc_pri7_tx_transitions;
+} __rte_packed;
-/* hwrm_port_phy_qcaps_input (size:192b/24B) */
-struct hwrm_port_phy_qcaps_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* Port ID of port that is being queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
+/* Port Rx Statistics extended Format */
+/* rx_port_stats_ext (size:3776b/472B) */
+struct rx_port_stats_ext {
+ /* Number of times link state changed to down */
+ uint64_t link_down_events;
+ /* Number of times the idle rings with pause bit are found */
+ uint64_t continuous_pause_events;
+ /* Number of times the active rings pause bit resumed back */
+ uint64_t resume_pause_events;
+ /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
+ uint64_t continuous_roce_pause_events;
+ /* Number of times, the ROCE cos queue PFC is enabled back */
+ uint64_t resume_roce_pause_events;
+ /* Total number of rx bytes count on cos queue 0 */
+ uint64_t rx_bytes_cos0;
+ /* Total number of rx bytes count on cos queue 1 */
+ uint64_t rx_bytes_cos1;
+ /* Total number of rx bytes count on cos queue 2 */
+ uint64_t rx_bytes_cos2;
+ /* Total number of rx bytes count on cos queue 3 */
+ uint64_t rx_bytes_cos3;
+ /* Total number of rx bytes count on cos queue 4 */
+ uint64_t rx_bytes_cos4;
+ /* Total number of rx bytes count on cos queue 5 */
+ uint64_t rx_bytes_cos5;
+ /* Total number of rx bytes count on cos queue 6 */
+ uint64_t rx_bytes_cos6;
+ /* Total number of rx bytes count on cos queue 7 */
+ uint64_t rx_bytes_cos7;
+ /* Total number of rx packets count on cos queue 0 */
+ uint64_t rx_packets_cos0;
+ /* Total number of rx packets count on cos queue 1 */
+ uint64_t rx_packets_cos1;
+ /* Total number of rx packets count on cos queue 2 */
+ uint64_t rx_packets_cos2;
+ /* Total number of rx packets count on cos queue 3 */
+ uint64_t rx_packets_cos3;
+ /* Total number of rx packets count on cos queue 4 */
+ uint64_t rx_packets_cos4;
+ /* Total number of rx packets count on cos queue 5 */
+ uint64_t rx_packets_cos5;
+ /* Total number of rx packets count on cos queue 6 */
+ uint64_t rx_packets_cos6;
+ /* Total number of rx packets count on cos queue 7 */
+ uint64_t rx_packets_cos7;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
+ uint64_t pfc_pri0_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
+ uint64_t pfc_pri0_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
+ uint64_t pfc_pri1_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
+ uint64_t pfc_pri1_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
+ uint64_t pfc_pri2_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
+ uint64_t pfc_pri2_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
+ uint64_t pfc_pri3_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
+ uint64_t pfc_pri3_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
+ uint64_t pfc_pri4_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
+ uint64_t pfc_pri4_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
+ uint64_t pfc_pri5_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
+ uint64_t pfc_pri5_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
+ uint64_t pfc_pri6_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
+ uint64_t pfc_pri6_rx_transitions;
+ /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
+ uint64_t pfc_pri7_rx_duration_us;
+ /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
+ uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * algorithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
+ /* Total number of FEC blocks corrected by the FEC function in the PHY */
+ uint64_t rx_fec_corrected_blocks;
+ /*
+ * Total number of FEC blocks determined to be uncorrectable by the
+ * FEC function in the PHY
+ */
+ uint64_t rx_fec_uncorrectable_blocks;
} __rte_packed;
-/* hwrm_port_phy_qcaps_output (size:192b/24B) */
-struct hwrm_port_phy_qcaps_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* PHY capability flags */
- uint8_t flags;
+/*
+ * Port Rx Statistics extended PFC WatchDog Format.
+ * StormDetect and StormRevert event determination is based
+ * on an integration period and a percentage threshold.
+ * StormDetect event - when percentage of XOFF frames received
+ * within an integration period exceeds the configured threshold.
+ * StormRevert event - when percentage of XON frames received
+ * within an integration period exceeds the configured threshold.
+ * Actual number of XOFF/XON frames for the events to be triggered
+ * depends on both configured integration period and sampling rate.
+ * The statistics in this structure represent counts of specified
+ * events from the moment the feature (PFC WatchDog) is enabled via
+ * hwrm_queue_pfc_enable_cfg call.
+ */
+/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
+struct rx_port_stats_ext_pfc_wd {
/*
- * If set to 1, then this field indicates that the
- * link is capable of supporting EEE.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 0
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
- UINT32_C(0x1)
+ uint64_t rx_pfc_watchdog_storms_detected_pri0;
/*
- * If set to 1, then this field indicates that the
- * PHY is capable of supporting external loopback.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 1
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
- UINT32_C(0x2)
+ uint64_t rx_pfc_watchdog_storms_detected_pri1;
/*
- * If set to 1, then this field indicates that the
- * PHY is capable of supporting loopback in autoneg mode.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 2
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
- UINT32_C(0x4)
+ uint64_t rx_pfc_watchdog_storms_detected_pri2;
/*
- * Indicates if the configuration of shared PHY settings is supported.
- * In cases where a physical port is shared by multiple functions
- * (e.g. NPAR, multihost, etc), the configuration of PHY
- * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
- * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 3
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
- UINT32_C(0x8)
+ uint64_t rx_pfc_watchdog_storms_detected_pri3;
/*
- * Reserved field. The HWRM shall set this field to 0.
- * An HWRM client shall ignore this field.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 4
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
- UINT32_C(0xf0)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
- /* Number of front panel ports for this device. */
- uint8_t port_cnt;
- /* Not supported or unknown */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
- /* single port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
- /* 2-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
- /* 3-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
- /* 4-port device */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
- HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
+ uint64_t rx_pfc_watchdog_storms_detected_pri4;
/*
- * This is a bit mask to indicate what speeds are supported
- * as forced speeds on this link.
- * For each speed that can be forced on this link, the
- * corresponding mask bit shall be set to '1'.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 5
*/
- uint16_t supported_speeds_force_mode;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
- UINT32_C(0x2000)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
- UINT32_C(0x4000)
+ uint64_t rx_pfc_watchdog_storms_detected_pri5;
/*
- * This is a bit mask to indicate what speeds are supported
- * for autonegotiation on this link.
- * For each speed that can be autonegotiated on this link, the
- * corresponding mask bit shall be set to '1'.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 6
*/
- uint16_t supported_speeds_auto_mode;
- /* 100Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
- UINT32_C(0x2)
- /* 1Gb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
- UINT32_C(0x8)
- /* 2Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
- UINT32_C(0x10)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
- UINT32_C(0x40)
- /* 20Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
- UINT32_C(0x80)
- /* 25Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
- UINT32_C(0x100)
- /* 40Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
- UINT32_C(0x200)
- /* 50Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
- UINT32_C(0x400)
- /* 100Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
- UINT32_C(0x800)
- /* 10Mb link speed (Half-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
- UINT32_C(0x1000)
- /* 10Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
- UINT32_C(0x2000)
- /* 200Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
- UINT32_C(0x4000)
+ uint64_t rx_pfc_watchdog_storms_detected_pri6;
/*
- * This is a bit mask to indicate what speeds are supported
- * for EEE on this link.
- * For each speed that can be autonegotiated when EEE is enabled
- * on this link, the corresponding mask bit shall be set to '1'.
- * This field is only valid when the eee_suppotred is set to '1'.
+ * Total number of PFC WatchDog StormDetect events detected
+ * for Pri 7
*/
- uint16_t supported_speeds_eee_mode;
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
- UINT32_C(0x1)
- /* 100Mb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
- UINT32_C(0x2)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
- UINT32_C(0x4)
- /* 1Gb link speed (Full-duplex) */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
- UINT32_C(0x8)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
- UINT32_C(0x10)
- /* Reserved */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
- UINT32_C(0x20)
- /* 10Gb link speed */
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
- UINT32_C(0x40)
- uint32_t tx_lpi_timer_low;
+ uint64_t rx_pfc_watchdog_storms_detected_pri7;
/*
- * The lowest value of TX LPI timer that can be set on this link
- * when EEE is enabled. This value is in microseconds.
- * This field is valid only when_eee_supported is set to '1'.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 0
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
+ uint64_t rx_pfc_watchdog_storms_reverted_pri0;
/*
- * Reserved field. The HWRM shall set this field to 0.
- * An HWRM client shall ignore this field.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 1
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
- uint32_t valid_tx_lpi_timer_high;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri1;
/*
- * The highest value of TX LPI timer that can be set on this link
- * when EEE is enabled. This value is in microseconds.
- * This field is valid only when_eee_supported is set to '1'.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 2
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
- UINT32_C(0xffffff)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
+ uint64_t rx_pfc_watchdog_storms_reverted_pri2;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 3
*/
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
- UINT32_C(0xff000000)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
-} __rte_packed;
-
-/****************************
- * hwrm_port_phy_mdio_write *
- ****************************/
-
-
-/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
-struct hwrm_port_phy_mdio_write_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri3;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 4
*/
- uint16_t cmpl_ring;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri4;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 5
*/
- uint16_t seq_id;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri5;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 6
*/
- uint16_t target_id;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri6;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of PFC WatchDog StormRevert events detected
+ * for Pri 7
*/
- uint64_t resp_addr;
- /* Reserved for future use. */
- uint32_t unused_0[2];
- /* Port ID of port. */
- uint16_t port_id;
- /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
- uint8_t phy_addr;
- /* 8-bit device address. */
- uint8_t dev_addr;
- /* 16-bit register address. */
- uint16_t reg_addr;
- /* 16-bit register data. */
- uint16_t reg_data;
+ uint64_t rx_pfc_watchdog_storms_reverted_pri7;
/*
- * When this bit is set to 1 a Clause 45 mdio access is done.
- * when this bit is set to 0 a Clause 22 mdio access is done.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 0
*/
- uint8_t cl45_mdio;
- /* */
- uint8_t unused_1[7];
-} __rte_packed;
-
-/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
-struct hwrm_port_phy_mdio_write_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 1
*/
- uint8_t valid;
-} __rte_packed;
-
-/***************************
- * hwrm_port_phy_mdio_read *
- ***************************/
-
-
-/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
-struct hwrm_port_phy_mdio_read_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 2
*/
- uint16_t cmpl_ring;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 3
*/
- uint16_t seq_id;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Total number of packets received during PFC watchdog storm
+ * for pri 4
*/
- uint16_t target_id;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 5
*/
- uint64_t resp_addr;
- /* Reserved for future use. */
- uint32_t unused_0[2];
- /* Port ID of port. */
- uint16_t port_id;
- /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
- uint8_t phy_addr;
- /* 8-bit device address. */
- uint8_t dev_addr;
- /* 16-bit register address. */
- uint16_t reg_addr;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
/*
- * When this bit is set to 1 a Clause 45 mdio access is done.
- * when this bit is set to 0 a Clause 22 mdio access is done.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 6
*/
- uint8_t cl45_mdio;
- /* */
- uint8_t unused_1;
-} __rte_packed;
-
-/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
-struct hwrm_port_phy_mdio_read_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* 16-bit register data. */
- uint16_t reg_data;
- uint8_t unused_0[5];
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Total number of packets received during PFC watchdog storm
+ * for pri 7
*/
- uint8_t valid;
-} __rte_packed;
-
-/*********************
- * hwrm_port_led_cfg *
- *********************/
-
-
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 0
*/
- uint16_t cmpl_ring;
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 1
*/
- uint16_t seq_id;
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 2
*/
- uint16_t target_id;
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 3
*/
- uint64_t resp_addr;
- uint32_t enables;
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 4
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 5
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 6
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * Total number of bytes received during PFC watchdog storm
+ * for pri 7
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 0
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 1
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 2
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
- UINT32_C(0x40)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
/*
- * This bit must be '1' for the led1_state field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 3
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
- UINT32_C(0x80)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
/*
- * This bit must be '1' for the led1_color field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 4
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
- UINT32_C(0x100)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
/*
- * This bit must be '1' for the led1_blink_on field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 5
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
- UINT32_C(0x200)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
/*
- * This bit must be '1' for the led1_blink_off field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 6
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
- UINT32_C(0x400)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
/*
- * This bit must be '1' for the led1_group_id field to be
- * configured.
+ * Total number of packets dropped on rx during PFC watchdog storm
+ * for pri 7
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
- UINT32_C(0x800)
+ uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
/*
- * This bit must be '1' for the led2_id field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 0
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
- UINT32_C(0x1000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
/*
- * This bit must be '1' for the led2_state field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 1
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
- UINT32_C(0x2000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
/*
- * This bit must be '1' for the led2_color field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 2
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
- UINT32_C(0x4000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
/*
- * This bit must be '1' for the led2_blink_on field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 3
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
- UINT32_C(0x8000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
/*
- * This bit must be '1' for the led2_blink_off field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 4
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
- UINT32_C(0x10000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
/*
- * This bit must be '1' for the led2_group_id field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 5
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
- UINT32_C(0x20000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
/*
- * This bit must be '1' for the led3_id field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 6
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
- UINT32_C(0x40000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
/*
- * This bit must be '1' for the led3_state field to be
- * configured.
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 7
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
- UINT32_C(0x80000)
+ uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
/*
- * This bit must be '1' for the led3_color field to be
- * configured.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 0
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
- UINT32_C(0x100000)
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
/*
- * This bit must be '1' for the led3_blink_on field to be
- * configured.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 1
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
- UINT32_C(0x200000)
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
/*
- * This bit must be '1' for the led3_blink_off field to be
- * configured.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 2
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
- UINT32_C(0x400000)
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
/*
- * This bit must be '1' for the led3_group_id field to be
- * configured.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 3
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
- UINT32_C(0x800000)
- /* Port ID of port whose LEDs are configured. */
- uint16_t port_id;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
/*
- * The number of LEDs that are being configured.
- * Up to 4 LEDs can be configured with this command.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 4
*/
- uint8_t num_leds;
- /* Reserved field. */
- uint8_t rsvd;
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The requested state of the LED #0. */
- uint8_t led0_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
- /* The requested color of LED #0. */
- uint8_t led0_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
- uint8_t unused_0;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
/*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 5
*/
- uint16_t led0_blink_on;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
/*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 6
*/
- uint16_t led0_blink_off;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
/*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #0 shall
- * be grouped together with the LEDs with the same group ID
- * value.
+ * Number of packets received during last PFC watchdog storm
+ * for pri 7
*/
- uint8_t led0_group_id;
- /* Reserved field. */
- uint8_t rsvd0;
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The requested state of the LED #1. */
- uint8_t led1_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
- /* The requested color of LED #1. */
- uint8_t led1_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
- uint8_t unused_1;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
/*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 0
*/
- uint16_t led1_blink_on;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
/*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 1
*/
- uint16_t led1_blink_off;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
/*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #1 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #1 shall
- * be grouped together with the LEDs with the same group ID
- * value.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 2
*/
- uint8_t led1_group_id;
- /* Reserved field. */
- uint8_t rsvd1;
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The requested state of the LED #2. */
- uint8_t led2_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
- /* The requested color of LED #2. */
- uint8_t led2_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
- uint8_t unused_2;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 3
*/
- uint16_t led2_blink_on;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 4
*/
- uint16_t led2_blink_off;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
/*
- * An identifier for the group of LEDs that LED #2 belongs
- * to.
- * If set to 0, then the LED #2 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #2 shall
- * be grouped together with the LEDs with the same group ID
- * value.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 5
*/
- uint8_t led2_group_id;
- /* Reserved field. */
- uint8_t rsvd2;
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The requested state of the LED #3. */
- uint8_t led3_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
- /* The requested color of LED #3. */
- uint8_t led3_color;
- /* Default */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
- HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
- uint8_t unused_3;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
/*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 6
*/
- uint16_t led3_blink_on;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
/*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * Number of bytes received during last PFC watchdog storm
+ * for pri 7
*/
- uint16_t led3_blink_off;
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
/*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #3 shall not be grouped and
- * shall be treated as an individual resource.
- * For all other non-zero values of this field, LED #3 shall
- * be grouped together with the LEDs with the same group ID
- * value.
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 0
*/
- uint8_t led3_group_id;
- /* Reserved field. */
- uint8_t rsvd3;
-} __rte_packed;
-
-/* hwrm_port_led_cfg_output (size:128b/16B) */
-struct hwrm_port_led_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 1
*/
- uint8_t valid;
-} __rte_packed;
-
-/**********************
- * hwrm_port_led_qcfg *
- **********************/
-
-
-/* hwrm_port_led_qcfg_input (size:192b/24B) */
-struct hwrm_port_led_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 2
*/
- uint16_t cmpl_ring;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 3
*/
- uint16_t seq_id;
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
+ /*
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 4
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
+ /*
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 5
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
+ /*
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 6
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
+ /*
+ * Number of packets dropped on rx during last PFC watchdog storm
+ * for pri 7
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
+ /*
+ * Total number of bytes dropped on rx during PFC watchdog storm
+ * for pri 0
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 1
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 2
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 3
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 4
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 5
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 6
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
+ /*
+ * Number of bytes dropped on rx during last PFC watchdog storm
+ * for pri 7
+ */
+ uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
+} __rte_packed;
+
+/************************
+ * hwrm_port_qstats_ext *
+ ************************/
+
+
+/* hwrm_port_qstats_ext_input (size:320b/40B) */
+struct hwrm_port_qstats_ext_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port whose LED configuration is being queried. */
+ /* Port ID of port that is being queried. */
uint16_t port_id;
- uint8_t unused_0[6];
+ /*
+ * The size of TX port extended
+ * statistics block in bytes.
+ */
+ uint16_t tx_stat_size;
+ /*
+ * The size of RX port extended
+ * statistics block in bytes
+ */
+ uint16_t rx_stat_size;
+ uint8_t flags;
+ /* This value is not used to avoid backward compatibility issues. */
+ #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
+ /*
+ * This bit is set to 1 when request is for the counter mask,
+ * representing width of each of the stats counters, rather than
+ * counters themselves.
+ */
+ #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
+ #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
+ HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
+ uint8_t unused_0;
+ /*
+ * This is the host address where
+ * Tx port statistics will be stored
+ */
+ uint64_t tx_stat_host_addr;
+ /*
+ * This is the host address where
+ * Rx port statistics will be stored
+ */
+ uint64_t rx_stat_host_addr;
} __rte_packed;
-/* hwrm_port_led_qcfg_output (size:448b/56B) */
-struct hwrm_port_led_qcfg_output {
+/* hwrm_port_qstats_ext_output (size:128b/16B) */
+struct hwrm_port_qstats_ext_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* The size of TX port statistics block in bytes. */
+ uint16_t tx_stat_size;
+ /* The size of RX port statistics block in bytes. */
+ uint16_t rx_stat_size;
+ /* Total number of active cos queues available. */
+ uint16_t total_active_cos_queues;
+ uint8_t flags;
/*
- * The number of LEDs that are configured on this port.
- * Up to 4 LEDs can be returned in the response.
- */
- uint8_t num_leds;
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The type of LED #0. */
- uint8_t led0_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
- /* The current state of the LED #0. */
- uint8_t led0_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
- /* The color of LED #0. */
- uint8_t led0_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
- uint8_t unused_0;
- /*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
- */
- uint16_t led0_blink_on;
- /*
- * If the LED #0 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
- */
- uint16_t led0_blink_off;
- /*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 is not grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led0_group_id;
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The type of LED #1. */
- uint8_t led1_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
- /* The current state of the LED #1. */
- uint8_t led1_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
- /* The color of LED #1. */
- uint8_t led1_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
- uint8_t unused_1;
- /*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * If set to 1, then this field indicates that clear
+ * roce specific counters is supported.
*/
- uint16_t led1_blink_on;
+ #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
+ UINT32_C(0x1)
/*
- * If the LED #1 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t led1_blink_off;
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_port_qstats_ext_pfc_wd *
+ *******************************/
+
+
+/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
+struct hwrm_port_qstats_ext_pfc_wd_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #1 is not grouped.
- * For all other non-zero values of this field, LED #1 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t led1_group_id;
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The type of LED #2. */
- uint8_t led2_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
- /* The current state of the LED #2. */
- uint8_t led2_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
- /* The color of LED #2. */
- uint8_t led2_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
- uint8_t unused_2;
+ uint16_t cmpl_ring;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t led2_blink_on;
+ uint16_t seq_id;
/*
- * If the LED #2 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint16_t led2_blink_off;
+ uint16_t target_id;
/*
- * An identifier for the group of LEDs that LED #2 belongs
- * to.
- * If set to 0, then the LED #2 is not grouped.
- * For all other non-zero values of this field, LED #2 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t led2_group_id;
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The type of LED #3. */
- uint8_t led3_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
- /* The current state of the LED #3. */
- uint8_t led3_state;
- /* Default state of the LED */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
- /* Off */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
- /* On */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
- /* Blink */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
- /* Blink Alternately */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
- /* The color of LED #3. */
- uint8_t led3_color;
- /* Default */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
- /* Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
- /* Green */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
- /* Green or Amber */
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
- #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
- HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
- uint8_t unused_3;
+ uint64_t resp_addr;
+ /* Port ID of port that is being queried. */
+ uint16_t port_id;
/*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED on between cycles.
+ * The size of rx_port_stats_ext_pfc_wd
+ * block in bytes
*/
- uint16_t led3_blink_on;
+ uint16_t pfc_wd_stat_size;
+ uint8_t unused_0[4];
/*
- * If the LED #3 state is "blink" or "blinkalt", then
- * this field represents the requested time in milliseconds
- * to keep LED off between cycles.
+ * This is the host address where
+ * rx_port_stats_ext_pfc_wd will be stored
*/
- uint16_t led3_blink_off;
+ uint64_t pfc_wd_stat_host_addr;
+} __rte_packed;
+
+/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
+struct hwrm_port_qstats_ext_pfc_wd_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #3 is not grouped.
- * For all other non-zero values of this field, LED #3 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * The size of rx_port_stats_ext_pfc_wd
+ * statistics block in bytes.
*/
- uint8_t led3_group_id;
- uint8_t unused_4[6];
+ uint16_t pfc_wd_stat_size;
+ uint8_t flags;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
+ uint8_t unused_0[4];
} __rte_packed;
-/***********************
- * hwrm_port_led_qcaps *
- ***********************/
+/*************************
+ * hwrm_port_lpbk_qstats *
+ *************************/
-/* hwrm_port_led_qcaps_input (size:192b/24B) */
-struct hwrm_port_led_qcaps_input {
+/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
+struct hwrm_port_lpbk_qstats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of port whose LED configuration is being queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_led_qcaps_output (size:384b/48B) */
-struct hwrm_port_led_qcaps_output {
+/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
+struct hwrm_port_lpbk_qstats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* Number of transmitted unicast frames */
+ uint64_t lpbk_ucast_frames;
+ /* Number of transmitted multicast frames */
+ uint64_t lpbk_mcast_frames;
+ /* Number of transmitted broadcast frames */
+ uint64_t lpbk_bcast_frames;
+ /* Number of transmitted bytes for unicast traffic */
+ uint64_t lpbk_ucast_bytes;
+ /* Number of transmitted bytes for multicast traffic */
+ uint64_t lpbk_mcast_bytes;
+ /* Number of transmitted bytes for broadcast traffic */
+ uint64_t lpbk_bcast_bytes;
+ /* Total Tx Drops for loopback traffic reported by STATS block */
+ uint64_t tx_stat_discard;
+ /* Total Tx Error Drops for loopback traffic reported by STATS block */
+ uint64_t tx_stat_error;
+ /* Total Rx Drops for loopback traffic reported by STATS block */
+ uint64_t rx_stat_discard;
+ /* Total Rx Error Drops for loopback traffic reported by STATS block */
+ uint64_t rx_stat_error;
+ uint8_t unused_0[7];
/*
- * The number of LEDs that are configured on this port.
- * Up to 4 LEDs can be returned in the response.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t num_leds;
- /* Reserved for future use. */
- uint8_t unused[3];
- /* An identifier for the LED #0. */
- uint8_t led0_id;
- /* The type of LED #0. */
- uint8_t led0_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_port_ecn_qstats *
+ ************************/
+
+
+/* hwrm_port_ecn_qstats_input (size:256b/32B) */
+struct hwrm_port_ecn_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t led0_group_id;
- uint8_t unused_0;
- /* The states supported by LED #0. */
- uint16_t led0_state_caps;
+ uint16_t cmpl_ring;
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
- /*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
- /*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
- /*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
- /*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #0. */
- uint16_t led0_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
- UINT32_C(0x1)
- /*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
- /*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- /* An identifier for the LED #1. */
- uint8_t led1_id;
- /* The type of LED #1. */
- uint8_t led1_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
- /*
- * An identifier for the group of LEDs that LED #1 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led1_group_id;
- uint8_t unused_1;
- /* The states supported by LED #1. */
- uint16_t led1_state_caps;
- /*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
- /*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
- /*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
- /*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
- /*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #1. */
- uint16_t led1_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
- UINT32_C(0x1)
- /*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
- /*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
- */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- /* An identifier for the LED #2. */
- uint8_t led2_id;
- /* The type of LED #2. */
- uint8_t led2_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
- /*
- * An identifier for the group of LEDs that LED #0 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
- */
- uint8_t led2_group_id;
- uint8_t unused_2;
- /* The states supported by LED #2. */
- uint16_t led2_state_caps;
+ uint16_t seq_id;
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
+ uint16_t target_id;
/*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
+ uint64_t resp_addr;
/*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
+ * Port ID of port that is being queried. Unused if NIC is in
+ * multi-host mode.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
+ uint16_t port_id;
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * Size of the DMA buffer the caller has allocated for the firmware to
+ * write into.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
+ uint16_t ecn_stat_buf_size;
+ uint8_t flags;
+ /* This value is not used to avoid backward compatibility issues. */
+ #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * This bit is set to 1 when request is for a counter mask,
+ * representing the width of each of the stats counters, rather
+ * than counters themselves.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #2. */
- uint16_t led2_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
- UINT32_C(0x1)
+ #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
+ #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
+ HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ uint8_t unused_0[3];
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * This is the host address where
+ * ECN port statistics will be stored
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
+ uint64_t ecn_stat_host_addr;
+} __rte_packed;
+
+/* hwrm_port_ecn_qstats_output (size:128b/16B) */
+struct hwrm_port_ecn_qstats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of bytes of stats the firmware wrote to the DMA buffer. */
+ uint16_t ecn_stat_buf_size;
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
+ * Bitmask that indicates which CoS queues have ECN marking enabled.
+ * Bit i corresponds to CoS queue i.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- /* An identifier for the LED #3. */
- uint8_t led3_id;
- /* The type of LED #3. */
- uint8_t led3_type;
- /* Speed LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
- /* Activity LED */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
- /* Invalid */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
- HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
+ uint8_t mark_en;
+ uint8_t unused_0[4];
/*
- * An identifier for the group of LEDs that LED #3 belongs
- * to.
- * If set to 0, then the LED #0 cannot be grouped.
- * For all other non-zero values of this field, LED #0 is
- * grouped together with the LEDs with the same group ID
- * value.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t led3_group_id;
- uint8_t unused_3;
- /* The states supported by LED #3. */
- uint16_t led3_state_caps;
+ uint8_t valid;
+} __rte_packed;
+
+/* ECN mark statistics format */
+/* port_stats_ecn (size:512b/64B) */
+struct port_stats_ecn {
/*
- * If set to 1, this LED is enabled.
- * If set to 0, this LED is disabled.
+ * Number of packets marked in CoS queue 0.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
- UINT32_C(0x1)
+ uint64_t mark_cnt_cos0;
/*
- * If set to 1, off state is supported on this LED.
- * If set to 0, off state is not supported on this LED.
+ * Number of packets marked in CoS queue 1.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
- UINT32_C(0x2)
+ uint64_t mark_cnt_cos1;
/*
- * If set to 1, on state is supported on this LED.
- * If set to 0, on state is not supported on this LED.
+ * Number of packets marked in CoS queue 2.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
- UINT32_C(0x4)
+ uint64_t mark_cnt_cos2;
/*
- * If set to 1, blink state is supported on this LED.
- * If set to 0, blink state is not supported on this LED.
+ * Number of packets marked in CoS queue 3.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
- UINT32_C(0x8)
+ uint64_t mark_cnt_cos3;
/*
- * If set to 1, blink_alt state is supported on this LED.
- * If set to 0, blink_alt state is not supported on this LED.
+ * Number of packets marked in CoS queue 4.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
- UINT32_C(0x10)
- /* The colors supported by LED #3. */
- uint16_t led3_color_caps;
- /* reserved. */
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
- UINT32_C(0x1)
+ uint64_t mark_cnt_cos4;
/*
- * If set to 1, Amber color is supported on this LED.
- * If set to 0, Amber color is not supported on this LED.
+ * Number of packets marked in CoS queue 5.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
- UINT32_C(0x2)
+ uint64_t mark_cnt_cos5;
/*
- * If set to 1, Green color is supported on this LED.
- * If set to 0, Green color is not supported on this LED.
+ * Number of packets marked in CoS queue 6.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
- UINT32_C(0x4)
- uint8_t unused_4[3];
+ uint64_t mark_cnt_cos6;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * Number of packets marked in CoS queue 7.
+ * Or, if the driver requested counter masks, a mask to indicate the size
+ * of the counter.
*/
- uint8_t valid;
+ uint64_t mark_cnt_cos7;
} __rte_packed;
/***********************
- * hwrm_port_prbs_test *
+ * hwrm_port_clr_stats *
***********************/
-/* hwrm_port_prbs_test_input (size:384b/48B) */
-struct hwrm_port_prbs_test_input {
+/* hwrm_port_clr_stats_input (size:192b/24B) */
+struct hwrm_port_clr_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Host address data is to DMA'd to. */
- uint64_t resp_data_addr;
- /*
- * Size of the buffer pointed to by resp_data_addr. The firmware may
- * use this entire buffer or less than the entire buffer, but never more.
- */
- uint16_t data_len;
- uint16_t unused_0;
- uint32_t unused_1;
- /* Port ID of port where PRBS test to be run. */
+ /* Port ID of port that is being queried. */
uint16_t port_id;
- /* Polynomial selection for PRBS test. */
- uint16_t poly;
- /* PRBS7 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
- /* PRBS9 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
- /* PRBS11 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
- /* PRBS15 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
- /* PRBS23 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
- /* PRBS31 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
- /* PRBS58 */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
- /* Invalid */
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
- #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
- HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
- /*
- * Configuration bits for PRBS test.
- * Use enable bit to start/stop test.
- * Use tx/rx lane map bits to run test on specific lanes,
- * if set to 0 test will be run on all lanes.
- */
- uint16_t prbs_config;
- /*
- * Set 0 to stop test currently in progress
- * Set 1 to start test with configuration provided.
- */
- #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
- UINT32_C(0x1)
- /*
- * If set to 1, tx_lane_map bitmap should have lane bits set.
- * If set to 0, test will be run on all lanes for this port.
- */
- #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
- UINT32_C(0x2)
- /*
- * If set to 1, rx_lane_map bitmap should have lane bits set.
- * If set to 0, test will be run on all lanes for this port.
- */
- #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
- UINT32_C(0x4)
- /* Duration in seconds to run the PRBS test. */
- uint16_t timeout;
- /*
- * If tx_lane_map_valid is set to 1, this field is a bitmap
- * of tx lanes to run PRBS test. bit0 = lane0,
- * bit1 = lane1 ..bit31 = lane31
- */
- uint32_t tx_lane_map;
+ uint8_t flags;
/*
- * If rx_lane_map_valid is set to 1, this field is a bitmap
- * of rx lanes to run PRBS test. bit0 = lane0,
- * bit1 = lane1 ..bit31 = lane31
+ * If set to 1, then this field indicates clear the following RoCE
+ * specific counters.
+ * RoCE associated TX/RX cos counters
+ * CNP associated TX/RX cos counters
+ * RoCE/CNP specific TX/RX flow counters
+ * Firmware will determine the RoCE/CNP cos queue based on qos profile.
+ * This flag is honored only when RoCE is enabled on that port.
*/
- uint32_t rx_lane_map;
+ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
+ uint8_t unused_0[5];
} __rte_packed;
-/* hwrm_port_prbs_test_output (size:128b/16B) */
-struct hwrm_port_prbs_test_output {
+/* hwrm_port_clr_stats_output (size:128b/16B) */
+struct hwrm_port_clr_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Total length of stored data. */
- uint16_t total_data_len;
- uint16_t unused_0;
- uint8_t unused_1[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_port_dsc_dump *
- **********************/
+/***********************
+ * hwrm_port_phy_qcaps *
+ ***********************/
-/* hwrm_port_dsc_dump_input (size:320b/40B) */
-struct hwrm_port_dsc_dump_input {
+/* hwrm_port_phy_qcaps_input (size:192b/24B) */
+struct hwrm_port_phy_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Host address where response diagnostic data is returned. */
- uint64_t resp_data_addr;
- /*
- * Size of the buffer pointed to by resp_data_addr. The firmware
- * may use this entire buffer or less than the entire buffer, but
- * never more.
- */
- uint16_t data_len;
- uint16_t unused_0;
- uint32_t unused_1;
- /* Port ID of port where dsc dump to be collected. */
+ /* Port ID of port that is being queried. */
uint16_t port_id;
- /* Diag level specified by the user */
- uint16_t diag_level;
- /* SRDS_DIAG_LANE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
- UINT32_C(0x0)
- /* SRDS_DIAG_CORE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
- UINT32_C(0x1)
- /* SRDS_DIAG_EVENT */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
- UINT32_C(0x2)
- /* SRDS_DIAG_EYE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
- UINT32_C(0x3)
- /* SRDS_DIAG_REG_CORE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
- UINT32_C(0x4)
- /* SRDS_DIAG_REG_LANE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
- UINT32_C(0x5)
- /* SRDS_DIAG_UC_CORE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
- UINT32_C(0x6)
- /* SRDS_DIAG_UC_LANE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
- UINT32_C(0x7)
- /* SRDS_DIAG_LANE_DEBUG */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
- UINT32_C(0x8)
- /* SRDS_DIAG_BER_VERT */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
- UINT32_C(0x9)
- /* SRDS_DIAG_BER_HORZ */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
- UINT32_C(0xa)
- /* SRDS_DIAG_EVENT_SAFE */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
- UINT32_C(0xb)
- /* SRDS_DIAG_TIMESTAMP */
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
- UINT32_C(0xc)
- #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
- HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
- /*
- * This field is a lane number
- * on which to collect the dsc dump
- */
- uint16_t lane_number;
- /*
- * Configuration bits.
- * Use enable bit to start dsc dump or retrieve dump
- */
- uint16_t dsc_dump_config;
- /*
- * Set 0 to retrieve the dsc dump
- * Set 1 to start the dsc dump
- */
- #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
- UINT32_C(0x1)
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_dsc_dump_output (size:128b/16B) */
-struct hwrm_port_dsc_dump_output {
+/* hwrm_port_phy_qcaps_output (size:256b/32B) */
+struct hwrm_port_phy_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Total length of stored data. */
- uint16_t total_data_len;
- uint16_t unused_0;
- uint8_t unused_1[3];
+ /* PHY capability flags */
+ uint8_t flags;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * If set to 1, then this field indicates that the
+ * link is capable of supporting EEE.
*/
- uint8_t valid;
-} __rte_packed;
-
-/******************************
- * hwrm_port_sfp_sideband_cfg *
- ******************************/
-
-
-/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
-struct hwrm_port_sfp_sideband_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
+ UINT32_C(0x1)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If set to 1, then this field indicates that the
+ * PHY is capable of supporting external loopback.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
+ UINT32_C(0x2)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * If set to 1, then this field indicates that the
+ * PHY is capable of supporting loopback in autoneg mode.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
+ UINT32_C(0x4)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Indicates if the configuration of shared PHY settings is supported.
+ * In cases where a physical port is shared by multiple functions
+ * (e.g. NPAR, multihost, etc), the configuration of PHY
+ * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
+ * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
*/
- uint16_t target_id;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
+ UINT32_C(0x8)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If set to 1, it indicates that the port counters and extended
+ * port counters will not reset when the firmware shuts down or
+ * resets the PHY. These counters will only be reset during power
+ * cycle or by calling HWRM_PORT_CLR_STATS.
+ * If set to 0, the state of the counters is unspecified when
+ * firmware shuts down or resets the PHY.
*/
- uint64_t resp_addr;
- /* Port ID of port that is to be queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
+ UINT32_C(0x10)
/*
- * This bitfield is used to specify which bits from the 'flags'
- * fields are being configured by the caller.
+ * If set to 1, then this field indicates that the
+ * local loopback is not supported on this controller.
*/
- uint32_t enables;
- /* This bit must be '1' for rs0 to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
+ UINT32_C(0x20)
+ /*
+ * If set to 1, then this field indicates that the
+ * PHY/Link down policy during PF shutdown is totally
+ * controlled by the firmware. It can shutdown the link
+ * even when there are active VFs associated with the PF.
+ * Host PF driver can send HWRM_PHY_CFG command to bring
+ * down the PHY even when the port is shared between VFs
+ * and PFs.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
+ UINT32_C(0x40)
+ /*
+ * If set to 1, this field indicates that the FCS may
+ * be disabled for a given packet via the transmit
+ * buffer descriptor.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
+ UINT32_C(0x80)
+ /* Number of front panel ports for this device. */
+ uint8_t port_cnt;
+ /* Not supported or unknown */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
+ /* single port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
+ /* 2-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
+ /* 3-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
+ /* 4-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
+ /* 12-port device */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
+ HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12
+ /*
+ * This is a bit mask to indicate what speeds are supported
+ * as forced speeds on this link.
+ * For each speed that can be forced on this link, the
+ * corresponding mask bit shall be set to '1'.
+ */
+ uint16_t supported_speeds_force_mode;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
UINT32_C(0x1)
- /* This bit must be '1' for rs1 to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
UINT32_C(0x2)
- /* This bit must be '1' for tx_disable to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
UINT32_C(0x4)
- /*
- * This bit must be '1' for mod_sel to be configured.
- * Valid only on QSFP modules
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
UINT32_C(0x8)
- /* This bit must be '1' for reset_l to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
UINT32_C(0x10)
- /* This bit must be '1' for lp_mode to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
UINT32_C(0x20)
- /* This bit must be '1' for pwr_disable to be configured. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
+ UINT32_C(0x2000)
/*
- * Only bits that have corresponding bits in the 'enables'
- * bitfield are processed by the firmware, all other bits
- * of 'flags' are ignored.
- */
- uint32_t flags;
- /*
- * This bit along with rs1 configures the current speed of the dual
- * rate module. If these pins are GNDed then the speed can be changed
- * by driectly writing to EEPROM.
+ * This is a bit mask to indicate what speeds are supported
+ * for autonegotiation on this link.
+ * For each speed that can be autonegotiated on this link, the
+ * corresponding mask bit shall be set to '1'.
*/
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
+ uint16_t supported_speeds_auto_mode;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
UINT32_C(0x1)
- /*
- * This bit along with rs0 configures the current speed of the dual
- * rate module. If these pins are GNDed then the speed can be changed
- * by driectly writing to EEPROM.
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
UINT32_C(0x2)
- /*
- * When this bit is set to '1', tx_disable is set.
- * On a 1G BASE-T module, if this bit is set,
- * module PHY registers will not be accessible.
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
UINT32_C(0x4)
- /*
- * When this bit is set to '1', this module is selected.
- * Valid only on QSFP modules
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
UINT32_C(0x8)
- /*
- * If reset_l is set to 0, Module will be taken out of reset
- * and other signals will be set to their requested state once
- * the module is out of reset.
- * Valid only on QSFP modules
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
UINT32_C(0x10)
- /*
- * When this bit is set to '1', the module will be configured
- * in low power mode.
- * Valid only on QSFP modules
- */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
UINT32_C(0x20)
- /* When this bit is set to '1', the module will be powered down. */
- #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
UINT32_C(0x40)
-} __rte_packed;
-
-/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
-struct hwrm_port_sfp_sideband_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused[7];
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
+ UINT32_C(0x2000)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written. When
- * writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This is a bit mask to indicate what speeds are supported
+ * for EEE on this link.
+ * For each speed that can be autonegotiated when EEE is enabled
+ * on this link, the corresponding mask bit shall be set to '1'.
+ * This field is only valid when the eee_supported is set to '1'.
*/
- uint8_t valid;
-} __rte_packed;
-
-/*******************************
- * hwrm_port_sfp_sideband_qcfg *
- *******************************/
-
-
-/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
-struct hwrm_port_sfp_sideband_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint16_t supported_speeds_eee_mode;
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
+ UINT32_C(0x40)
+ uint32_t tx_lpi_timer_low;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * The lowest value of TX LPI timer that can be set on this link
+ * when EEE is enabled. This value is in microseconds.
+ * This field is valid only when_eee_supported is set to '1'.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Reserved field. The HWRM shall set this field to 0.
+ * An HWRM client shall ignore this field.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
+ uint32_t valid_tx_lpi_timer_high;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * The highest value of TX LPI timer that can be set on this link
+ * when EEE is enabled. This value is in microseconds.
+ * This field is valid only when_eee_supported is set to '1'.
*/
- uint16_t target_id;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Reserved field. The HWRM shall set this field to 0.
+ * An HWRM client shall ignore this field.
*/
- uint64_t resp_addr;
- /* Port ID of port that is to be queried. */
- uint16_t port_id;
- uint8_t unused_0[6];
-} __rte_packed;
-
-/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
-struct hwrm_port_sfp_sideband_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
/*
- * Bitmask indicating which sideband signals are valid.
- * This is based on the board and nvm cfg that is present on the board.
+ * This field is used to advertise which PAM4 speeds are supported
+ * in auto mode.
*/
- uint32_t supported_mask;
- uint32_t sideband_signals;
- /* When this bit is set to '1', the Module is absent. */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
+ uint16_t supported_pam4_speeds_auto_mode;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
UINT32_C(0x1)
- /*
- * When this bit is set to '1', there is no valid signal on RX.
- * This signal is a filtered version of Signal Detect.
- */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
UINT32_C(0x2)
- /*
- * This bit along with rs1 indiactes the current speed of the dual
- * rate module.If these pins are grounded then the speed can be
- * changed by driectky writing to EEPROM.
- */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
UINT32_C(0x4)
/*
- * This bit along with rs0 indiactes the current speed of the dual
- * rate module.If these pins are grounded then the speed can be
- * changed by driectky writing to EEPROM.
- */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
- UINT32_C(0x8)
- /*
- * When this bit is set to '1', tx_disable is set.
- * On a 1G BASE-T module, if this bit is set, module PHY
- * registers will not be accessible.
+ * This field is used to advertise which PAM4 speeds are supported
+ * in forced mode.
*/
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
- UINT32_C(0x10)
- /* When this bit is set to '1', tx_fault is set. */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
- UINT32_C(0x20)
+ uint16_t supported_pam4_speeds_force_mode;
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
+ UINT32_C(0x1)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
+ UINT32_C(0x2)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
+ UINT32_C(0x4)
+ /* More PHY capability flags */
+ uint16_t flags2;
/*
- * When this bit is set to '1', module is selected.
- * Valid only on QSFP modules
+ * If set to 1, then this field indicates that
+ * 802.3x flow control is not supported.
*/
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
- UINT32_C(0x40)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \
+ UINT32_C(0x1)
/*
- * When this bit is set to '0', the module is held in reset.
- * if reset_l is set to 1,first module is taken out of reset
- * and other signals will be set to their requested state.
- * Valid only on QSFP modules.
+ * If set to 1, then this field indicates that
+ * priority-based flow control is not supported.
*/
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
- UINT32_C(0x80)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \
+ UINT32_C(0x2)
/*
- * When this bit is set to '1', the module is in low power mode.
- * Valid only on QSFP modules
+ * Number of internal ports for this device. This field allows the FW
+ * to advertise how many internal ports are present. Manufacturing
+ * tools uses this to determine how many internal ports should have
+ * the PRBS test run on them. This field always return 0 unless NVM
+ * option "HPTN_MODE" is set to 1.
*/
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
- UINT32_C(0x100)
- /* When this bit is set to '1', module is in power down state. */
- #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
- UINT32_C(0x200)
- uint8_t unused[7];
+ uint8_t internal_port_cnt;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written. When
- * writing a command completion or response to an internal processor,
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
} __rte_packed;
-/**********************************
- * hwrm_port_phy_mdio_bus_acquire *
- **********************************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
-struct hwrm_port_phy_mdio_bus_acquire_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of the port. */
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
/*
- * client_id of the client requesting BUS access.
- * Any value from 0x10 to 0xFFFF can be used.
- * Client should make sure that the returned client_id
- * in response matches the client_id in request.
- * 0-0xF are reserved for internal use.
- */
- uint16_t client_id;
- /*
- * Timeout in milli seconds, MDIO BUS will be released automatically
- * after this time, if another mdio acquire command is not received
- * within the timeout window from the same client.
- * A 0xFFFF will hold the bus until this bus is released.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- uint16_t mdio_bus_timeout;
- uint8_t unused_0[2];
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
} __rte_packed;
-/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
-struct hwrm_port_phy_mdio_bus_acquire_output {
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint16_t unused_0;
- /*
- * client_id of the module holding the BUS.
- * 0-0xF are reserved for internal use.
- */
- uint16_t client_id;
- uint8_t unused_1[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/**********************************
- * hwrm_port_phy_mdio_bus_release *
- **********************************/
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
-/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
-struct hwrm_port_phy_mdio_bus_release_input {
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Port ID of the port. */
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * client_id of the client requesting BUS release.
- * A client should not release any other clients BUS.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- uint16_t client_id;
- uint8_t unused_0[4];
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
} __rte_packed;
-/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
-struct hwrm_port_phy_mdio_bus_release_output {
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint16_t unused_0;
- /* The BUS is released if client_id matches the client_id in request. */
- uint16_t clients_id;
- uint8_t unused_1[3];
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_queue_qportcfg *
- ***********************/
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
-/* hwrm_queue_qportcfg_input (size:192b/24B) */
-struct hwrm_queue_qportcfg_input {
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
+ uint32_t enables;
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * This bit must be '1' for the led0_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
/*
- * Port ID of port for which the queue configuration is being
- * queried. This field is only required when sent by IPC.
+ * This bit must be '1' for the led0_state field to be
+ * configured.
*/
- uint16_t port_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
/*
- * Drivers will set this capability when it can use
- * queue_idx_service_profile to map the queues to application.
+ * This bit must be '1' for the led0_color field to be
+ * configured.
*/
- uint8_t drv_qmap_cap;
- /* disabled */
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
- /* enabled */
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
- #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
- HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
- uint8_t unused_0;
-} __rte_packed;
-
-/* hwrm_queue_qportcfg_output (size:256b/32B) */
-struct hwrm_queue_qportcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
/*
- * The maximum number of queues that can be configured on this
- * port.
- * Valid values range from 1 through 8.
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
*/
- uint8_t max_configurable_queues;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
/*
- * The maximum number of lossless queues that can be configured
- * on this port.
- * Valid values range from 0 through 8.
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
*/
- uint8_t max_configurable_lossless_queues;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_cfg command shall return error when trying to
- * configure a queue not configurable.
- */
- uint8_t queue_cfg_allowed;
- /* Information about queue configuration. */
- uint8_t queue_cfg_info;
- /*
- * If this flag is set to '1', then the queues are
- * configured asymmetrically on TX and RX sides.
- * If this flag is set to '0', then the queues are
- * configured symmetrically on TX and RX sides. For
- * symmetric configuration, the queue configuration
- * including queue ids and service profiles on the
- * TX side is the same as the corresponding queue
- * configuration on the RX side.
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
- UINT32_C(0x1)
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pfcenable_cfg command.
- *
- * Each bit represents a specific priority where bit 0 represents
- * priority 0 and bit 7 represents priority 7.
- * # A value of 0 indicates that the priority is not configurable by
- * the hwrm_queue_pfcenable_cfg command.
- * # A value of 1 indicates that the priority is configurable.
- * # A hwrm_queue_pfcenable_cfg command shall return error when
- * trying to configure a priority that is not configurable.
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
- uint8_t queue_pfcenable_cfg_allowed;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
+ UINT32_C(0x40)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pri2cos_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_pri2cos_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_pri2cos_cfg command shall return error when
- * trying to configure a queue that is not configurable.
+ * This bit must be '1' for the led1_state field to be
+ * configured.
*/
- uint8_t queue_pri2cos_cfg_allowed;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
+ UINT32_C(0x80)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_pri2cos_cfg command.
- *
- * Each bit represents a specific queue where bit 0 represents
- * queue 0 and bit 7 represents queue 7.
- * # A value of 0 indicates that the queue is not configurable
- * by the hwrm_queue_pri2cos_cfg command.
- * # A value of 1 indicates that the queue is configurable.
- * # A hwrm_queue_pri2cos_cfg command shall return error when
- * trying to configure a queue not configurable.
+ * This bit must be '1' for the led1_color field to be
+ * configured.
*/
- uint8_t queue_cos2bw_cfg_allowed;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
+ UINT32_C(0x100)
/*
- * ID of CoS Queue 0.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led1_blink_on field to be
+ * configured.
*/
- uint8_t queue_id0;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id0_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
+ UINT32_C(0x200)
/*
- * ID of CoS Queue 1.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led1_blink_off field to be
+ * configured.
*/
- uint8_t queue_id1;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id1_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
+ UINT32_C(0x400)
/*
- * ID of CoS Queue 2.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led1_group_id field to be
+ * configured.
*/
- uint8_t queue_id2;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id2_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
+ UINT32_C(0x800)
/*
- * ID of CoS Queue 3.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led2_id field to be
+ * configured.
*/
- uint8_t queue_id3;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id3_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
+ UINT32_C(0x1000)
/*
- * ID of CoS Queue 4.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led2_state field to be
+ * configured.
*/
- uint8_t queue_id4;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id4_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
+ UINT32_C(0x2000)
/*
- * ID of CoS Queue 5.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led2_color field to be
+ * configured.
*/
- uint8_t queue_id5;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id5_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
+ UINT32_C(0x4000)
/*
- * ID of CoS Queue 6.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led2_blink_on field to be
+ * configured.
*/
- uint8_t queue_id6;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id6_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
+ UINT32_C(0x8000)
/*
- * ID of CoS Queue 7.
- * FF - Invalid id
- *
- * # This ID can be used on any subsequent call to an hwrm command
- * that takes a queue id.
- * # IDs must always be queried by this command before any use
- * by the driver or software.
- * # Any driver or software should not make any assumptions about
- * queue IDs.
- * # A value of 0xff indicates that the queue is not available.
- * # Available queues may not be in sequential order.
+ * This bit must be '1' for the led2_blink_off field to be
+ * configured.
*/
- uint8_t queue_id7;
- /* This value is applicable to CoS queues only. */
- uint8_t queue_id7_service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
- UINT32_C(0x0)
- /* Lossless (legacy) */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
- UINT32_C(0x1)
- /* Lossless RoCE */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
- UINT32_C(0x1)
- /* Lossy RoCE CNP */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
- UINT32_C(0x2)
- /* Lossless NIC */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
- UINT32_C(0x3)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
- UINT32_C(0xff)
- #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
+ UINT32_C(0x10000)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * This bit must be '1' for the led2_group_id field to be
+ * configured.
*/
- uint8_t valid;
-} __rte_packed;
-
-/*******************
- * hwrm_queue_qcfg *
- *******************/
-
-
-/* hwrm_queue_qcfg_input (size:192b/24B) */
-struct hwrm_queue_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
+ UINT32_C(0x20000)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This bit must be '1' for the led3_id field to be
+ * configured.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
+ UINT32_C(0x40000)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * This bit must be '1' for the led3_state field to be
+ * configured.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
+ UINT32_C(0x80000)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * This bit must be '1' for the led3_color field to be
+ * configured.
*/
- uint16_t target_id;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
+ UINT32_C(0x100000)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This bit must be '1' for the led3_blink_on field to be
+ * configured.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
+ UINT32_C(0x200000)
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * This bit must be '1' for the led3_blink_off field to be
+ * configured.
*/
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
- /* Queue ID of the queue. */
- uint32_t queue_id;
-} __rte_packed;
-
-/* hwrm_queue_qcfg_output (size:128b/16B) */
-struct hwrm_queue_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
+ UINT32_C(0x400000)
/*
- * This value is the estimate packet length used in the
- * TX arbiter.
+ * This bit must be '1' for the led3_group_id field to be
+ * configured.
*/
- uint32_t queue_len;
- /* This value is applicable to CoS queues only. */
- uint8_t service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
- /* Lossless */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
- #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
- /* Information about queue configuration. */
- uint8_t queue_cfg_info;
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
+ UINT32_C(0x800000)
+ /* Port ID of port whose LEDs are configured. */
+ uint16_t port_id;
/*
- * If this flag is set to '1', then the queue is
- * configured asymmetrically on TX and RX sides.
- * If this flag is set to '0', then this queue is
- * configured symmetrically on TX and RX sides.
+ * The number of LEDs that are being configured.
+ * Up to 4 LEDs can be configured with this command.
*/
- #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
- UINT32_C(0x1)
+ uint8_t num_leds;
+ /* Reserved field. */
+ uint8_t rsvd;
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The requested state of the LED #0. */
+ uint8_t led0_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
+ /* The requested color of LED #0. */
+ uint8_t led0_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
uint8_t unused_0;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/******************
- * hwrm_queue_cfg *
- ******************/
-
-
-/* hwrm_queue_cfg_input (size:320b/40B) */
-struct hwrm_queue_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint16_t cmpl_ring;
+ uint16_t led0_blink_on;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint16_t seq_id;
+ uint16_t led0_blink_off;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #0 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t flags;
- /*
- * Enumeration denoting the RX, TX, or both directions applicable to the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
- /* tx path */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- /* Bi-directional (Symmetrically applicable to TX and RX paths) */
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
- #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
- uint32_t enables;
+ uint8_t led0_group_id;
+ /* Reserved field. */
+ uint8_t rsvd0;
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The requested state of the LED #1. */
+ uint8_t led1_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
+ /* The requested color of LED #1. */
+ uint8_t led1_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
+ uint8_t unused_1;
/*
- * This bit must be '1' for the dflt_len field to be
- * configured.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
+ uint16_t led1_blink_on;
/*
- * This bit must be '1' for the service_profile field to be
- * configured.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
- /* Queue ID of queue that is to be configured by this function. */
- uint32_t queue_id;
+ uint16_t led1_blink_off;
/*
- * This value is a the estimate packet length used in the
- * TX arbiter.
- * Set to 0xFF... (All Fs) to not adjust this value.
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #1 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #1 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint32_t dflt_len;
- /* This value is applicable to CoS queues only. */
- uint8_t service_profile;
- /* Lossy (best-effort) */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
- /* Lossless */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
- /* Set to 0xFF... (All Fs) if there is no service profile specified */
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
- #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
- HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
- uint8_t unused_0[7];
-} __rte_packed;
-
-/* hwrm_queue_cfg_output (size:128b/16B) */
-struct hwrm_queue_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t led1_group_id;
+ /* Reserved field. */
+ uint8_t rsvd1;
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The requested state of the LED #2. */
+ uint8_t led2_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
+ /* The requested color of LED #2. */
+ uint8_t led2_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
+ uint8_t unused_2;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t valid;
-} __rte_packed;
-
-/*****************************
- * hwrm_queue_pfcenable_qcfg *
- *****************************/
-
-
-/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
-struct hwrm_queue_pfcenable_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint16_t led2_blink_on;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint16_t cmpl_ring;
+ uint16_t led2_blink_off;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * An identifier for the group of LEDs that LED #2 belongs
+ * to.
+ * If set to 0, then the LED #2 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #2 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t seq_id;
+ uint8_t led2_group_id;
+ /* Reserved field. */
+ uint8_t rsvd2;
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The requested state of the LED #3. */
+ uint8_t led3_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
+ /* The requested color of LED #3. */
+ uint8_t led3_color;
+ /* Default */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
+ HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
+ uint8_t unused_3;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint16_t target_id;
+ uint16_t led3_blink_on;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint64_t resp_addr;
+ uint16_t led3_blink_off;
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #3 shall not be grouped and
+ * shall be treated as an individual resource.
+ * For all other non-zero values of this field, LED #3 shall
+ * be grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t port_id;
- uint8_t unused_0[6];
+ uint8_t led3_group_id;
+ /* Reserved field. */
+ uint8_t rsvd3;
} __rte_packed;
-/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
-struct hwrm_queue_pfcenable_qcfg_output {
+/* hwrm_port_led_cfg_output (size:128b/16B) */
+struct hwrm_port_led_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t flags;
- /* If set to 1, then PFC is enabled on PRI 0. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
- UINT32_C(0x1)
- /* If set to 1, then PFC is enabled on PRI 1. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
- UINT32_C(0x2)
- /* If set to 1, then PFC is enabled on PRI 2. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
- UINT32_C(0x4)
- /* If set to 1, then PFC is enabled on PRI 3. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
- UINT32_C(0x8)
- /* If set to 1, then PFC is enabled on PRI 4. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
- UINT32_C(0x10)
- /* If set to 1, then PFC is enabled on PRI 5. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
- UINT32_C(0x20)
- /* If set to 1, then PFC is enabled on PRI 6. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
- UINT32_C(0x40)
- /* If set to 1, then PFC is enabled on PRI 7. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
- UINT32_C(0x80)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x100)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x200)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x400)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x800)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x1000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x2000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x4000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
- #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x8000)
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/****************************
- * hwrm_queue_pfcenable_cfg *
- ****************************/
+/**********************
+ * hwrm_port_led_qcfg *
+ **********************/
-/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
-struct hwrm_queue_pfcenable_cfg_input {
+/* hwrm_port_led_qcfg_input (size:192b/24B) */
+struct hwrm_port_led_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If set to 1, then PFC is requested to be enabled on PRI 0. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
- UINT32_C(0x1)
- /* If set to 1, then PFC is requested to be enabled on PRI 1. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
- UINT32_C(0x2)
- /* If set to 1, then PFC is requested to be enabled on PRI 2. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
- UINT32_C(0x4)
- /* If set to 1, then PFC is requested to be enabled on PRI 3. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
- UINT32_C(0x8)
- /* If set to 1, then PFC is requested to be enabled on PRI 4. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
- UINT32_C(0x10)
- /* If set to 1, then PFC is requested to be enabled on PRI 5. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
- UINT32_C(0x20)
- /* If set to 1, then PFC is requested to be enabled on PRI 6. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
- UINT32_C(0x40)
- /* If set to 1, then PFC is requested to be enabled on PRI 7. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
- UINT32_C(0x80)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x100)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x200)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x400)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x800)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x1000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x2000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x4000)
- /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
- #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
- UINT32_C(0x8000)
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
+ /* Port ID of port whose LED configuration is being queried. */
uint16_t port_id;
- uint8_t unused_0[2];
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
-struct hwrm_queue_pfcenable_cfg_output {
+/* hwrm_port_led_qcfg_output (size:448b/56B) */
+struct hwrm_port_led_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * The number of LEDs that are configured on this port.
+ * Up to 4 LEDs can be returned in the response.
*/
- uint8_t valid;
-} __rte_packed;
-
-/***************************
- * hwrm_queue_pri2cos_qcfg *
- ***************************/
-
-
-/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
-struct hwrm_queue_pri2cos_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ uint8_t num_leds;
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The type of LED #0. */
+ uint8_t led0_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
+ /* The current state of the LED #0. */
+ uint8_t led0_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
+ /* The color of LED #0. */
+ uint8_t led0_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
+ uint8_t unused_0;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint16_t cmpl_ring;
+ uint16_t led0_blink_on;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * If the LED #0 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint16_t seq_id;
+ uint16_t led0_blink_off;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 is not grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint16_t target_id;
+ uint8_t led0_group_id;
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The type of LED #1. */
+ uint8_t led1_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
+ /* The current state of the LED #1. */
+ uint8_t led1_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
+ /* The color of LED #1. */
+ uint8_t led1_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
+ uint8_t unused_1;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint64_t resp_addr;
- uint32_t flags;
+ uint16_t led1_blink_on;
/*
- * Enumeration denoting the RX, TX type of the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
- */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
- /*
- * When this bit is set to '0', the query is
- * for PRI from tunnel headers.
- * When this bit is set to '1', the query is
- * for PRI from inner packet headers.
- */
- #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- uint8_t unused_0[3];
-} __rte_packed;
-
-/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
-struct hwrm_queue_pri2cos_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /*
- * CoS Queue assigned to priority 0. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
- */
- uint8_t pri0_cos_queue_id;
- /*
- * CoS Queue assigned to priority 1. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * If the LED #1 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t pri1_cos_queue_id;
+ uint16_t led1_blink_off;
/*
- * CoS Queue assigned to priority 2. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #1 is not grouped.
+ * For all other non-zero values of this field, LED #1 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t pri2_cos_queue_id;
+ uint8_t led1_group_id;
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The type of LED #2. */
+ uint8_t led2_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
+ /* The current state of the LED #2. */
+ uint8_t led2_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
+ /* The color of LED #2. */
+ uint8_t led2_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
+ uint8_t unused_2;
/*
- * CoS Queue assigned to priority 3. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t pri3_cos_queue_id;
+ uint16_t led2_blink_on;
/*
- * CoS Queue assigned to priority 4. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * If the LED #2 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t pri4_cos_queue_id;
+ uint16_t led2_blink_off;
/*
- * CoS Queue assigned to priority 5. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * An identifier for the group of LEDs that LED #2 belongs
+ * to.
+ * If set to 0, then the LED #2 is not grouped.
+ * For all other non-zero values of this field, LED #2 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t pri5_cos_queue_id;
+ uint8_t led2_group_id;
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The type of LED #3. */
+ uint8_t led3_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
+ /* The current state of the LED #3. */
+ uint8_t led3_state;
+ /* Default state of the LED */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
+ /* Off */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
+ /* On */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
+ /* Blink */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
+ /* Blink Alternately */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
+ /* The color of LED #3. */
+ uint8_t led3_color;
+ /* Default */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
+ /* Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
+ /* Green */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
+ /* Green or Amber */
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
+ #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
+ HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
+ uint8_t unused_3;
/*
- * CoS Queue assigned to priority 6. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED on between cycles.
*/
- uint8_t pri6_cos_queue_id;
+ uint16_t led3_blink_on;
/*
- * CoS Queue assigned to priority 7. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no CoS queue is assigned to the
- * specified priority.
+ * If the LED #3 state is "blink" or "blinkalt", then
+ * this field represents the requested time in milliseconds
+ * to keep LED off between cycles.
*/
- uint8_t pri7_cos_queue_id;
- /* Information about queue configuration. */
- uint8_t queue_cfg_info;
+ uint16_t led3_blink_off;
/*
- * If this flag is set to '1', then the PRI to CoS
- * configuration is asymmetric on TX and RX sides.
- * If this flag is set to '0', then PRI to CoS configuration
- * is symmetric on TX and RX sides.
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #3 is not grouped.
+ * For all other non-zero values of this field, LED #3 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
- UINT32_C(0x1)
- uint8_t unused_0[6];
+ uint8_t led3_group_id;
+ uint8_t unused_4[6];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/**************************
- * hwrm_queue_pri2cos_cfg *
- **************************/
+/***********************
+ * hwrm_port_led_qcaps *
+ ***********************/
-/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
-struct hwrm_queue_pri2cos_cfg_input {
+/* hwrm_port_led_qcaps_input (size:192b/24B) */
+struct hwrm_port_led_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
+ /* Port ID of port whose LED configuration is being queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_port_led_qcaps_output (size:384b/48B) */
+struct hwrm_port_led_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * Enumeration denoting the RX, TX, or both directions applicable to the resource.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * The number of LEDs that are configured on this port.
+ * Up to 4 LEDs can be returned in the response.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
- /* tx path */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- /* Bi-directional (Symmetrically applicable to TX and RX paths) */
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
+ uint8_t num_leds;
+ /* Reserved for future use. */
+ uint8_t unused[3];
+ /* An identifier for the LED #0. */
+ uint8_t led0_id;
+ /* The type of LED #0. */
+ uint8_t led0_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
/*
- * When this bit is set to '0', the mapping is requested
- * for PRI from tunnel headers.
- * When this bit is set to '1', the mapping is requested
- * for PRI from inner packet headers.
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
- uint32_t enables;
+ uint8_t led0_group_id;
+ uint8_t unused_0;
+ /* The states supported by LED #0. */
+ uint16_t led0_state_caps;
/*
- * This bit must be '1' for the pri0_cos_queue_id field to be
- * configured.
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
UINT32_C(0x1)
/*
- * This bit must be '1' for the pri1_cos_queue_id field to be
- * configured.
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
UINT32_C(0x2)
/*
- * This bit must be '1' for the pri2_cos_queue_id field to be
- * configured.
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
UINT32_C(0x4)
/*
- * This bit must be '1' for the pri3_cos_queue_id field to be
- * configured.
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
UINT32_C(0x8)
/*
- * This bit must be '1' for the pri4_cos_queue_id field to be
- * configured.
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
UINT32_C(0x10)
+ /* The colors supported by LED #0. */
+ uint16_t led0_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
/*
- * This bit must be '1' for the pri5_cos_queue_id field to be
- * configured.
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
- UINT32_C(0x20)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
/*
- * This bit must be '1' for the pri6_cos_queue_id field to be
- * configured.
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
- UINT32_C(0x40)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #1. */
+ uint8_t led1_id;
+ /* The type of LED #1. */
+ uint8_t led1_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
/*
- * This bit must be '1' for the pri7_cos_queue_id field to be
- * configured.
+ * An identifier for the group of LEDs that LED #1 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
- UINT32_C(0x80)
+ uint8_t led1_group_id;
+ uint8_t unused_1;
+ /* The states supported by LED #1. */
+ uint16_t led1_state_caps;
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
*/
- uint8_t port_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
/*
- * CoS Queue assigned to priority 0. This value can only
- * be changed before traffic has started.
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
*/
- uint8_t pri0_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
/*
- * CoS Queue assigned to priority 1. This value can only
- * be changed before traffic has started.
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
*/
- uint8_t pri1_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
/*
- * CoS Queue assigned to priority 2 This value can only
- * be changed before traffic has started.
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
*/
- uint8_t pri2_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
/*
- * CoS Queue assigned to priority 3. This value can only
- * be changed before traffic has started.
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
*/
- uint8_t pri3_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #1. */
+ uint16_t led1_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
/*
- * CoS Queue assigned to priority 4. This value can only
- * be changed before traffic has started.
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
*/
- uint8_t pri4_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
/*
- * CoS Queue assigned to priority 5. This value can only
- * be changed before traffic has started.
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
*/
- uint8_t pri5_cos_queue_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #2. */
+ uint8_t led2_id;
+ /* The type of LED #2. */
+ uint8_t led2_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
/*
- * CoS Queue assigned to priority 6. This value can only
- * be changed before traffic has started.
+ * An identifier for the group of LEDs that LED #0 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint8_t pri6_cos_queue_id;
+ uint8_t led2_group_id;
+ uint8_t unused_2;
+ /* The states supported by LED #2. */
+ uint16_t led2_state_caps;
/*
- * CoS Queue assigned to priority 7. This value can only
- * be changed before traffic has started.
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
*/
- uint8_t pri7_cos_queue_id;
- uint8_t unused_0[7];
-} __rte_packed;
-
-/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
-struct hwrm_queue_pri2cos_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
+ UINT32_C(0x1)
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
*/
- uint8_t valid;
-} __rte_packed;
-
-/**************************
- * hwrm_queue_cos2bw_qcfg *
- **************************/
-
-
-/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
-struct hwrm_queue_cos2bw_qcfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
*/
- uint16_t cmpl_ring;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
*/
- uint16_t seq_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
*/
- uint16_t target_id;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #2. */
+ uint16_t led2_color_caps;
+ /* reserved. */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
*/
- uint64_t resp_addr;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure TC BW assignment on this port.
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
*/
- uint16_t port_id;
- uint8_t unused_0[6];
-} __rte_packed;
-
-/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
-struct hwrm_queue_cos2bw_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* ID of CoS Queue 0. */
- uint8_t queue_id0;
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ /* An identifier for the LED #3. */
+ uint8_t led3_id;
+ /* The type of LED #3. */
+ uint8_t led3_type;
+ /* Speed LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
+ /* Activity LED */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
+ /* Invalid */
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
+ HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * An identifier for the group of LEDs that LED #3 belongs
+ * to.
+ * If set to 0, then the LED #0 cannot be grouped.
+ * For all other non-zero values of this field, LED #0 is
+ * grouped together with the LEDs with the same group ID
+ * value.
*/
- uint32_t queue_id0_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t led3_group_id;
+ uint8_t unused_3;
+ /* The states supported by LED #3. */
+ uint16_t led3_state_caps;
/*
- * Maximum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * If set to 1, this LED is enabled.
+ * If set to 0, this LED is disabled.
*/
- uint32_t queue_id0_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id0_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * If set to 1, off state is supported on this LED.
+ * If set to 0, off state is not supported on this LED.
*/
- uint8_t queue_id0_pri_lvl;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
+ UINT32_C(0x2)
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * If set to 1, on state is supported on this LED.
+ * If set to 0, on state is not supported on this LED.
*/
- uint8_t queue_id0_bw_weight;
- /* ID of CoS Queue 1. */
- uint8_t queue_id1;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
+ UINT32_C(0x4)
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * If set to 1, blink state is supported on this LED.
+ * If set to 0, blink state is not supported on this LED.
*/
- uint32_t queue_id1_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
+ UINT32_C(0x8)
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * If set to 1, blink_alt state is supported on this LED.
+ * If set to 0, blink_alt state is not supported on this LED.
*/
- uint32_t queue_id1_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id1_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
+ UINT32_C(0x10)
+ /* The colors supported by LED #3. */
+ uint16_t led3_color_caps;
/* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
+ UINT32_C(0x1)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * If set to 1, Amber color is supported on this LED.
+ * If set to 0, Amber color is not supported on this LED.
*/
- uint8_t queue_id1_pri_lvl;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
+ UINT32_C(0x2)
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * If set to 1, Green color is supported on this LED.
+ * If set to 0, Green color is not supported on this LED.
*/
- uint8_t queue_id1_bw_weight;
- /* ID of CoS Queue 2. */
- uint8_t queue_id2;
+ #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
+ UINT32_C(0x4)
+ uint8_t unused_4[3];
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t queue_id2_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint32_t queue_id2_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id2_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint16_t cmpl_ring;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t queue_id2_pri_lvl;
+ uint16_t seq_id;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint8_t queue_id2_bw_weight;
- /* ID of CoS Queue 3. */
- uint8_t queue_id3;
+ uint16_t target_id;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t queue_id3_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
*/
- uint32_t queue_id3_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id3_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
+ uint16_t data_len;
+ uint16_t flags;
+ /*
+ * If set, the port_id field should be interpreted as an internal
+ * port. The internal port id range is returned in port_phy_qcaps
+ * response internal_port_cnt field.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1)
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
*/
- uint8_t queue_id3_pri_lvl;
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
*/
- uint8_t queue_id3_bw_weight;
- /* ID of CoS Queue 4. */
- uint8_t queue_id4;
+ uint32_t tx_lane_map;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
*/
- uint32_t queue_id4_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint32_t rx_lane_map;
+} __rte_packed;
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t queue_id4_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id4_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_port_dsc_dump *
+ **********************/
+
+
+/* hwrm_port_dsc_dump_input (size:320b/40B) */
+struct hwrm_port_dsc_dump_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t queue_id4_pri_lvl;
+ uint16_t cmpl_ring;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t queue_id4_bw_weight;
- /* ID of CoS Queue 5. */
- uint8_t queue_id5;
+ uint16_t seq_id;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint32_t queue_id5_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint16_t target_id;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t queue_id5_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id5_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
+ uint64_t resp_addr;
+ /* Host address where response diagnostic data is returned. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware
+ * may use this entire buffer or less than the entire buffer, but
+ * never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where dsc dump to be collected. */
+ uint16_t port_id;
+ /* Diag level specified by the user */
+ uint16_t diag_level;
+ /* SRDS_DIAG_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
+ /* SRDS_DIAG_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
+ /* SRDS_DIAG_EVENT */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ /* SRDS_DIAG_EYE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
+ UINT32_C(0x3)
+ /* SRDS_DIAG_REG_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
+ UINT32_C(0x4)
+ /* SRDS_DIAG_REG_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
+ UINT32_C(0x5)
+ /* SRDS_DIAG_UC_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
+ UINT32_C(0x6)
+ /* SRDS_DIAG_UC_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
+ UINT32_C(0x7)
+ /* SRDS_DIAG_LANE_DEBUG */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
+ UINT32_C(0x8)
+ /* SRDS_DIAG_BER_VERT */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
+ UINT32_C(0x9)
+ /* SRDS_DIAG_BER_HORZ */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
+ UINT32_C(0xa)
+ /* SRDS_DIAG_EVENT_SAFE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
+ UINT32_C(0xb)
+ /* SRDS_DIAG_TIMESTAMP */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
+ UINT32_C(0xc)
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
+ HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
+ /*
+ * This field is a lane number
+ * on which to collect the dsc dump
+ */
+ uint16_t lane_number;
+ /*
+ * Configuration bits.
+ * Use enable bit to start dsc dump or retrieve dump
+ */
+ uint16_t dsc_dump_config;
+ /*
+ * Set 0 to retrieve the dsc dump
+ * Set 1 to start the dsc dump
+ */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
+ UINT32_C(0x1)
+} __rte_packed;
+
+/* hwrm_port_dsc_dump_output (size:128b/16B) */
+struct hwrm_port_dsc_dump_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_port_sfp_sideband_cfg *
+ ******************************/
+
+
+/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
+struct hwrm_port_sfp_sideband_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+ /*
+ * This bitfield is used to specify which bits from the 'flags'
+ * fields are being configured by the caller.
+ */
+ uint32_t enables;
+ /* This bit must be '1' for rs0 to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
+ UINT32_C(0x1)
+ /* This bit must be '1' for rs1 to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
+ UINT32_C(0x2)
+ /* This bit must be '1' for tx_disable to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for mod_sel to be configured.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for reset_l to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
+ UINT32_C(0x10)
+ /* This bit must be '1' for lp_mode to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
+ UINT32_C(0x20)
+ /* This bit must be '1' for pwr_disable to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
+ UINT32_C(0x40)
+ /*
+ * Only bits that have corresponding bits in the 'enables'
+ * bitfield are processed by the firmware, all other bits
+ * of 'flags' are ignored.
+ */
+ uint32_t flags;
+ /*
+ * This bit along with rs1 configures the current speed of the dual
+ * rate module. If these pins are GNDed then the speed can be changed
+ * by directly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
+ UINT32_C(0x1)
+ /*
+ * This bit along with rs0 configures the current speed of the dual
+ * rate module. If these pins are GNDed then the speed can be changed
+ * by directly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
+ UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', tx_disable is set.
+ * On a 1G BASE-T module, if this bit is set,
+ * module PHY registers will not be accessible.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
+ UINT32_C(0x4)
+ /*
+ * When this bit is set to '1', this module is selected.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
+ UINT32_C(0x8)
+ /*
+ * If reset_l is set to 0, Module will be taken out of reset
+ * and other signals will be set to their requested state once
+ * the module is out of reset.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
+ UINT32_C(0x10)
+ /*
+ * When this bit is set to '1', the module will be configured
+ * in low power mode.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
+ UINT32_C(0x20)
+ /* When this bit is set to '1', the module will be powered down. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
+ UINT32_C(0x40)
+} __rte_packed;
+
+/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
+struct hwrm_port_sfp_sideband_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_port_sfp_sideband_qcfg *
+ *******************************/
+
+
+/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
+struct hwrm_port_sfp_sideband_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
+struct hwrm_port_sfp_sideband_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Bitmask indicating which sideband signals are valid.
+ * This is based on the board and nvm cfg that is present on the board.
+ */
+ uint32_t supported_mask;
+ uint32_t sideband_signals;
+ /* When this bit is set to '1', the Module is absent. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', there is no valid signal on RX.
+ * This signal is a filtered version of Signal Detect.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
+ UINT32_C(0x2)
+ /*
+ * This bit along with rs1 indicates the current speed of the dual
+ * rate module.If these pins are grounded then the speed can be
+ * changed by directly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
+ UINT32_C(0x4)
+ /*
+ * This bit along with rs0 indicates the current speed of the dual
+ * rate module.If these pins are grounded then the speed can be
+ * changed by directly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
+ UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', tx_disable is set.
+ * On a 1G BASE-T module, if this bit is set, module PHY
+ * registers will not be accessible.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
+ UINT32_C(0x10)
+ /* When this bit is set to '1', tx_fault is set. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
+ UINT32_C(0x20)
+ /*
+ * When this bit is set to '1', module is selected.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
+ UINT32_C(0x40)
+ /*
+ * When this bit is set to '0', the module is held in reset.
+ * if reset_l is set to 1,first module is taken out of reset
+ * and other signals will be set to their requested state.
+ * Valid only on QSFP modules.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
+ UINT32_C(0x80)
+ /*
+ * When this bit is set to '1', the module is in low power mode.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
+ UINT32_C(0x100)
+ /* When this bit is set to '1', module is in power down state. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
+ UINT32_C(0x200)
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************************
+ * hwrm_port_phy_mdio_bus_acquire *
+ **********************************/
+
+
+/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
+struct hwrm_port_phy_mdio_bus_acquire_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of the port. */
+ uint16_t port_id;
+ /*
+ * client_id of the client requesting BUS access.
+ * Any value from 0x10 to 0xFFFF can be used.
+ * Client should make sure that the returned client_id
+ * in response matches the client_id in request.
+ * 0-0xF are reserved for internal use.
+ */
+ uint16_t client_id;
+ /*
+ * Timeout in milli seconds, MDIO BUS will be released automatically
+ * after this time, if another mdio acquire command is not received
+ * within the timeout window from the same client.
+ * A 0xFFFF will hold the bus until this bus is released.
+ */
+ uint16_t mdio_bus_timeout;
+ uint8_t unused_0[2];
+} __rte_packed;
+
+/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_bus_acquire_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t unused_0;
+ /*
+ * client_id of the module holding the BUS.
+ * 0-0xF are reserved for internal use.
+ */
+ uint16_t client_id;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************************
+ * hwrm_port_phy_mdio_bus_release *
+ **********************************/
+
+
+/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
+struct hwrm_port_phy_mdio_bus_release_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of the port. */
+ uint16_t port_id;
+ /*
+ * client_id of the client requesting BUS release.
+ * A client should not release any other clients BUS.
+ */
+ uint16_t client_id;
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_bus_release_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t unused_0;
+ /* The BUS is released if client_id matches the client_id in request. */
+ uint16_t clients_id;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_port_tx_fir_cfg *
+ ************************/
+
+
+/* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
+struct hwrm_port_tx_fir_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Modulation types of TX FIR: NRZ, PAM4. */
+ uint8_t mod_type;
+ /* For NRZ */
+ #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
+ /* For PAM4 */
+ #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
+ #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
+ HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
+ /* The lane mask of the lane TX FIR will be configured. */
+ uint8_t lane_mask;
+ uint8_t unused_0[2];
+ /* Value1 of TX FIR, required for NRZ or PAM4. */
+ uint32_t txfir_val_1;
+ /* Value2 of TX FIR, required for NRZ or PAM4. */
+ uint32_t txfir_val_2;
+ /* Value3 of TX FIR, required for PAM4. */
+ uint32_t txfir_val_3;
+ /* Value4 of TX FIR, required for PAM4. */
+ uint32_t txfir_val_4;
+ uint8_t unused_1[4];
+} __rte_packed;
+
+/* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
+struct hwrm_port_tx_fir_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_port_tx_fir_qcfg *
+ *************************/
+
+
+/* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
+struct hwrm_port_tx_fir_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Modulation types of TX FIR: NRZ, PAM4. */
+ uint8_t mod_type;
+ /* For NRZ */
+ #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
+ /* For PAM4 */
+ #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
+ #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
+ HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
+ /* The ID of the lane TX FIR will be queried. */
+ uint8_t lane_id;
+ uint8_t unused[6];
+} __rte_packed;
+
+/* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
+struct hwrm_port_tx_fir_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Value1 of TX FIR, required for NRZ or PAM4. */
+ uint32_t txfir_val_1;
+ /* Value2 of TX FIR, required for NRZ or PAM4. */
+ uint32_t txfir_val_2;
+ /* Value3 of TX FIR, required for PAM4. */
+ uint32_t txfir_val_3;
+ /* Value4 of TX FIR, required for PAM4. */
+ uint32_t txfir_val_4;
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_port_ep_tx_cfg *
+ ***********************/
+
+
+/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */
+struct hwrm_port_ep_tx_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t enables;
+ /* When this bit is '1', the value in the ep0_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
+ /* When this bit is '1', the value in the ep0_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
+ /* When this bit is '1', the value in the ep1_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
+ /* When this bit is '1', the value in the ep1_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
+ /* When this bit is '1', the value in the ep2_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
+ /* When this bit is '1', the value in the ep2_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
+ /* When this bit is '1', the value in the ep3_min_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
+ /* When this bit is '1', the value in the ep3_max_bw field is valid. */
+ #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
+ /* A port index, from 0 to the number of front panel ports, minus 1. */
+ uint8_t port_id;
+ uint8_t unused;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep0_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep0_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep1_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep1_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep2_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set of
+ * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of
+ * the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep2_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep3_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep3_max_bw;
+ uint8_t unused_1[4];
+} __rte_packed;
+
+/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */
+struct hwrm_port_ep_tx_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */
+struct hwrm_port_ep_tx_cfg_cmd_err {
+ /*
+ * command specific error codes for the cmd_err field in
+ * hwrm_err_output
+ */
+ uint8_t code;
+ /* Unknown error. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /* The port ID is invalid */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \
+ UINT32_C(0x1)
+ /* One of the PCIe endpoints configured is not active. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \
+ UINT32_C(0x2)
+ /* A minimum bandwidth is out of range. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \
+ UINT32_C(0x3)
+ /*
+ * One endpoint's minimum bandwidth is more than its maximum
+ * bandwidth.
+ */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \
+ UINT32_C(0x4)
+ /* The sum of the minimum bandwidths on the port is more than 100%. */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \
+ UINT32_C(0x5)
+ /*
+ * The NIC does not support enforcement of a minimum guaranteed
+ * bandwidth for an endpoint.
+ */
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \
+ UINT32_C(0x6)
+ #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \
+ HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/************************
+ * hwrm_port_ep_tx_qcfg *
+ ************************/
+
+
+/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */
+struct hwrm_port_ep_tx_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The port whose endpoint rate limits are queried. */
+ uint8_t port_id;
+ uint8_t unused[7];
+} __rte_packed;
+
+/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */
+struct hwrm_port_ep_tx_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep0_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep0_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep1_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep1_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep2_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep2_max_bw;
+ /*
+ * Specifies a minimum guaranteed bandwidth, as a percentage of the
+ * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for
+ * the specified port. The range is 0 to 100. A value of 0 indicates no
+ * minimum rate. The endpoint's min_bw must be less than or equal to
+ * max_bw. The sum of all configured minimum bandwidths for a port must
+ * be less than or equal to 100.
+ */
+ uint8_t ep3_min_bw;
+ /*
+ * Specifies the maximum portion of the port's bandwidth that the set
+ * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage
+ * of the link bandwidth, from 0 to 100. A value of 0 indicates no
+ * maximum rate.
+ */
+ uint8_t ep3_max_bw;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_queue_qportcfg *
+ ***********************/
+
+
+/* hwrm_queue_qportcfg_input (size:192b/24B) */
+struct hwrm_queue_qportcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
+ /*
+ * Port ID of port for which the queue configuration is being
+ * queried. This field is only required when sent by IPC.
+ */
+ uint16_t port_id;
+ /*
+ * Drivers will set this capability when it can use
+ * queue_idx_service_profile to map the queues to application.
+ */
+ uint8_t drv_qmap_cap;
+ /* disabled */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
+ /* enabled */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
+ HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
+ uint8_t unused_0;
+} __rte_packed;
+
+/* hwrm_queue_qportcfg_output (size:1344b/168B) */
+struct hwrm_queue_qportcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * The maximum number of queues that can be configured on this
+ * port.
+ * Valid values range from 1 through 8.
+ */
+ uint8_t max_configurable_queues;
+ /*
+ * The maximum number of lossless queues that can be configured
+ * on this port.
+ * Valid values range from 0 through 8.
+ */
+ uint8_t max_configurable_lossless_queues;
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_cfg command shall return error when trying to
+ * configure a queue not configurable.
+ */
+ uint8_t queue_cfg_allowed;
+ /* Information about queue configuration. */
+ uint8_t queue_cfg_info;
+ /*
+ * If this flag is set to '1', then the queues are
+ * configured asymmetrically on TX and RX sides.
+ * If this flag is set to '0', then the queues are
+ * configured symmetrically on TX and RX sides. For
+ * symmetric configuration, the queue configuration
+ * including queue ids and service profiles on the
+ * TX side is the same as the corresponding queue
+ * configuration on the RX side.
+ */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ UINT32_C(0x1)
+ /*
+ * If this flag is set to '1', then service_profile will carry
+ * either lossy/lossless type and the new service_profile_type
+ * field will be used to determine if the queue is for L2/ROCE/CNP.
+ */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \
+ UINT32_C(0x2)
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pfcenable_cfg command.
+ *
+ * Each bit represents a specific priority where bit 0 represents
+ * priority 0 and bit 7 represents priority 7.
+ * # A value of 0 indicates that the priority is not configurable by
+ * the hwrm_queue_pfcenable_cfg command.
+ * # A value of 1 indicates that the priority is configurable.
+ * # A hwrm_queue_pfcenable_cfg command shall return error when
+ * trying to configure a priority that is not configurable.
+ */
+ uint8_t queue_pfcenable_cfg_allowed;
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pri2cos_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_pri2cos_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_pri2cos_cfg command shall return error when
+ * trying to configure a queue that is not configurable.
+ */
+ uint8_t queue_pri2cos_cfg_allowed;
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_pri2cos_cfg command.
+ *
+ * Each bit represents a specific queue where bit 0 represents
+ * queue 0 and bit 7 represents queue 7.
+ * # A value of 0 indicates that the queue is not configurable
+ * by the hwrm_queue_pri2cos_cfg command.
+ * # A value of 1 indicates that the queue is configurable.
+ * # A hwrm_queue_pri2cos_cfg command shall return error when
+ * trying to configure a queue not configurable.
+ */
+ uint8_t queue_cos2bw_cfg_allowed;
+ /*
+ * ID of CoS Queue 0.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id0;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id0_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 1.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id1;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id1_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 2.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id2;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id2_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 3.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id3;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id3_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 4.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id4;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id4_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 5.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id5;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id5_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 6.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id6;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id6_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
+ /*
+ * ID of CoS Queue 7.
+ * FF - Invalid id
+ *
+ * # This ID can be used on any subsequent call to an hwrm command
+ * that takes a queue id.
+ * # IDs must always be queried by this command before any use
+ * by the driver or software.
+ * # The CoS queue index is obtained by applying modulo 10 to the
+ * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
+ * The CoS queue index is used to reference port statistics for the
+ * CoS queue.
+ * # A value of 0xff indicates that the queue is not available.
+ * # Available queues may not be in sequential order.
+ */
+ uint8_t queue_id7;
+ /* This value specifies service profile kind for CoS queue */
+ uint8_t queue_id7_service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
+ UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
+ UINT32_C(0x1)
+ /* Lossless RoCE (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
+ UINT32_C(0x1)
+ /* Lossy RoCE CNP (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
+ UINT32_C(0x2)
+ /* Lossless NIC (deprecated) */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
+ UINT32_C(0x3)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
+ UINT32_C(0xff)
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id0_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * Up to 16 bytes of null padded ASCII string describing this queue.
+ * The queue name includes a CoS queue index and, in some cases, text
+ * that distinguishes the queue from other queues in the group.
+ */
+ char qid0_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid1_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid2_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid3_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid4_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid5_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid6_name[16];
+ /* Up to 16 bytes of null padded ASCII string describing this queue. */
+ char qid7_name[16];
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id1_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id2_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id3_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id4_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id5_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id6_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This value specifies traffic type for the service profile. We can
+ * have a TC mapped to multiple traffic types. For example shared
+ * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
+ * A value of zero is considered as invalid.
+ */
+ uint8_t queue_id7_service_profile_type;
+ /* Recommended to be used for RoCE traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
+ UINT32_C(0x1)
+ /* Recommended to be used for NIC/L2 traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
+ UINT32_C(0x2)
+ /* Recommended to be used for CNP traffic only. */
+ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
+ UINT32_C(0x4)
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************
+ * hwrm_queue_qcfg *
+ *******************/
+
+
+/* hwrm_queue_qcfg_input (size:192b/24B) */
+struct hwrm_queue_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
+ /* Queue ID of the queue. */
+ uint32_t queue_id;
+} __rte_packed;
+
+/* hwrm_queue_qcfg_output (size:128b/16B) */
+struct hwrm_queue_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * This value is the estimate packet length used in the
+ * TX arbiter.
+ */
+ uint32_t queue_len;
+ /* This value is applicable to CoS queues only. */
+ uint8_t service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
+ #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
+ /* Information about queue configuration. */
+ uint8_t queue_cfg_info;
+ /*
+ * If this flag is set to '1', then the queue is
+ * configured asymmetrically on TX and RX sides.
+ * If this flag is set to '0', then this queue is
+ * configured symmetrically on TX and RX sides.
+ */
+ #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ UINT32_C(0x1)
+ uint8_t unused_0;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************
+ * hwrm_queue_cfg *
+ ******************/
+
+
+/* hwrm_queue_cfg_input (size:320b/40B) */
+struct hwrm_queue_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX, or both directions applicable to the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
+ /* tx path */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ /* Bi-directional (Symmetrically applicable to TX and RX paths) */
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
+ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the dflt_len field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the service_profile field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
+ /* Queue ID of queue that is to be configured by this function. */
+ uint32_t queue_id;
+ /*
+ * This value is a the estimate packet length used in the
+ * TX arbiter.
+ * Set to 0xFF... (All Fs) to not adjust this value.
+ */
+ uint32_t dflt_len;
+ /* This value is applicable to CoS queues only. */
+ uint8_t service_profile;
+ /* Lossy (best-effort) */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
+ /* Lossless */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
+ /* Set to 0xFF... (All Fs) if there is no service profile specified */
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
+ #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
+ HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_cfg_output (size:128b/16B) */
+struct hwrm_queue_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_queue_pfcenable_qcfg *
+ *****************************/
+
+
+/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
+struct hwrm_queue_pfcenable_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
+struct hwrm_queue_pfcenable_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /* If set to 1, then PFC is enabled on PRI 0. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
+ UINT32_C(0x1)
+ /* If set to 1, then PFC is enabled on PRI 1. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
+ UINT32_C(0x2)
+ /* If set to 1, then PFC is enabled on PRI 2. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
+ UINT32_C(0x4)
+ /* If set to 1, then PFC is enabled on PRI 3. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
+ UINT32_C(0x8)
+ /* If set to 1, then PFC is enabled on PRI 4. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
+ UINT32_C(0x10)
+ /* If set to 1, then PFC is enabled on PRI 5. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
+ UINT32_C(0x20)
+ /* If set to 1, then PFC is enabled on PRI 6. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
+ UINT32_C(0x40)
+ /* If set to 1, then PFC is enabled on PRI 7. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
+ UINT32_C(0x80)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x100)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x200)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x400)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x800)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x1000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x2000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x4000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
+ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x8000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_queue_pfcenable_cfg *
+ ****************************/
+
+
+/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
+struct hwrm_queue_pfcenable_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If set to 1, then PFC is requested to be enabled on PRI 0. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
+ UINT32_C(0x1)
+ /* If set to 1, then PFC is requested to be enabled on PRI 1. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
+ UINT32_C(0x2)
+ /* If set to 1, then PFC is requested to be enabled on PRI 2. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
+ UINT32_C(0x4)
+ /* If set to 1, then PFC is requested to be enabled on PRI 3. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
+ UINT32_C(0x8)
+ /* If set to 1, then PFC is requested to be enabled on PRI 4. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
+ UINT32_C(0x10)
+ /* If set to 1, then PFC is requested to be enabled on PRI 5. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
+ UINT32_C(0x20)
+ /* If set to 1, then PFC is requested to be enabled on PRI 6. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
+ UINT32_C(0x40)
+ /* If set to 1, then PFC is requested to be enabled on PRI 7. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
+ UINT32_C(0x80)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x100)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x200)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x400)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x800)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x1000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x2000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x4000)
+ /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
+ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
+ UINT32_C(0x8000)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint16_t port_id;
+ uint8_t unused_0[2];
+} __rte_packed;
+
+/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
+struct hwrm_queue_pfcenable_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_queue_pri2cos_qcfg *
+ ***************************/
+
+
+/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
+struct hwrm_queue_pri2cos_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
+ /*
+ * When this bit is set to '0', the query is
+ * for PRI from tunnel headers.
+ * When this bit is set to '1', the query is
+ * for PRI from inner packet headers.
+ */
+ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[3];
+} __rte_packed;
+
+/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
+struct hwrm_queue_pri2cos_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * CoS Queue assigned to priority 0. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri0_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 1. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri1_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 2. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri2_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 3. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri3_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 4. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri4_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 5. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri5_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 6. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri6_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 7. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no CoS queue is assigned to the
+ * specified priority.
+ */
+ uint8_t pri7_cos_queue_id;
+ /* Information about queue configuration. */
+ uint8_t queue_cfg_info;
+ /*
+ * If this flag is set to '1', then the PRI to CoS
+ * configuration is asymmetric on TX and RX sides.
+ * If this flag is set to '0', then PRI to CoS configuration
+ * is symmetric on TX and RX sides.
+ */
+ #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
+ UINT32_C(0x1)
+ uint8_t unused_0[6];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_queue_pri2cos_cfg *
+ **************************/
+
+
+/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
+struct hwrm_queue_pri2cos_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX, or both directions applicable to the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
+ /* tx path */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ /* Bi-directional (Symmetrically applicable to TX and RX paths) */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
+ /*
+ * When this bit is set to '0', the mapping is requested
+ * for PRI from tunnel headers.
+ * When this bit is set to '1', the mapping is requested
+ * for PRI from inner packet headers.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the pri0_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the pri1_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the pri2_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the pri3_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the pri4_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the pri5_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the pri6_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the pri7_cos_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
+ UINT32_C(0x80)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ /*
+ * CoS Queue assigned to priority 0. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri0_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 1. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri1_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 2 This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri2_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 3. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri3_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 4. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri4_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 5. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri5_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 6. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri6_cos_queue_id;
+ /*
+ * CoS Queue assigned to priority 7. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t pri7_cos_queue_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
+struct hwrm_queue_pri2cos_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_queue_cos2bw_qcfg *
+ **************************/
+
+
+/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
+struct hwrm_queue_cos2bw_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure TC BW assignment on this port.
+ */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
+struct hwrm_queue_cos2bw_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* ID of CoS Queue 0. */
+ uint8_t queue_id0;
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id0_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id0_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id0_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id0_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id0_bw_weight;
+ /* ID of CoS Queue 1. */
+ uint8_t queue_id1;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id1_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id1_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id1_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id1_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id1_bw_weight;
+ /* ID of CoS Queue 2. */
+ uint8_t queue_id2;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id2_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id2_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id2_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id2_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id2_bw_weight;
+ /* ID of CoS Queue 3. */
+ uint8_t queue_id3;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id3_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id3_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id3_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id3_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id3_bw_weight;
+ /* ID of CoS Queue 4. */
+ uint8_t queue_id4;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id4_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id4_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id4_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id4_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id4_bw_weight;
+ /* ID of CoS Queue 5. */
+ uint8_t queue_id5;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id5_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id5_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id5_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id5_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id5_bw_weight;
+ /* ID of CoS Queue 6. */
+ uint8_t queue_id6;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id6_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id6_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id6_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id6_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id6_bw_weight;
+ /* ID of CoS Queue 7. */
+ uint8_t queue_id7;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id7_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id7_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id7_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id7_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id7_bw_weight;
+ uint8_t unused_2[4];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_queue_cos2bw_cfg *
+ *************************/
+
+
+/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
+struct hwrm_queue_cos2bw_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint32_t enables;
+ /*
+ * If this bit is set to 1, then all queue_id0 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
+ UINT32_C(0x1)
+ /*
+ * If this bit is set to 1, then all queue_id1 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
+ UINT32_C(0x2)
+ /*
+ * If this bit is set to 1, then all queue_id2 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
+ UINT32_C(0x4)
+ /*
+ * If this bit is set to 1, then all queue_id3 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
+ UINT32_C(0x8)
+ /*
+ * If this bit is set to 1, then all queue_id4 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
+ UINT32_C(0x10)
+ /*
+ * If this bit is set to 1, then all queue_id5 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
+ UINT32_C(0x20)
+ /*
+ * If this bit is set to 1, then all queue_id6 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
+ UINT32_C(0x40)
+ /*
+ * If this bit is set to 1, then all queue_id7 related
+ * parameters in this command are valid.
+ */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
+ UINT32_C(0x80)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure TC BW assignment on this port.
+ */
+ uint16_t port_id;
+ /* ID of CoS Queue 0. */
+ uint8_t queue_id0;
+ uint8_t unused_0;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id0_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id0_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id0_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id0_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id0_bw_weight;
+ /* ID of CoS Queue 1. */
+ uint8_t queue_id1;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id1_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id1_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id1_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id1_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id1_bw_weight;
+ /* ID of CoS Queue 2. */
+ uint8_t queue_id2;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id2_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id2_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id2_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id2_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id2_bw_weight;
+ /* ID of CoS Queue 3. */
+ uint8_t queue_id3;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id3_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id3_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id3_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id3_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id3_bw_weight;
+ /* ID of CoS Queue 4. */
+ uint8_t queue_id4;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id4_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id4_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id4_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id4_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id4_bw_weight;
+ /* ID of CoS Queue 5. */
+ uint8_t queue_id5;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id5_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id5_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id5_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id5_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id5_bw_weight;
+ /* ID of CoS Queue 6. */
+ uint8_t queue_id6;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id6_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id6_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id6_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id6_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id6_bw_weight;
+ /* ID of CoS Queue 7. */
+ uint8_t queue_id7;
+ /*
+ * Minimum BW allocated to CoS Queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id7_min_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * Maximum BW allocated to CoS queue.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this COS inside the device.
+ */
+ uint32_t queue_id7_max_bw;
+ /* The bandwidth value. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
+ /* Transmission Selection Algorithm (TSA) for CoS Queue. */
+ uint8_t queue_id7_tsa_assign;
+ /* Strict Priority */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
+ UINT32_C(0x0)
+ /* Enhanced Transmission Selection */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
+ UINT32_C(0x1)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
+ UINT32_C(0x2)
+ /* reserved. */
+ #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
+ UINT32_C(0xff)
+ /*
+ * Priority level for strict priority. Valid only when the
+ * tsa_assign is 0 - Strict Priority (SP)
+ * 0..7 - Valid values.
+ * 8..255 - Reserved.
+ */
+ uint8_t queue_id7_pri_lvl;
+ /*
+ * Weight used to allocate remaining BW for this COS after
+ * servicing guaranteed bandwidths for all COS.
+ */
+ uint8_t queue_id7_bw_weight;
+ uint8_t unused_1[5];
+} __rte_packed;
+
+/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
+struct hwrm_queue_cos2bw_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_queue_dscp_qcaps *
+ *************************/
+
+
+/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
+struct hwrm_queue_dscp_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
+struct hwrm_queue_dscp_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of bits provided by the hardware for the DSCP value. */
+ uint8_t num_dscp_bits;
+ uint8_t unused_0;
+ /* Max number of DSCP-MASK-PRI entries supported. */
+ uint16_t max_entries;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_queue_dscp2pri_qcfg *
+ ****************************/
+
+
+/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
+struct hwrm_queue_dscp2pri_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * This is the host address where the 24-bits DSCP-MASK-PRI
+ * tuple(s) will be copied to.
+ */
+ uint64_t dest_data_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0;
+ /* Size of the buffer pointed to by dest_data_addr. */
+ uint16_t dest_data_buffer_size;
+ uint8_t unused_1[4];
+} __rte_packed;
+
+/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
+struct hwrm_queue_dscp2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
+ * by the dest_data_addr.
+ */
+ uint16_t entry_cnt;
+ /*
+ * This is the default PRI which un-initialized DSCP values are
+ * mapped to.
+ */
+ uint8_t default_pri;
+ uint8_t unused_0[4];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_queue_dscp2pri_cfg *
+ ***************************/
+
+
+/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
+struct hwrm_queue_dscp2pri_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * This is the host address where the 24-bits DSCP-MASK-PRI tuple
+ * will be copied from.
+ */
+ uint64_t src_data_addr;
+ uint32_t flags;
+ /* use_hw_default_pri is 1 b */
+ #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the default_pri field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
+ UINT32_C(0x1)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ /*
+ * This is the default PRI which un-initialized DSCP values will be
+ * mapped to.
+ */
+ uint8_t default_pri;
+ /*
+ * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
+ * to by src_data_addr.
+ */
+ uint16_t entry_cnt;
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_dscp2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_queue_mpls_qcaps *
+ *************************/
+
+
+/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
+struct hwrm_queue_mpls_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP) to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
+struct hwrm_queue_mpls_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_mplstc2pri_cfg command.
+ *
+ * Each bit represents a specific pri where bit 0 represents
+ * pri 0 and bit 7 represents pri 7.
+ * # A value of 0 indicates that the pri is not configurable
+ * by the hwrm_queue_mplstc2pri_cfg command.
+ * # A value of 1 indicates that the pri is configurable.
+ * # A hwrm_queue_mplstc2pri_cfg command shall return error when
+ * trying to configure a pri that is not configurable.
+ */
+ uint8_t queue_mplstc2pri_cfg_allowed;
+ /*
+ * This is the default PRI which un-initialized MPLS values will be
+ * mapped to.
+ */
+ uint8_t hw_default_pri;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_queue_mplstc2pri_qcfg *
+ ******************************/
+
+
+/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
+struct hwrm_queue_mplstc2pri_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP) to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
+struct hwrm_queue_mplstc2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * pri assigned to MPLS TC(EXP) 0. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 0.
+ */
+ uint8_t tc0_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 1. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 1.
+ */
+ uint8_t tc1_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 2. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 2.
+ */
+ uint8_t tc2_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 3. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 3.
+ */
+ uint8_t tc3_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 4. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 4.
+ */
+ uint8_t tc4_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 5. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 5.
+ */
+ uint8_t tc5_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 6. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 6.
+ */
+ uint8_t tc6_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 7. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 7.
+ */
+ uint8_t tc7_pri_queue_id;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_queue_mplstc2pri_cfg *
+ *****************************/
+
+
+/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
+struct hwrm_queue_mplstc2pri_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the mplstc0_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the mplstc1_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the mplstc2_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the mplstc3_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the mplstc4_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the mplstc5_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the mplstc6_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the mplstc7_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
+ UINT32_C(0x80)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP)to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[3];
+ /*
+ * pri assigned to MPLS TC(EXP) 0. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc0_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 1. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc1_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 2 This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc2_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 3. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc3_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 4. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc4_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 5. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc5_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 6. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc6_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 7. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc7_pri_queue_id;
+} __rte_packed;
+
+/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_mplstc2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_queue_vlanpri_qcaps *
+ ****************************/
+
+
+/* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
+struct hwrm_queue_vlanpri_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure VLAN priority to user priority mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
+struct hwrm_queue_vlanpri_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * This is the default user priority which all VLAN priority values
+ * are mapped to if there is no VLAN priority to user priority mapping.
+ */
+ uint8_t hw_default_pri;
+ uint8_t unused_0[6];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_queue_vlanpri2pri_qcfg *
+ *******************************/
+
+
+/* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
+struct hwrm_queue_vlanpri2pri_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t queue_id5_pri_lvl;
+ uint16_t cmpl_ring;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t queue_id5_bw_weight;
- /* ID of CoS Queue 6. */
- uint8_t queue_id6;
+ uint16_t seq_id;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint32_t queue_id6_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint16_t target_id;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t queue_id6_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id6_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint64_t resp_addr;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure VLAN priority to user priority mapping on this port.
*/
- uint8_t queue_id6_pri_lvl;
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
+struct hwrm_queue_vlanpri2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * User priority assigned to VLAN priority 0. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
*/
- uint8_t queue_id6_bw_weight;
- /* ID of CoS Queue 7. */
- uint8_t queue_id7;
+ uint8_t vlanpri0_user_pri_id;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * User priority assigned to VLAN priority 1. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
*/
- uint32_t queue_id7_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t vlanpri1_user_pri_id;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * User priority assigned to VLAN priority 2. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
*/
- uint32_t queue_id7_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id7_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint8_t vlanpri2_user_pri_id;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * User priority assigned to VLAN priority 3. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
*/
- uint8_t queue_id7_pri_lvl;
+ uint8_t vlanpri3_user_pri_id;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * User priority assigned to VLAN priority 4. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
*/
- uint8_t queue_id7_bw_weight;
- uint8_t unused_2[4];
+ uint8_t vlanpri4_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 5. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri5_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 6. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri6_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 7. A value of 0xff
+ * indicates that no user priority is assigned. The default user
+ * priority will be used.
+ */
+ uint8_t vlanpri7_user_pri_id;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*************************
- * hwrm_queue_cos2bw_cfg *
- *************************/
+/******************************
+ * hwrm_queue_vlanpri2pri_cfg *
+ ******************************/
-/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
-struct hwrm_queue_cos2bw_cfg_input {
+/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
+struct hwrm_queue_vlanpri2pri_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
uint32_t enables;
/*
- * If this bit is set to 1, then all queue_id0 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri0_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
UINT32_C(0x1)
/*
- * If this bit is set to 1, then all queue_id1 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri1_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
UINT32_C(0x2)
/*
- * If this bit is set to 1, then all queue_id2 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri2_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
UINT32_C(0x4)
/*
- * If this bit is set to 1, then all queue_id3 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri3_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
UINT32_C(0x8)
/*
- * If this bit is set to 1, then all queue_id4 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri4_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
UINT32_C(0x10)
/*
- * If this bit is set to 1, then all queue_id5 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri5_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
UINT32_C(0x20)
/*
- * If this bit is set to 1, then all queue_id6 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri6_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
UINT32_C(0x40)
/*
- * If this bit is set to 1, then all queue_id7 related
- * parameters in this command are valid.
+ * This bit must be '1' for the vlanpri7_user_pri_id field to be
+ * configured.
*/
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
+ #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
UINT32_C(0x80)
/*
* Port ID of port for which the table is being configured.
* The HWRM needs to check whether this function is allowed
- * to configure TC BW assignment on this port.
+ * to configure VLAN priority to user priority mapping on this port.
*/
- uint16_t port_id;
- /* ID of CoS Queue 0. */
- uint8_t queue_id0;
- uint8_t unused_0;
+ uint8_t port_id;
+ uint8_t unused_0[3];
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * User priority assigned to VLAN priority 0. This value can only
+ * be changed before traffic has started.
*/
- uint32_t queue_id0_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t vlanpri0_user_pri_id;
/*
- * Maximum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * User priority assigned to VLAN priority 1. This value can only
+ * be changed before traffic has started.
*/
- uint32_t queue_id0_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id0_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint8_t vlanpri1_user_pri_id;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * User priority assigned to VLAN priority 2. This value can only
+ * be changed before traffic has started.
*/
- uint8_t queue_id0_pri_lvl;
+ uint8_t vlanpri2_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 3. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t vlanpri3_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 4. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t vlanpri4_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 5. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t vlanpri5_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 6. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t vlanpri6_user_pri_id;
+ /*
+ * User priority assigned to VLAN priority 7. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t vlanpri7_user_pri_id;
+} __rte_packed;
+
+/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_vlanpri2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_queue_global_cfg *
+ *************************/
+
+
+/* hwrm_queue_global_cfg_input (size:192b/24B) */
+struct hwrm_queue_global_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Configuration mode for rx cos queues, configuring whether they
+ * use one shared buffer pool (across ports or PCIe endpoints) or
+ * independent per port or per endpoint buffer pools.
+ */
+ uint8_t mode;
+ /* One shared buffer pool to be used by all RX CoS queues */
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
+ /*
+ * Each port or PCIe endpoint to use an independent buffer pool
+ * for its RX CoS queues
+ */
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \
+ HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT
+ uint8_t unused_0;
+ uint16_t enables;
+ /* This bit must be '1' when the mode field is configured. */
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * This bit must be '1' when the maximum bandwidth for queue group 0
+ * (g0_max_bw) is configured.
*/
- uint8_t queue_id0_bw_weight;
- /* ID of CoS Queue 1. */
- uint8_t queue_id1;
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * This bit must be '1' when the maximum bandwidth for queue group 1
+ * (g1_max_bw) is configured.
*/
- uint32_t queue_id1_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * This bit must be '1' when the maximum bandwidth for queue group 2
+ * (g2_max_bw) is configured.
*/
- uint32_t queue_id1_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id1_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * This bit must be '1' when the maximum bandwidth for queue group 3
+ * (g3_max_bw) is configured.
*/
- uint8_t queue_id1_pri_lvl;
+ #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \
+ UINT32_C(0x10)
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * Specifies the maximum receive rate, as a percentage of total link
+ * bandwidth, of the receive traffic through queue group 0. A value
+ * of 0 indicates no rate limit.
+ *
+ * A queue group is a set of queues, one per traffic class. In
+ * single-host mode, each panel port has its own queue group, and thus,
+ * this rate limit shapes the traffic received on a port, in this case,
+ * through port 0. In multi-root or multi-host mode, each PCIe endpoint
+ * on the NIC has its own queue group. In these cases, the rate limit
+ * shapes the traffic sent to the host through one of the PCIe
+ * endpoints, in this case endpoint 0.
*/
- uint8_t queue_id1_bw_weight;
- /* ID of CoS Queue 2. */
- uint8_t queue_id2;
+ uint8_t g0_max_bw;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Specifies the maximum rate of the traffic through receive CoS queue
+ * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of
+ * total link bandwidth (the sum of the bandwidths of all links). A
+ * value of 0 indicates no rate limit.
*/
- uint32_t queue_id2_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t g1_max_bw;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Specifies the maximum rate of the traffic through receive CoS queue
+ * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of
+ * total link bandwidth (the sum of the bandwidths of all links). A
+ * value of 0 indicates no rate limit.
*/
- uint32_t queue_id2_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id2_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint8_t g2_max_bw;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * Specifies the maximum receive rate, in Mbps, of the receive traffic
+ * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
+ * indicates no rate limit.
*/
- uint8_t queue_id2_pri_lvl;
+ uint8_t g3_max_bw;
+} __rte_packed;
+
+/* hwrm_queue_global_cfg_output (size:128b/16B) */
+struct hwrm_queue_global_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t queue_id2_bw_weight;
- /* ID of CoS Queue 3. */
- uint8_t queue_id3;
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_queue_global_qcfg *
+ **************************/
+
+
+/* hwrm_queue_global_qcfg_input (size:128b/16B) */
+struct hwrm_queue_global_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint32_t queue_id3_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint16_t cmpl_ring;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint32_t queue_id3_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id3_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
- UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ uint16_t seq_id;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- uint8_t queue_id3_pri_lvl;
+ uint16_t target_id;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint8_t queue_id3_bw_weight;
- /* ID of CoS Queue 4. */
- uint8_t queue_id4;
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_queue_global_qcfg_output (size:320b/40B) */
+struct hwrm_queue_global_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 0. */
+ uint8_t buffer_pool_id0_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 1. */
+ uint8_t buffer_pool_id1_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 2. */
+ uint8_t buffer_pool_id2_map;
+ /* Port or PCIe endpoint id to be mapped for buffer pool 3. */
+ uint8_t buffer_pool_id3_map;
+ /* Size of buffer pool 0 (KBytes). */
+ uint32_t buffer_pool_id0_size;
+ /* Size of buffer pool 1 (KBytes). */
+ uint32_t buffer_pool_id1_size;
+ /* Size of buffer pool 2 (KBytes). */
+ uint32_t buffer_pool_id2_size;
+ /* Size of buffer pool 3 (KBytes). */
+ uint32_t buffer_pool_id3_size;
+ uint16_t flags;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Enumeration denoting whether the rx buffer pool mapping is
+ * per port or per PCIe endpoint
*/
- uint32_t queue_id4_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \
+ UINT32_C(0x1)
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The buffer_pool_id[0-3]_map field represents mapping of rx
+ * buffer pools to a port.
*/
- uint32_t queue_id4_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id4_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \
UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
+ /*
+ * The buffer_pool_id[0-3]_map field represents mapping of rx
+ * buffer pools to a PCIe endpoint.
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
- UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \
+ HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT
+ /*
+ * Configuration mode for rx cos queues, configuring whether they
+ * use one shared buffer pool (across ports or PCIe endpoints) or
+ * independent per port or per endpoint buffer pools.
+ */
+ uint8_t mode;
+ /* One shared buffer pool to be used by all RX CoS queues */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
+ /*
+ * Each port or PCIe endpoint to use an independent buffer pool
+ * for its RX CoS queues
+ */
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
+ #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \
+ HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT
+ uint8_t unused_0;
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 0. The rate limit is a percentage of total link bandwidth. A
+ * value of 0 indicates no rate limit.
+ *
+ * A queue group is a set of queues, one per traffic class. In
+ * single-host mode, each panel port has its own queue group, and thus,
+ * this rate limit shapes the traffic received on a port, in this case,
+ * through port 0. In multi-root or multi-host mode, each PCIe endpoint
+ * on the NIC has its own queue group. In these cases, the rate limit
+ * shapes the traffic sent to the host through one of the PCIe
+ * endpoints, in this case endpoint 0.
*/
- uint8_t queue_id4_pri_lvl;
+ uint8_t g0_max_bw;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
*/
- uint8_t queue_id4_bw_weight;
- /* ID of CoS Queue 5. */
- uint8_t queue_id5;
+ uint8_t g1_max_bw;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
*/
- uint32_t queue_id5_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t g2_max_bw;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * Reports the rate limit applied to traffic through receive CoS queue
+ * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a
+ * percentage of total link bandwidth. A value of 0 indicates no rate
+ * limit.
*/
- uint32_t queue_id5_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id5_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
+ uint8_t g3_max_bw;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************
+ * hwrm_vnic_alloc *
+ *******************/
+
+
+/* hwrm_vnic_alloc_input (size:192b/24B) */
+struct hwrm_vnic_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When this bit is '1', this VNIC is requested to
+ * be the default VNIC for this function.
+ */
+ #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
+ /*
+ * When this bit is '1', proxy VEE PF is requesting
+ * allocation of a default VNIC on behalf of virtio-net
+ * function given in virtio_net_fid field.
+ */
+ #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * Virtio-net function's FID.
+ * This virtio-net function is requesting allocation of default
+ * VNIC through proxy VEE PF.
*/
- uint8_t queue_id5_pri_lvl;
+ uint16_t virtio_net_fid;
+ uint8_t unused_0[2];
+} __rte_packed;
+
+/* hwrm_vnic_alloc_output (size:128b/16B) */
+struct hwrm_vnic_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint8_t unused_0[3];
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint8_t queue_id5_bw_weight;
- /* ID of CoS Queue 6. */
- uint8_t queue_id6;
+ uint8_t valid;
+} __rte_packed;
+
+/********************
+ * hwrm_vnic_update *
+ ********************/
+
+
+/* hwrm_vnic_update_input (size:256b/32B) */
+struct hwrm_vnic_update_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint32_t queue_id6_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint16_t cmpl_ring;
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint32_t queue_id6_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id6_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
- UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vnic_state field to be
+ * configured.
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
+ /*
+ * This bit must be '1' for the mru field to be
+ * configured.
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * This bit must be '1' for the metadata_format_type field to be
+ * configured.
*/
- uint8_t queue_id6_pri_lvl;
+ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
+ UINT32_C(0x4)
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * This bit must be '1' for the rss_hash_function field to be
+ * configured.
*/
- uint8_t queue_id6_bw_weight;
- /* ID of CoS Queue 7. */
- uint8_t queue_id7;
+ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_RSS_HASH_FUNCTION_VALID \
+ UINT32_C(0x8)
/*
- * Minimum BW allocated to CoS Queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * This will update the context variable with the same name if
+ * the corresponding enable is set.
*/
- uint32_t queue_id7_min_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
+ uint8_t vnic_state;
+ /* Normal operation state for the VNIC. */
+ #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
+ /* All packets are dropped in this state. */
+ #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
+ #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
+ HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
/*
- * Maximum BW allocated to CoS queue.
- * The HWRM will translate this value into byte counter and
- * time interval used for this COS inside the device.
+ * The metadata format type used in all the RX packet completions
+ * going through this VNIC.
*/
- uint32_t queue_id7_max_bw;
- /* The bandwidth value. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
- 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
- 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
- /* Transmission Selection Algorithm (TSA) for CoS Queue. */
- uint8_t queue_id7_tsa_assign;
- /* Strict Priority */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
+ uint8_t metadata_format_type;
+ /* No metadata information. */
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
UINT32_C(0x0)
- /* Enhanced Transmission Selection */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
+ /*
+ * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
+ * vtag[19:0]).
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
UINT32_C(0x1)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
+ /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
UINT32_C(0x2)
- /* reserved. */
- #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
- UINT32_C(0xff)
+ /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
+ UINT32_C(0x3)
+ /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
+ UINT32_C(0x4)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
+ HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
/*
- * Priority level for strict priority. Valid only when the
- * tsa_assign is 0 - Strict Priority (SP)
- * 0..7 - Valid values.
- * 8..255 - Reserved.
+ * The maximum receive unit of the vnic.
+ * Each vnic is associated with a function.
+ * The vnic mru value overwrites the mru setting of the
+ * associated function.
+ * The HWRM shall make sure that vnic mru does not exceed
+ * the mru of the port the function is associated with.
*/
- uint8_t queue_id7_pri_lvl;
+ uint16_t mru;
/*
- * Weight used to allocate remaining BW for this COS after
- * servicing guaranteed bandwidths for all COS.
+ * Used to choose the RSS hash algorithm based on which HW
+ * can select the destination ring
*/
- uint8_t queue_id7_bw_weight;
- uint8_t unused_1[5];
+ uint8_t rss_hash_function;
+ /*
+ * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
+ * headers and uses the hash to select the ring.
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_TOEPLITZ UINT32_C(0x0)
+ /*
+ * NIC calculates the RSS hash using the XOR algorithm on L3/L4
+ * headers and uses the hash to select the ring.
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_XOR UINT32_C(0x1)
+ /*
+ * In this mode, RSS hash is calculated with Toeplitz and reported
+ * in the RX completion. However, the ring selection algorithm is
+ * based on the checksum. In this mode, only the innermost L3/L4
+ * packet checksums are used. So this hash function mode will not
+ * be exposed/valid when the outer RSS mode is enabled.
+ */
+ #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM UINT32_C(0x2)
+ #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_LAST \
+ HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM
+ uint8_t unused_1[3];
} __rte_packed;
-/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
-struct hwrm_queue_cos2bw_cfg_output {
+/* hwrm_vnic_update_output (size:128b/16B) */
+struct hwrm_vnic_update_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/*************************
- * hwrm_queue_dscp_qcaps *
- *************************/
+/******************
+ * hwrm_vnic_free *
+ ******************/
-/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
-struct hwrm_queue_dscp_qcaps_input {
+/* hwrm_vnic_free_input (size:192b/24B) */
+struct hwrm_vnic_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- uint8_t unused_0[7];
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
-struct hwrm_queue_dscp_qcaps_output {
+/* hwrm_vnic_free_output (size:128b/16B) */
+struct hwrm_vnic_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The number of bits provided by the hardware for the DSCP value. */
- uint8_t num_dscp_bits;
- uint8_t unused_0;
- /* Max number of DSCP-MASK-PRI entries supported. */
- uint16_t max_entries;
- uint8_t unused_1[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/****************************
- * hwrm_queue_dscp2pri_qcfg *
- ****************************/
+/*****************
+ * hwrm_vnic_cfg *
+ *****************/
-/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
-struct hwrm_queue_dscp2pri_qcfg_input {
+/* hwrm_vnic_cfg_input (size:384b/48B) */
+struct hwrm_vnic_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint32_t flags;
/*
- * This is the host address where the 24-bits DSCP-MASK-PRI
- * tuple(s) will be copied to.
+ * When this bit is '1', the VNIC is requested to
+ * be the default VNIC for the function.
*/
- uint64_t dest_data_addr;
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
+ UINT32_C(0x1)
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
+ * When this bit is '1', the VNIC is being configured to
+ * strip VLAN in the RX path.
+ * If set to '0', then VLAN stripping is disabled on
+ * this VNIC.
*/
- uint8_t port_id;
- uint8_t unused_0;
- /* Size of the buffer pointed to by dest_data_addr. */
- uint16_t dest_data_buffer_size;
- uint8_t unused_1[4];
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', the VNIC is being configured to
+ * buffer receive packets in the hardware until the host
+ * posts new receive buffers.
+ * If set to '0', then bd_stall is being configured to be
+ * disabled on this VNIC.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the VNIC is being configured to
+ * receive both RoCE and non-RoCE traffic.
+ * If set to '0', then this VNIC is not configured to be
+ * operating in dual VNIC mode.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ UINT32_C(0x8)
+ /*
+ * When this flag is set to '1', the VNIC is requested to
+ * be configured to receive only RoCE traffic.
+ * If this flag is set to '0', then this flag shall be
+ * ignored by the HWRM.
+ * If roce_dual_vnic_mode flag is set to '1'
+ * or roce_mirroring_capable_vnic_mode flag to 1,
+ * then the HWRM client shall not set this flag to '1'.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ UINT32_C(0x10)
+ /*
+ * When a VNIC uses one destination ring group for certain
+ * application (e.g. Receive Flow Steering) where
+ * exact match is used to direct packets to a VNIC with one
+ * destination ring group only, there is no need to configure
+ * RSS indirection table for that VNIC as only one destination
+ * ring group is used.
+ *
+ * This flag is used to enable a mode where
+ * RSS is enabled in the VNIC using a RSS context
+ * for computing RSS hash but the RSS indirection table is
+ * not configured using hwrm_vnic_rss_cfg.
+ *
+ * If this mode is enabled, then the driver should not program
+ * RSS indirection table for the RSS context that is used for
+ * computing RSS hash only.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the VNIC is being configured to
+ * receive both RoCE and non-RoCE traffic, but forward only the
+ * RoCE traffic further. Also, RoCE traffic can be mirrored to
+ * L2 driver.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ UINT32_C(0x40)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the dflt_ring_grp field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the rss_rule field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the cos_rule field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the lb_rule field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the mru field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the default_rx_ring_id field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the default_cmpl_ring_id field to be
+ * configured.
+ */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the queue_id field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
+ UINT32_C(0x80)
+ /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
+ UINT32_C(0x100)
+ /* Logical vnic ID */
+ uint16_t vnic_id;
+ /*
+ * Default Completion ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules and if
+ * there is no COS rule.
+ */
+ uint16_t dflt_ring_grp;
+ /*
+ * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
+ * there is no RSS rule.
+ */
+ uint16_t rss_rule;
+ /*
+ * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
+ * there is no COS rule.
+ */
+ uint16_t cos_rule;
+ /*
+ * RSS ID for load balancing rule/table structure.
+ * 0xFF... (All Fs) if there is no LB rule.
+ */
+ uint16_t lb_rule;
+ /*
+ * The maximum receive unit of the vnic.
+ * Each vnic is associated with a function.
+ * The vnic mru value overwrites the mru setting of the
+ * associated function.
+ * The HWRM shall make sure that vnic mru does not exceed
+ * the mru of the port the function is associated with.
+ */
+ uint16_t mru;
+ /*
+ * Default Rx ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules.
+ * The aggregation ring associated with the Rx ring is
+ * implied based on the Rx ring specified when the
+ * aggregation ring was allocated.
+ */
+ uint16_t default_rx_ring_id;
+ /*
+ * Default completion ring for the VNIC. This ring will
+ * be chosen if packet does not match any RSS rules.
+ */
+ uint16_t default_cmpl_ring_id;
+ /*
+ * When specified, only incoming packets classified to the specified CoS
+ * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
+ * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
+ * ntuple filters with VNIC destination specified are invalid since they
+ * conflict with the CoS to VNIC steering rules in this mode.
+ *
+ * If this field is not specified, packet to VNIC steering will be
+ * subject to the standard L2 filter rules and any additional ntuple
+ * filter rules with destination VNIC specified.
+ */
+ uint16_t queue_id;
+ /*
+ * If the device supports the RX V2 and RX TPA start V2 completion
+ * records as indicated by the HWRM_VNIC_QCAPS command, this field is
+ * used to specify the two RX checksum modes supported by these
+ * completion records.
+ */
+ uint8_t rx_csum_v2_mode;
+ /*
+ * When configured with this checksum mode, the number of header
+ * groups in the delivered packet with a valid IP checksum and
+ * the number of header groups in the delivered packet with a valid
+ * L4 checksum are reported. Valid checksums are counted from the
+ * outermost header group to the innermost header group, stopping at
+ * the first error. This is the default checksum mode supported if
+ * the driver doesn't explicitly configure the RX checksum mode.
+ */
+ #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
+ /*
+ * When configured with this checksum mode, the checksum status is
+ * reported using 'all ok' mode. In the RX completion record, one
+ * bit indicates if the IP checksum is valid for all the parsed
+ * header groups with an IP checksum. Another bit indicates if the
+ * L4 checksum is valid for all the parsed header groups with an L4
+ * checksum. The number of header groups that were parsed by the
+ * chip and passed in the delivered packet is also reported.
+ */
+ #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
+ /*
+ * Any rx_csum_v2_mode value larger than or equal to this is not
+ * valid
+ */
+ #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
+ #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
+ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
+ uint8_t unused0[5];
} __rte_packed;
-/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
-struct hwrm_queue_dscp2pri_qcfg_output {
+/* hwrm_vnic_cfg_output (size:128b/16B) */
+struct hwrm_vnic_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
- * by the dest_data_addr.
- */
- uint16_t entry_cnt;
- /*
- * This is the default PRI which un-initialized DSCP values are
- * mapped to.
- */
- uint8_t default_pri;
- uint8_t unused_0[4];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/***************************
- * hwrm_queue_dscp2pri_cfg *
- ***************************/
+/******************
+ * hwrm_vnic_qcfg *
+ ******************/
-/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
-struct hwrm_queue_dscp2pri_cfg_input {
+/* hwrm_vnic_qcfg_input (size:256b/32B) */
+struct hwrm_vnic_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * This is the host address where the 24-bits DSCP-MASK-PRI tuple
- * will be copied from.
- */
- uint64_t src_data_addr;
- uint32_t flags;
- /* use_hw_default_pri is 1 b */
- #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
- UINT32_C(0x1)
uint32_t enables;
/*
- * This bit must be '1' for the default_pri field to be
+ * This bit must be '1' for the vf_id_valid field to be
* configured.
*/
- #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
- UINT32_C(0x1)
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure pri2cos mapping on this port.
- */
- uint8_t port_id;
- /*
- * This is the default PRI which un-initialized DSCP values will be
- * mapped to.
- */
- uint8_t default_pri;
- /*
- * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
- * to by src_data_addr.
- */
- uint16_t entry_cnt;
- uint8_t unused_0[4];
+ #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /* Logical vnic ID */
+ uint32_t vnic_id;
+ /* ID of Virtual Function whose VNIC resource is being queried. */
+ uint16_t vf_id;
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
-struct hwrm_queue_dscp2pri_cfg_output {
+/* hwrm_vnic_qcfg_output (size:256b/32B) */
+struct hwrm_vnic_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* Default Completion ring for the VNIC. */
+ uint16_t dflt_ring_grp;
+ /*
+ * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
+ * there is no RSS rule.
+ */
+ uint16_t rss_rule;
+ /*
+ * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
+ * there is no COS rule.
+ */
+ uint16_t cos_rule;
+ /*
+ * RSS ID for load balancing rule/table structure.
+ * 0xFF... (All Fs) if there is no LB rule.
+ */
+ uint16_t lb_rule;
+ /* The maximum receive unit of the vnic. */
+ uint16_t mru;
+ uint8_t unused_0[2];
+ uint32_t flags;
+ /*
+ * When this bit is '1', the VNIC is the default VNIC for
+ * the function.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * strip VLAN in the RX path.
+ * If set to '0', then VLAN stripping is disabled on
+ * this VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * buffer receive packets in the hardware until the host
+ * posts new receive buffers.
+ * If set to '0', then bd_stall is disabled on
+ * this VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * receive both RoCE and non-RoCE traffic.
+ * If set to '0', then this VNIC is not configured to
+ * operate in dual VNIC mode.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ UINT32_C(0x8)
+ /*
+ * When this flag is set to '1', the VNIC is configured to
+ * receive only RoCE traffic.
+ * When this flag is set to '0', the VNIC is not configured
+ * to receive only RoCE traffic.
+ * If roce_dual_vnic_mode flag and this flag both are set
+ * to '1', then it is an invalid configuration of the
+ * VNIC. The HWRM should not allow that type of
+ * mis-configuration by HWRM clients.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ UINT32_C(0x10)
+ /*
+ * When a VNIC uses one destination ring group for certain
+ * application (e.g. Receive Flow Steering) where
+ * exact match is used to direct packets to a VNIC with one
+ * destination ring group only, there is no need to configure
+ * RSS indirection table for that VNIC as only one destination
+ * ring group is used.
+ *
+ * When this bit is set to '1', then the VNIC is enabled in a
+ * mode where RSS is enabled in the VNIC using a RSS context
+ * for computing RSS hash but the RSS indirection table is
+ * not configured.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the VNIC is configured to
+ * receive both RoCE and non-RoCE traffic, but forward only
+ * RoCE traffic further. Also RoCE traffic can be mirrored to
+ * L2 driver.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '0', VNIC is in normal operation state.
+ * When this bit is '1', VNIC drops all the received packets.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
+ UINT32_C(0x80)
+ /*
+ * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
+ * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
+ * queue association.
+ */
+ uint16_t queue_id;
+ /*
+ * If the device supports the RX V2 and RX TPA start V2 completion
+ * records as indicated by the HWRM_VNIC_QCAPS command, this field is
+ * used to specify the current RX checksum mode configured for all the
+ * RX rings of a VNIC.
+ */
+ uint8_t rx_csum_v2_mode;
+ /*
+ * This value indicates that the VNIC is configured to use the
+ * default RX checksum mode for all the rings associated with this
+ * VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
+ /*
+ * This value indicates that the VNIC is configured to use the RX
+ * checksum ‘all_ok’ mode for all the rings associated with this
+ * VNIC.
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
+ /*
+ * Any rx_csum_v2_mode value larger than or equal to this is not
+ * valid
+ */
+ #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
+ #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
+ HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
+ uint8_t unused_1[4];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/*************************
- * hwrm_queue_mpls_qcaps *
- *************************/
+/*******************
+ * hwrm_vnic_qcaps *
+ *******************/
-/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
-struct hwrm_queue_mpls_qcaps_input {
+/* hwrm_vnic_qcaps_input (size:192b/24B) */
+struct hwrm_vnic_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure MPLS TC(EXP) to pri mapping on this port.
- */
- uint8_t port_id;
- uint8_t unused_0[7];
+ uint32_t enables;
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
-struct hwrm_queue_mpls_qcaps_output {
+/* hwrm_vnic_qcaps_output (size:192b/24B) */
+struct hwrm_vnic_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* The maximum receive unit that is settable on a vnic. */
+ uint16_t mru;
+ uint8_t unused_0[2];
+ uint32_t flags;
+ /* Unused. */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', the capability of stripping VLAN in
+ * the RX path is supported on VNIC(s).
+ * If set to '0', then VLAN stripping capability is
+ * not supported on VNIC(s).
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', the capability to buffer receive
+ * packets in the hardware until the host posts new receive buffers
+ * is supported on VNIC(s).
+ * If set to '0', then bd_stall capability is not supported
+ * on VNIC(s).
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', the capability to
+ * receive both RoCE and non-RoCE traffic on VNIC(s) is
+ * supported.
+ * If set to '0', then the capability to receive
+ * both RoCE and non-RoCE traffic on VNIC(s) is
+ * not supported.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
+ UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', the capability to configure
+ * a VNIC to receive only RoCE traffic is supported.
+ * When this flag is set to '0', the VNIC capability to
+ * configure to receive only RoCE traffic is not supported.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
+ UINT32_C(0x10)
+ /*
+ * When this bit is set to '1', then the capability to enable
+ * a VNIC in a mode where RSS context without configuring
+ * RSS indirection table is supported (for RSS hash computation).
+ * When this bit is set to '0', then a VNIC can not be configured
+ * with a mode to enable RSS context without configuring RSS
+ * indirection table.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the capability to
+ * mirror the RoCE traffic is supported.
+ * If set to '0', then the capability to mirror the
+ * RoCE traffic is not supported.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', the outermost RSS hashing capability
+ * is supported. If set to '0', then the outermost RSS hashing
+ * capability is not supported.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', it indicates that firmware supports the
+ * ability to steer incoming packets from one CoS queue to one
+ * VNIC. This optional feature can then be enabled
+ * using HWRM_VNIC_CFG on any VNIC. This feature is only
+ * available when NVM option “enable_cos_classification” is set
+ * to 1. If set to '0', firmware does not support this feature.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', it indicates that HW and firmware supports
+ * the use of RX V2 and RX TPA start V2 completion records for all
+ * the RX rings of a VNIC. Once set, this feature is mandatory to
+ * be used for the RX rings of the VNIC. Additionally, two new RX
+ * checksum features supported by these completion records can be
+ * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
+ * HW and the firmware does not support this feature.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', it indicates that HW and firmware support
+ * vnic state change. Host drivers can change the vnic state using
+ * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
+ * support this feature.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
+ UINT32_C(0x400)
+ /*
+ * When this bit is '1', it indicates that firmware supports
+ * virtio-net functions default VNIC allocation using
+ * HWRM_VNIC_ALLOC.
+ * This capability is available only on Proxy VEE PF. If set to '0',
+ * firmware does not support this feature.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
+ UINT32_C(0x800)
+ /*
+ * When this bit is set '1', then the capability to configure the
+ * metadata format in the RX completion is supported for the VNIC.
+ * When this bit is set to '0', then the capability to configure
+ * the metadata format in the RX completion is not supported for
+ * the VNIC.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
+ UINT32_C(0x1000)
+ /*
+ * When this bit is set '1', it indicates that firmware returns
+ * INVALID_PARAM error, if host drivers choose invalid hash type
+ * bit combinations in vnic_rss_cfg.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \
+ UINT32_C(0x2000)
+ /*
+ * When this bit is set '1', it indicates that firmware supports
+ * the hash_type include and exclude flags in hwrm_vnic_rss_cfg.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \
+ UINT32_C(0x4000)
+ /*
+ * When this bit is '1', it indicates that HW is capable
+ * of calculating the RSS hash using Toeplitz algorithm.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP \
+ UINT32_C(0x8000)
+ /*
+ * When this bit is '1', it indicates that HW is capable
+ * of calculating the RSS hash using XOR algorithm.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_XOR_CAP \
+ UINT32_C(0x10000)
+ /*
+ * When this bit is '1', it indicates that HW is capable
+ * of using checksum algorithm.
+ * In this mode, RSS hash is calculated with Toeplitz and reported
+ * in the RX completion. However, the ring selection algorithm is
+ * based on the checksum. In this mode, only the innermost L3/L4
+ * packet checksums are used. So this hash function mode will not
+ * be exposed/valid when the outer RSS mode is enabled.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP \
+ UINT32_C(0x20000)
/*
- * Bitmask indicating which queues can be configured by the
- * hwrm_queue_mplstc2pri_cfg command.
- *
- * Each bit represents a specific pri where bit 0 represents
- * pri 0 and bit 7 represents pri 7.
- * # A value of 0 indicates that the pri is not configurable
- * by the hwrm_queue_mplstc2pri_cfg command.
- * # A value of 1 indicates that the pri is configurable.
- * # A hwrm_queue_mplstc2pri_cfg command shall return error when
- * trying to configure a pri that is not configurable.
+ * When this bit is '1' HW supports hash calculation
+ * based on IPV6 flow labels.
*/
- uint8_t queue_mplstc2pri_cfg_allowed;
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \
+ UINT32_C(0x40000)
/*
- * This is the default PRI which un-initialized MPLS values will be
- * mapped to.
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
*/
- uint8_t hw_default_pri;
- uint8_t unused_0[5];
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/******************************
- * hwrm_queue_mplstc2pri_qcfg *
- ******************************/
+/*********************
+ * hwrm_vnic_tpa_cfg *
+ *********************/
-/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
-struct hwrm_queue_mplstc2pri_qcfg_input {
+/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
+struct hwrm_vnic_tpa_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint32_t flags;
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure MPLS TC(EXP) to pri mapping on this port.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) of
+ * non-tunneled TCP packets.
*/
- uint8_t port_id;
- uint8_t unused_0[7];
-} __rte_packed;
-
-/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
-struct hwrm_queue_mplstc2pri_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
+ UINT32_C(0x1)
/*
- * pri assigned to MPLS TC(EXP) 0. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 0.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) of
+ * tunneled TCP packets.
*/
- uint8_t tc0_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
+ UINT32_C(0x2)
/*
- * pri assigned to MPLS TC(EXP) 1. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 1.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) according
+ * to Windows Receive Segment Coalescing (RSC) rules.
*/
- uint8_t tc1_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
+ UINT32_C(0x4)
/*
- * pri assigned to MPLS TC(EXP) 2. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 2.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) according
+ * to Linux Generic Receive Offload (GRO) rules.
*/
- uint8_t tc2_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
+ UINT32_C(0x8)
/*
- * pri assigned to MPLS TC(EXP) 3. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 3.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for TCP
+ * packets with IP ECN set to non-zero.
*/
- uint8_t tc3_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
+ UINT32_C(0x10)
/*
- * pri assigned to MPLS TC(EXP) 4. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 4.
+ * When this bit is '1', the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * GRE tunneled TCP packets only if all packets have the
+ * same GRE sequence.
*/
- uint8_t tc4_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
+ UINT32_C(0x20)
/*
- * pri assigned to MPLS TC(EXP) 5. This value can only be changed
- * before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 5.
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * TCP/IPv4 packets with consecutively increasing IPIDs.
+ * In other words, the last packet that is being
+ * aggregated to an already existing aggregation context
+ * shall have IPID 1 more than the IPID of the last packet
+ * that was aggregated in that aggregation context.
*/
- uint8_t tc5_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
+ UINT32_C(0x40)
/*
- * pri assigned to MPLS TC(EXP) 6. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 6.
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall be configured to
+ * perform transparent packet aggregation (TPA) for
+ * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
+ * value.
*/
- uint8_t tc6_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
+ UINT32_C(0x80)
/*
- * pri assigned to MPLS TC(EXP) 7. This value can only
- * be changed before traffic has started.
- * A value of 0xff indicates that no pri is assigned to the
- * MPLS TC(EXP) 7.
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
*/
- uint8_t tc7_pri_queue_id;
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the max_agg_segs field to be
+ * configured.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the max_aggs field to be
+ * configured.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the max_agg_timer field to be
+ * configured.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
+ /* deprecated bit. Do not use!!! */
+ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
+ /* Logical vnic ID */
+ uint16_t vnic_id;
+ /*
+ * This is the maximum number of TCP segments that can
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
+ */
+ uint16_t max_agg_segs;
+ /* 1 segment */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
+ /* 2 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
+ /* 4 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
+ /* 8 segments */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
+ /* Any segment size larger than this is not valid */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
+ HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
+ /*
+ * This is the maximum number of aggregations this VNIC is
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
+ */
+ uint16_t max_aggs;
+ /* 1 aggregation */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
+ /* 2 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
+ /* 4 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
+ /* 8 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
+ /* 16 aggregations */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
+ /* Any aggregation size larger than this is not valid */
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
+ #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
+ HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
+ uint8_t unused_0[2];
+ /*
+ * This is the maximum amount of time allowed for
+ * an aggregation context to complete after it was initiated.
+ */
+ uint32_t max_agg_timer;
+ /*
+ * This is the minimum amount of payload length required to
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
+ */
+ uint32_t min_agg_len;
+} __rte_packed;
+
+/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
+struct hwrm_vnic_tpa_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/*****************************
- * hwrm_queue_mplstc2pri_cfg *
- *****************************/
+/*********************
+ * hwrm_vnic_rss_cfg *
+ *********************/
-/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
-struct hwrm_queue_mplstc2pri_cfg_input {
+/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
+struct hwrm_vnic_rss_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ uint32_t hash_type;
/*
- * This bit must be '1' for the mplstc0_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
- UINT32_C(0x1)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
/*
- * This bit must be '1' for the mplstc1_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
- UINT32_C(0x2)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
/*
- * This bit must be '1' for the mplstc2_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
- UINT32_C(0x4)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
/*
- * This bit must be '1' for the mplstc3_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv6 addresses of IPv6
+ * packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
- UINT32_C(0x8)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
/*
- * This bit must be '1' for the mplstc4_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
- UINT32_C(0x10)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
/*
- * This bit must be '1' for the mplstc5_pri_queue_id field to be
- * configured.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
- UINT32_C(0x20)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ /* VNIC ID of VNIC associated with RSS table being configured. */
+ uint16_t vnic_id;
/*
- * This bit must be '1' for the mplstc6_pri_queue_id field to be
- * configured.
+ * Specifies which VNIC ring table pair to configure.
+ * Valid values range from 0 to 7.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
- UINT32_C(0x40)
+ uint8_t ring_table_pair_index;
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
/*
- * This bit must be '1' for the mplstc7_pri_queue_id field to be
- * configured.
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
*/
- #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
- UINT32_C(0x80)
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
+ UINT32_C(0x1)
/*
- * Port ID of port for which the table is being configured.
- * The HWRM needs to check whether this function is allowed
- * to configure MPLS TC(EXP)to pri mapping on this port.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- uint8_t port_id;
- uint8_t unused_0[3];
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
+ UINT32_C(0x2)
/*
- * pri assigned to MPLS TC(EXP) 0. This value can only
- * be changed before traffic has started.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- uint8_t tc0_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
+ UINT32_C(0x4)
/*
- * pri assigned to MPLS TC(EXP) 1. This value can only
- * be changed before traffic has started.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
*/
- uint8_t tc1_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
+ UINT32_C(0x8)
/*
- * pri assigned to MPLS TC(EXP) 2 This value can only
- * be changed before traffic has started.
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- uint8_t tc2_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
+ UINT32_C(0x10)
+ /* This is the address for rss ring group table */
+ uint64_t ring_grp_tbl_addr;
+ /* This is the address for rss hash key table */
+ uint64_t hash_key_tbl_addr;
+ /* Index to the rss indirection table. */
+ uint16_t rss_ctx_idx;
+ uint8_t flags;
/*
- * pri assigned to MPLS TC(EXP) 3. This value can only
- * be changed before traffic has started.
- */
- uint8_t tc3_pri_queue_id;
+ * When this bit is '1', it indicates that the hash_type field is
+ * interpreted as a change relative the current configuration. Each
+ * '1' bit in hash_type represents a header to add to the current
+ * hash. Zeroes designate the hash_type state bits that should remain
+ * unchanged, if possible. If this constraint on the existing state
+ * cannot be satisfied, then the implementation should preference
+ * adding other headers so as to honor the request to add the
+ * specified headers. It is an error to set this flag concurrently
+ * with hash_type_exclude.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the hash_type field is
+ * interpreted as a change relative the current configuration. Each
+ * '1' bit in hash_type represents a header to remove from the
+ * current hash. Zeroes designate the hash_type state bits that
+ * should remain unchanged, if possible. If this constraint on the
+ * existing state cannot be satisfied, then the implementation should
+ * preference removing other headers so as to honor the request to
+ * remove the specified headers. It is an error to set this flag
+ * concurrently with hash_type_include.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \
+ UINT32_C(0x2)
/*
- * pri assigned to MPLS TC(EXP) 4. This value can only
- * be changed before traffic has started.
+ * Used to choose the RSS hash algorithm based on which HW
+ * can select the destination ring
*/
- uint8_t tc4_pri_queue_id;
+ uint8_t rss_hash_function;
/*
- * pri assigned to MPLS TC(EXP) 5. This value can only
- * be changed before traffic has started.
+ * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
+ * headers and uses the hash to select the ring.
*/
- uint8_t tc5_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_TOEPLITZ \
+ UINT32_C(0x0)
/*
- * pri assigned to MPLS TC(EXP) 6. This value can only
- * be changed before traffic has started.
+ * NIC calculates the RSS hash using the XOR algorithm on L3/L4
+ * headers and uses the hash to select the ring.
*/
- uint8_t tc6_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_XOR \
+ UINT32_C(0x1)
/*
- * pri assigned to MPLS TC(EXP) 7. This value can only
- * be changed before traffic has started.
+ * In this mode, RSS hash is calculated with Toeplitz and reported
+ * in the RX completion. However, the ring selection algorithm is
+ * based on the checksum. In this mode, only the innermost L3/L4
+ * packet checksums are used. So this hash function mode will not
+ * be exposed/valid when the outer RSS mode is enabled.
*/
- uint8_t tc7_pri_queue_id;
+ #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM \
+ UINT32_C(0x2)
+ #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_LAST \
+ HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
-struct hwrm_queue_mplstc2pri_cfg_output {
+/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
+struct hwrm_vnic_rss_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t valid;
} __rte_packed;
-/*******************
- * hwrm_vnic_alloc *
- *******************/
+/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
+struct hwrm_vnic_rss_cfg_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /*
+ * Unable to change global RSS mode to outer due to all active
+ * interfaces are not ready to support outer RSS hashing.
+ */
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
+ UINT32_C(0x1)
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
+ HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/**********************
+ * hwrm_vnic_rss_qcfg *
+ **********************/
-/* hwrm_vnic_alloc_input (size:192b/24B) */
-struct hwrm_vnic_alloc_input {
+/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
+struct hwrm_vnic_rss_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /*
- * When this bit is '1', this VNIC is requested to
- * be the default VNIC for this function.
- */
- #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
- uint8_t unused_0[4];
+ /* Index to the rss indirection table. */
+ uint16_t rss_ctx_idx;
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_vnic_alloc_output (size:128b/16B) */
-struct hwrm_vnic_alloc_output {
+/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
+struct hwrm_vnic_rss_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[3];
+ uint32_t hash_type;
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv4 addresses of IPv4
+ * packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of TCP/IPv4 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv4 addresses and
+ * source/destination ports of UDP/IPv4 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source and destination IPv6 addresses of IPv6
+ * packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of TCP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source/destination IPv6 addresses and
+ * source/destination ports of UDP/IPv6 packets.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ uint8_t unused_0[4];
+ /* This is the value of rss hash key */
+ uint32_t hash_key[10];
+ /* Flags to specify different RSS hash modes. */
+ uint8_t hash_mode_flags;
+ /*
+ * When this bit is '1', it indicates using current RSS
+ * hash mode setting configured in the device.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
+ * l4.src, l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
+ * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
+ * packets, the RSS hash is computed over the normal
+ * src/dest l3 and src/dest l4 headers.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates requesting support of
+ * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
+ * tunnel packets. For none-tunnel packets, the RSS hash is
+ * computed over the normal src/dest l3 headers.
*/
- uint8_t valid;
-} __rte_packed;
-
-/******************
- * hwrm_vnic_free *
- ******************/
-
-
-/* hwrm_vnic_free_input (size:192b/24B) */
-struct hwrm_vnic_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
+ UINT32_C(0x10)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Used to choose the RSS hash algorithm based on which HW
+ * can select the destination ring
*/
- uint16_t cmpl_ring;
+ uint8_t rss_hash_function;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4
+ * headers and uses the hash to select the ring.
*/
- uint16_t seq_id;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_TOEPLITZ \
+ UINT32_C(0x0)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * NIC calculates the RSS hash using the XOR algorithm on L3/L4
+ * headers and uses the hash to select the ring.
*/
- uint16_t target_id;
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_XOR \
+ UINT32_C(0x1)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * In this mode, RSS hash is calculated with Toeplitz and reported
+ * in the RX completion. However, the ring selection algorithm is
+ * based on the checksum. In this mode, only the innermost L3/L4
+ * packet checksums are used. So this hash function mode will not
+ * be exposed/valid when the outer RSS mode is enabled.
*/
- uint64_t resp_addr;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[4];
-} __rte_packed;
-
-/* hwrm_vnic_free_output (size:128b/16B) */
-struct hwrm_vnic_free_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM \
+ UINT32_C(0x2)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_LAST \
+ HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*****************
- * hwrm_vnic_cfg *
- *****************/
+/**************************
+ * hwrm_vnic_plcmodes_cfg *
+ **************************/
-/* hwrm_vnic_cfg_input (size:384b/48B) */
-struct hwrm_vnic_cfg_input {
+/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
+struct hwrm_vnic_plcmodes_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint64_t resp_addr;
uint32_t flags;
/*
- * When this bit is '1', the VNIC is requested to
- * be the default VNIC for the function.
+ * When this bit is '1', the VNIC shall be configured to
+ * use regular placement algorithm.
+ * By default, the regular placement algorithm shall be
+ * enabled on the VNIC.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
UINT32_C(0x1)
/*
- * When this bit is '1', the VNIC is being configured to
- * strip VLAN in the RX path.
- * If set to '0', then VLAN stripping is disabled on
- * this VNIC.
+ * When this bit is '1', the VNIC shall be configured
+ * use the jumbo placement algorithm.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
UINT32_C(0x2)
/*
- * When this bit is '1', the VNIC is being configured to
- * buffer receive packets in the hardware until the host
- * posts new receive buffers.
- * If set to '0', then bd_stall is being configured to be
- * disabled on this VNIC.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for IPv4 packets according
+ * to the following rules:
+ * # If the packet is identified as TCP/IPv4, then the
+ * packet is split at the beginning of the TCP payload.
+ * # If the packet is identified as UDP/IPv4, then the
+ * packet is split at the beginning of UDP payload.
+ * # If the packet is identified as non-TCP and non-UDP
+ * IPv4 packet, then the packet is split at the beginning
+ * of the upper layer protocol header carried in the IPv4
+ * packet.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
UINT32_C(0x4)
/*
- * When this bit is '1', the VNIC is being configured to
- * receive both RoCE and non-RoCE traffic.
- * If set to '0', then this VNIC is not configured to be
- * operating in dual VNIC mode.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for IPv6 packets according
+ * to the following rules:
+ * # If the packet is identified as TCP/IPv6, then the
+ * packet is split at the beginning of the TCP payload.
+ * # If the packet is identified as UDP/IPv6, then the
+ * packet is split at the beginning of UDP payload.
+ * # If the packet is identified as non-TCP and non-UDP
+ * IPv6 packet, then the packet is split at the beginning
+ * of the upper layer protocol header carried in the IPv6
+ * packet.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
UINT32_C(0x8)
/*
- * When this flag is set to '1', the VNIC is requested to
- * be configured to receive only RoCE traffic.
- * If this flag is set to '0', then this flag shall be
- * ignored by the HWRM.
- * If roce_dual_vnic_mode flag is set to '1'
- * or roce_mirroring_capable_vnic_mode flag to 1,
- * then the HWRM client shall not set this flag to '1'.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for FCoE packets at the
+ * beginning of FC payload.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
UINT32_C(0x10)
/*
- * When a VNIC uses one destination ring group for certain
- * application (e.g. Receive Flow Steering) where
- * exact match is used to direct packets to a VNIC with one
- * destination ring group only, there is no need to configure
- * RSS indirection table for that VNIC as only one destination
- * ring group is used.
- *
- * This flag is used to enable a mode where
- * RSS is enabled in the VNIC using a RSS context
- * for computing RSS hash but the RSS indirection table is
- * not configured using hwrm_vnic_rss_cfg.
- *
- * If this mode is enabled, then the driver should not program
- * RSS indirection table for the RSS context that is used for
- * computing RSS hash only.
+ * When this bit is '1', the VNIC shall be configured
+ * to enable Header-Data split for RoCE packets at the
+ * beginning of RoCE payload (after BTH/GRH headers).
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
UINT32_C(0x20)
/*
- * When this bit is '1', the VNIC is being configured to
- * receive both RoCE and non-RoCE traffic, but forward only the
- * RoCE traffic further. Also, RoCE traffic can be mirrored to
- * L2 driver.
+ * When this bit is '1', the VNIC shall be configured use the virtio
+ * placement algorithm. This feature can only be configured when
+ * proxy mode is supported on the function.
*/
- #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
UINT32_C(0x40)
uint32_t enables;
/*
- * This bit must be '1' for the dflt_ring_grp field to be
+ * This bit must be '1' for the jumbo_thresh_valid field to be
* configured.
*/
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
UINT32_C(0x1)
/*
- * This bit must be '1' for the rss_rule field to be
+ * This bit must be '1' for the hds_offset_valid field to be
* configured.
*/
- #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
UINT32_C(0x2)
/*
- * This bit must be '1' for the cos_rule field to be
+ * This bit must be '1' for the hds_threshold_valid field to be
* configured.
*/
- #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
UINT32_C(0x4)
/*
- * This bit must be '1' for the lb_rule field to be
+ * This bit must be '1' for the max_bds_valid field to be
* configured.
*/
- #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
+ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
UINT32_C(0x8)
- /*
- * This bit must be '1' for the mru field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
- UINT32_C(0x10)
- /*
- * This bit must be '1' for the default_rx_ring_id field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
- UINT32_C(0x20)
- /*
- * This bit must be '1' for the default_cmpl_ring_id field to be
- * configured.
- */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
- UINT32_C(0x40)
- /* This bit must be '1' for the queue_id field to be configured. */
- #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
- UINT32_C(0x80)
/* Logical vnic ID */
- uint16_t vnic_id;
- /*
- * Default Completion ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules and if
- * there is no COS rule.
- */
- uint16_t dflt_ring_grp;
- /*
- * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
- * there is no RSS rule.
- */
- uint16_t rss_rule;
- /*
- * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
- * there is no COS rule.
- */
- uint16_t cos_rule;
- /*
- * RSS ID for load balancing rule/table structure.
- * 0xFF... (All Fs) if there is no LB rule.
- */
- uint16_t lb_rule;
+ uint32_t vnic_id;
/*
- * The maximum receive unit of the vnic.
- * Each vnic is associated with a function.
- * The vnic mru value overwrites the mru setting of the
- * associated function.
- * The HWRM shall make sure that vnic mru does not exceed
- * the mru of the port the function is associated with.
+ * When jumbo placement algorithm is enabled, this value
+ * is used to determine the threshold for jumbo placement.
+ * Packets with length larger than this value will be
+ * placed according to the jumbo placement algorithm.
*/
- uint16_t mru;
+ uint16_t jumbo_thresh;
/*
- * Default Rx ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules.
- * The aggregation ring associated with the Rx ring is
- * implied based on the Rx ring specified when the
- * aggregation ring was allocated.
+ * This value is used to determine the offset into
+ * packet buffer where the split data (payload) will be
+ * placed according to one of HDS placement algorithm.
+ *
+ * The lengths of packet buffers provided for split data
+ * shall be larger than this value.
*/
- uint16_t default_rx_ring_id;
+ uint16_t hds_offset;
/*
- * Default completion ring for the VNIC. This ring will
- * be chosen if packet does not match any RSS rules.
+ * When one of the HDS placement algorithm is enabled, this
+ * value is used to determine the threshold for HDS
+ * placement.
+ * Packets with length larger than this value will be
+ * placed according to the HDS placement algorithm.
+ * This value shall be in multiple of 4 bytes.
*/
- uint16_t default_cmpl_ring_id;
+ uint16_t hds_threshold;
/*
- * When specified, only incoming packets classified to the specified CoS
- * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
- * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
- * ntuple filters with VNIC destination specified are invalid since they
- * conflict with the the CoS to VNIC steering rules in this mode.
- *
- * If this field is not specified, packet to VNIC steering will be
- * subject to the standard L2 filter rules and any additional ntuple
- * filter rules with destination VNIC specified.
- */
- uint16_t queue_id;
- uint8_t unused0[6];
+ * When virtio placement algorithm is enabled, this
+ * value is used to determine the maximum number of BDs
+ * that can be used to place an Rx Packet.
+ * If an incoming packet does not fit in the buffers described
+ * by the max BDs, the packet will be dropped and an error
+ * will be reported in the completion. Valid values for this
+ * field are between 1 and 8. If the VNIC uses header-data-
+ * separation and/or TPA with buffer spanning enabled, valid
+ * values for this field are between 2 and 8.
+ * This feature can only be configured when proxy mode is
+ * supported on the function.
+ */
+ uint16_t max_bds;
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_vnic_cfg_output (size:128b/16B) */
-struct hwrm_vnic_cfg_output {
+/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
+struct hwrm_vnic_plcmodes_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/******************
- * hwrm_vnic_qcfg *
- ******************/
+/***************************
+ * hwrm_vnic_plcmodes_qcfg *
+ ***************************/
-/* hwrm_vnic_qcfg_input (size:256b/32B) */
-struct hwrm_vnic_qcfg_input {
+/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
+struct hwrm_vnic_plcmodes_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
- */
- #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
/* Logical vnic ID */
uint32_t vnic_id;
- /* ID of Virtual Function whose VNIC resource is being queried. */
- uint16_t vf_id;
- uint8_t unused_0[6];
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_vnic_qcfg_output (size:256b/32B) */
-struct hwrm_vnic_qcfg_output {
+/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
+struct hwrm_vnic_plcmodes_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Default Completion ring for the VNIC. */
- uint16_t dflt_ring_grp;
- /*
- * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
- * there is no RSS rule.
- */
- uint16_t rss_rule;
- /*
- * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
- * there is no COS rule.
- */
- uint16_t cos_rule;
- /*
- * RSS ID for load balancing rule/table structure.
- * 0xFF... (All Fs) if there is no LB rule.
- */
- uint16_t lb_rule;
- /* The maximum receive unit of the vnic. */
- uint16_t mru;
- uint8_t unused_0[2];
uint32_t flags;
/*
- * When this bit is '1', the VNIC is the default VNIC for
- * the function.
+ * When this bit is '1', the VNIC is configured to
+ * use regular placement algorithm.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
UINT32_C(0x1)
/*
* When this bit is '1', the VNIC is configured to
- * strip VLAN in the RX path.
- * If set to '0', then VLAN stripping is disabled on
- * this VNIC.
+ * use the jumbo placement algorithm.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
UINT32_C(0x2)
/*
- * When this bit is '1', the VNIC is configured to
- * buffer receive packets in the hardware until the host
- * posts new receive buffers.
- * If set to '0', then bd_stall is disabled on
- * this VNIC.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for IPv4 packets.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
UINT32_C(0x4)
/*
- * When this bit is '1', the VNIC is configured to
- * receive both RoCE and non-RoCE traffic.
- * If set to '0', then this VNIC is not configured to
- * operate in dual VNIC mode.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for IPv6 packets.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
UINT32_C(0x8)
/*
- * When this flag is set to '1', the VNIC is configured to
- * receive only RoCE traffic.
- * When this flag is set to '0', the VNIC is not configured
- * to receive only RoCE traffic.
- * If roce_dual_vnic_mode flag and this flag both are set
- * to '1', then it is an invalid configuration of the
- * VNIC. The HWRM should not allow that type of
- * mis-configuration by HWRM clients.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for FCoE packets.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
UINT32_C(0x10)
/*
- * When a VNIC uses one destination ring group for certain
- * application (e.g. Receive Flow Steering) where
- * exact match is used to direct packets to a VNIC with one
- * destination ring group only, there is no need to configure
- * RSS indirection table for that VNIC as only one destination
- * ring group is used.
- *
- * When this bit is set to '1', then the VNIC is enabled in a
- * mode where RSS is enabled in the VNIC using a RSS context
- * for computing RSS hash but the RSS indirection table is
- * not configured.
+ * When this bit is '1', the VNIC is configured
+ * to enable Header-Data split for RoCE packets.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
UINT32_C(0x20)
/*
- * When this bit is '1', the VNIC is configured to
- * receive both RoCE and non-RoCE traffic, but forward only
- * RoCE traffic further. Also RoCE traffic can be mirrored to
- * L2 driver.
+ * When this bit is '1', the VNIC is configured
+ * to be the default VNIC of the requesting function.
*/
- #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
UINT32_C(0x40)
/*
- * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
- * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
- * queue association.
+ * When this bit is '1', the VNIC is configured to use the virtio
+ * placement algorithm. This feature can only be configured when
+ * proxy mode is supported on the function.
*/
- uint16_t queue_id;
- uint8_t unused_1[5];
+ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
+ UINT32_C(0x80)
+ /*
+ * When jumbo placement algorithm is enabled, this value
+ * is used to determine the threshold for jumbo placement.
+ * Packets with length larger than this value will be
+ * placed according to the jumbo placement algorithm.
+ */
+ uint16_t jumbo_thresh;
+ /*
+ * This value is used to determine the offset into
+ * packet buffer where the split data (payload) will be
+ * placed according to one of HDS placement algorithm.
+ *
+ * The lengths of packet buffers provided for split data
+ * shall be larger than this value.
+ */
+ uint16_t hds_offset;
+ /*
+ * When one of the HDS placement algorithm is enabled, this
+ * value is used to determine the threshold for HDS
+ * placement.
+ * Packets with length larger than this value will be
+ * placed according to the HDS placement algorithm.
+ * This value shall be in multiple of 4 bytes.
+ */
+ uint16_t hds_threshold;
+ /*
+ * When virtio placement algorithm is enabled, this
+ * value is used to determine the maximum number of BDs
+ * that can be used to place an Rx Packet.
+ * If an incoming packet does not fit in the buffers described
+ * by the max BDs, the packet will be dropped and an error
+ * will be reported in the completion. Valid values for this
+ * field are between 1 and 8. If the VNIC uses header-data-
+ * separation and/or TPA with buffer spanning enabled, valid
+ * values for this field are between 2 and 8.
+ * This feature can only be configured when proxy mode is supported
+ * on the function
+ */
+ uint16_t max_bds;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/*******************
- * hwrm_vnic_qcaps *
- *******************/
+/**********************************
+ * hwrm_vnic_rss_cos_lb_ctx_alloc *
+ **********************************/
-/* hwrm_vnic_qcaps_input (size:192b/24B) */
-struct hwrm_vnic_qcaps_input {
+/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_vnic_qcaps_output (size:192b/24B) */
-struct hwrm_vnic_qcaps_output {
+/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The maximum receive unit that is settable on a vnic. */
- uint16_t mru;
- uint8_t unused_0[2];
- uint32_t flags;
- /* Unused. */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
- UINT32_C(0x1)
- /*
- * When this bit is '1', the capability of stripping VLAN in
- * the RX path is supported on VNIC(s).
- * If set to '0', then VLAN stripping capability is
- * not supported on VNIC(s).
- */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
- UINT32_C(0x2)
- /*
- * When this bit is '1', the capability to buffer receive
- * packets in the hardware until the host posts new receive buffers
- * is supported on VNIC(s).
- * If set to '0', then bd_stall capability is not supported
- * on VNIC(s).
- */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
- UINT32_C(0x4)
- /*
- * When this bit is '1', the capability to
- * receive both RoCE and non-RoCE traffic on VNIC(s) is
- * supported.
- * If set to '0', then the capability to receive
- * both RoCE and non-RoCE traffic on VNIC(s) is
- * not supported.
- */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
- UINT32_C(0x8)
- /*
- * When this bit is set to '1', the capability to configure
- * a VNIC to receive only RoCE traffic is supported.
- * When this flag is set to '0', the VNIC capability to
- * configure to receive only RoCE traffic is not supported.
- */
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
- UINT32_C(0x10)
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+ uint8_t unused_0[5];
/*
- * When this bit is set to '1', then the capability to enable
- * a VNIC in a mode where RSS context without configuring
- * RSS indirection table is supported (for RSS hash computation).
- * When this bit is set to '0', then a VNIC can not be configured
- * with a mode to enable RSS context without configuring RSS
- * indirection table.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
- UINT32_C(0x20)
+ uint8_t valid;
+} __rte_packed;
+
+/*********************************
+ * hwrm_vnic_rss_cos_lb_ctx_free *
+ *********************************/
+
+
+/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
+struct hwrm_vnic_rss_cos_lb_ctx_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * When this bit is '1', the capability to
- * mirror the the RoCE traffic is supported.
- * If set to '0', then the capability to mirror the
- * RoCE traffic is not supported.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
- UINT32_C(0x40)
+ uint16_t cmpl_ring;
/*
- * When this bit is '1', the outermost RSS hashing capability
- * is supported. If set to '0', then the outermost RSS hashing
- * capability is not supported.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
- UINT32_C(0x80)
+ uint16_t seq_id;
/*
- * When this bit is '1', it indicates that firmware supports the
- * ability to steer incoming packets from one CoS queue to one
- * VNIC. This optional feature can then be enabled
- * using HWRM_VNIC_CFG on any VNIC. This feature is only
- * available when NVM option “enable_cos_classfication” is set
- * to 1. If set to '0', firmware does not support this feature.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
*/
- #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
- UINT32_C(0x100)
+ uint16_t target_id;
/*
- * This field advertises the maximum concurrent TPA aggregations
- * supported by the VNIC on new devices that support TPA v2.
- * '0' means that TPA v2 is not supported.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t max_aggs_supported;
- uint8_t unused_1[5];
+ uint64_t resp_addr;
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
+struct hwrm_vnic_rss_cos_lb_ctx_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*********************
- * hwrm_vnic_tpa_cfg *
- *********************/
+/*******************
+ * hwrm_ring_alloc *
+ *******************/
-/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
-struct hwrm_vnic_tpa_cfg_input {
+/* hwrm_ring_alloc_input (size:704b/88B) */
+struct hwrm_ring_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) of
- * non-tunneled TCP packets.
- */
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
- UINT32_C(0x1)
+ uint32_t enables;
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) of
- * tunneled TCP packets.
+ * This bit must be '1' for the ring_arb_cfg field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
UINT32_C(0x2)
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) according
- * to Windows Receive Segment Coalescing (RSC) rules.
- */
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
- UINT32_C(0x4)
- /*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) according
- * to Linux Generic Receive Offload (GRO) rules.
+ * This bit must be '1' for the stat_ctx_id_valid field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
UINT32_C(0x8)
/*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for TCP
- * packets with IP ECN set to non-zero.
- */
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
- UINT32_C(0x10)
- /*
- * When this bit is '1', the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * GRE tunneled TCP packets only if all packets have the
- * same GRE sequence.
+ * This bit must be '1' for the max_bw_valid field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
UINT32_C(0x20)
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * TCP/IPv4 packets with consecutively increasing IPIDs.
- * In other words, the last packet that is being
- * aggregated to an already existing aggregation context
- * shall have IPID 1 more than the IPID of the last packet
- * that was aggregated in that aggregation context.
+ * This bit must be '1' for the rx_ring_id field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
UINT32_C(0x40)
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC shall be configured to
- * perform transparent packet aggregation (TPA) for
- * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
- * value.
+ * This bit must be '1' for the nq_ring_id field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
UINT32_C(0x80)
/*
- * When this bit is '1' and the GRO mode is enabled,
- * the VNIC shall DMA payload data using GRO rules.
- * When this bit is '0', the VNIC shall DMA payload data
- * using the more efficient LRO rules of filling all
- * aggregation buffers.
+ * This bit must be '1' for the rx_buf_size field to be
+ * configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
UINT32_C(0x100)
- uint32_t enables;
/*
- * This bit must be '1' for the max_agg_segs field to be
+ * This bit must be '1' for the schq_id field to be
* configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
+ UINT32_C(0x200)
/*
- * This bit must be '1' for the max_aggs field to be
+ * This bit must be '1' for the mpc_chnls_type field to be
* configured.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
+ UINT32_C(0x400)
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ /* RX Aggregation Ring */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
+ /* Notification Queue */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
+ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
/*
- * This bit must be '1' for the max_agg_timer field to be
- * configured.
+ * This field controls the number of packets transmitted before a TX
+ * completion is generated. Non-zero values for the field are only
+ * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion
+ * records capability is supported.
+ */
+ uint8_t cmpl_coal_cnt;
+ /* Generates a legacy TX completion on every packet. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
+ /* Generates a TX coalesced completion for up to 4 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1)
+ /* Generates a TX coalesced completion for up to 8 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2)
+ /* Generates a TX coalesced completion for up to 12 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3)
+ /* Generates a TX coalesced completion for up to 16 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4)
+ /* Generates a TX coalesced completion for up to 24 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5)
+ /* Generates a TX coalesced completion for up to 32 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6)
+ /* Generates a TX coalesced completion for up to 48 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7)
+ /* Generates a TX coalesced completion for up to 64 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8)
+ /* Generates a TX coalesced completion for up to 96 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9)
+ /* Generates a TX coalesced completion for up to 128 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
+ /* Generates a TX coalesced completion for up to 192 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
+ /* Generates a TX coalesced completion for up to 256 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
+ /* Generates a TX coalesced completion for up to 320 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
+ /* Generates a TX coalesced completion for up to 384 TX packets. */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
+ /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
+ #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \
+ HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX
+ /* Ring allocation flags. */
+ uint16_t flags;
+ /*
+ * For Rx rings, the incoming packet data can be placed at either
+ * a 0B or 2B offset from the start of the Rx packet buffer. When
+ * '1', the received packet will be padded with 2B of zeros at the
+ * front of the packet. Note that this flag is only used for
+ * Rx rings and is ignored for all other rings included Rx
+ * Aggregation rings.
*/
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /* deprecated bit. Do not use!!! */
- #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
- /* Logical vnic ID */
- uint16_t vnic_id;
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
/*
- * This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31. On new
- * devices supporting TPA v2, the unit is multiples of 4 and
- * valid values are > 0 and <= 63.
+ * This value is a pointer to the page table for the
+ * Ring.
*/
- uint16_t max_agg_segs;
- /* 1 segment */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
- /* 2 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
- /* 4 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
- /* 8 segments */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
- /* Any segment size larger than this is not valid */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
- HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
+ uint64_t page_tbl_addr;
+ /* First Byte Offset of the first entry in the first page. */
+ uint32_t fbo;
/*
- * This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7. On new devices
- * supporting TPA v2, this is in unit of 1 and must be > 0
- * and <= max_aggs_supported in the hwrm_vnic_qcaps response
- * to enable TPA v2.
+ * Actual page size in 2^page_size. The supported range is increments
+ * in powers of 2 from 16 bytes to 1GB.
+ * - 4 = 16 B
+ * Page size is 16 B.
+ * - 12 = 4 KB
+ * Page size is 4 KB.
+ * - 13 = 8 KB
+ * Page size is 8 KB.
+ * - 16 = 64 KB
+ * Page size is 64 KB.
+ * - 21 = 2 MB
+ * Page size is 2 MB.
+ * - 22 = 4 MB
+ * Page size is 4 MB.
+ * - 30 = 1 GB
+ * Page size is 1 GB.
*/
- uint16_t max_aggs;
- /* 1 aggregation */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
- /* 2 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
- /* 4 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
- /* 8 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
- /* 16 aggregations */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
- /* Any aggregation size larger than this is not valid */
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
- #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
- HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
- uint8_t unused_0[2];
+ uint8_t page_size;
/*
- * This is the maximum amount of time allowed for
- * an aggregation context to complete after it was initiated.
+ * This value indicates the depth of page table.
+ * For this version of the specification, value other than 0 or
+ * 1 shall be considered as an invalid value.
+ * When the page_tbl_depth = 0, then it is treated as a
+ * special case with the following.
+ * 1. FBO and page size fields are not valid.
+ * 2. page_tbl_addr is the physical address of the first
+ * element of the ring.
*/
- uint32_t max_agg_timer;
+ uint8_t page_tbl_depth;
+ /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
+ uint16_t schq_id;
/*
- * This is the minimum amount of payload length required to
- * start an aggregation context. This field is deprecated and
- * should be set to 0. The minimum length is set by firmware
- * and can be queried using hwrm_vnic_tpa_qcfg.
+ * Number of 16B units in the ring. Minimum size for
+ * a ring is 16 16B entries.
*/
- uint32_t min_agg_len;
+ uint32_t length;
+ /*
+ * Logical ring number for the ring to be allocated.
+ * This value determines the position in the doorbell
+ * area where the update to the ring will be made.
+ *
+ * For completion rings, this value is also the MSI-X
+ * vector number for the function the completion ring is
+ * associated with.
+ */
+ uint16_t logical_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This value indicates what completion ring the TX ring
+ * is associated with.
+ */
+ uint16_t cmpl_ring_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This value indicates what CoS queue the TX ring
+ * is associated with.
+ */
+ uint16_t queue_id;
+ /*
+ * When allocating a Rx ring or Rx aggregation ring, this field
+ * specifies the size of the buffer descriptors posted to the ring.
+ */
+ uint16_t rx_buf_size;
+ /*
+ * When allocating an Rx aggregation ring, this field
+ * specifies the associated Rx ring ID.
+ */
+ uint16_t rx_ring_id;
+ /*
+ * When allocating a completion ring, this field
+ * specifies the associated NQ ring ID.
+ */
+ uint16_t nq_ring_id;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This field is used to configure arbitration related
+ * parameters for a TX ring.
+ */
+ uint16_t ring_arb_cfg;
+ /* Arbitration policy used for the ring. */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
+ /*
+ * Use strict priority for the TX ring.
+ * Priority value is specified in arb_policy_param
+ */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
+ UINT32_C(0x1)
+ /*
+ * Use weighted fair queue arbitration for the TX ring.
+ * Weight is specified in arb_policy_param
+ */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
+ UINT32_C(0x2)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
+ HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
+ /* Reserved field. */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
+ /*
+ * Arbitration policy specific parameter.
+ * # For strict priority arbitration policy, this field
+ * represents a priority value. If set to 0, then the priority
+ * is not specified and the HWRM is allowed to select
+ * any priority for this TX ring.
+ * # For weighted fair queue arbitration policy, this field
+ * represents a weight value. If set to 0, then the weight
+ * is not specified and the HWRM is allowed to select
+ * any weight for this TX ring.
+ */
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
+ uint16_t unused_3;
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved3;
+ /*
+ * This field is used only when ring_type is a TX ring.
+ * This input indicates what statistics context this ring
+ * should be associated with.
+ */
+ uint32_t stat_ctx_id;
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved4;
+ /*
+ * This field is used only when ring_type is a TX ring
+ * to specify maximum BW allocated to the TX ring.
+ * The HWRM will translate this value into byte counter and
+ * time interval used for this ring inside the device.
+ */
+ uint32_t max_bw;
+ /* The bandwidth value. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
+ HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
+ HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
+ /*
+ * This field is used only when ring_type is a Completion ring.
+ * This value indicates what interrupt mode should be used
+ * on this completion ring.
+ * Note: In the legacy interrupt mode, no more than 16
+ * completion rings are allowed.
+ */
+ uint8_t int_mode;
+ /* Legacy INTA */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
+ /* Reserved */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
+ /* MSI-X */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
+ /* No Interrupt - Polled mode */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
+ HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
+ /* Midpath channel type */
+ uint8_t mpc_chnls_type;
+ /*
+ * Indicate the TX ring alloc MPC channel type is a MPC channel
+ * with destination to the TX crypto engine block.
+ */
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
+ /*
+ * Indicate the RX ring alloc MPC channel type is a MPC channel
+ * with destination to the RX crypto engine block.
+ */
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
+ /*
+ * Indicate the RX ring alloc MPC channel type is a MPC channel
+ * with destination to the TX configurable flow processing block.
+ */
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
+ /*
+ * Indicate the RX ring alloc MPC channel type is a MPC channel
+ * with destination to the RX configurable flow processing block.
+ */
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
+ /*
+ * Indicate the RX ring alloc MPC channel type is a MPC channel
+ * with destination to the primate processor block.
+ */
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
+ #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
+ HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
+ uint8_t unused_4[2];
+ /*
+ * The cq_handle is specified when allocating a completion ring. For
+ * devices that support NQs, this cq_handle will be included in the
+ * NQE to specify which CQ should be read to retrieve the completion
+ * record.
+ */
+ uint64_t cq_handle;
} __rte_packed;
-/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
-struct hwrm_vnic_tpa_cfg_output {
+/* hwrm_ring_alloc_output (size:128b/16B) */
+struct hwrm_ring_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * Physical number of ring allocated.
+ * This value shall be unique for a ring type.
+ */
+ uint16_t ring_id;
+ /* Logical number of ring allocated. */
+ uint16_t logical_ring_id;
+ /*
+ * This field will tell whether to use ping or pong buffer
+ * for first push operation.
+ */
+ uint8_t push_buffer_index;
+ /* Start push from ping buffer index */
+ #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
+ UINT32_C(0x0)
+ /* Start push from pong buffer index */
+ #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
+ UINT32_C(0x1)
+ #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
+ HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
+ uint8_t unused_0[2];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*********************
- * hwrm_vnic_rss_cfg *
- *********************/
+/******************
+ * hwrm_ring_free *
+ ******************/
-/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
-struct hwrm_vnic_rss_cfg_input {
+/* hwrm_ring_free_input (size:256b/32B) */
+struct hwrm_ring_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint32_t hash_type;
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv4
- * packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of TCP/IPv4 packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of UDP/IPv4 packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv6
- * packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of TCP/IPv6 packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of UDP/IPv6 packets.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
- /* VNIC ID of VNIC associated with RSS table being configured. */
- uint16_t vnic_id;
- /*
- * Specifies which VNIC ring table pair to configure.
- * Valid values range from 0 to 7.
- */
- uint8_t ring_table_pair_index;
- /* Flags to specify different RSS hash modes. */
- uint8_t hash_mode_flags;
- /*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
- */
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
- UINT32_C(0x1)
+ uint16_t target_id;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
- * l4.src, l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
- UINT32_C(0x2)
+ uint64_t resp_addr;
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ /* RX Aggregation Ring */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
+ /* Notification Queue */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
+ HWRM_RING_FREE_INPUT_RING_TYPE_NQ
+ uint8_t flags;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * If this bit is set to '1', ring_id in this command belongs to
+ * virtio function. prod_idx in this command corresponds to doorbell
+ * producer index. opaque field in this command needs to be inserted
+ * by firmware in VEE_FLUSH completion record.
+ * Firmware will poll the corresponding ring context to reach the
+ * given producer index before sending successful response. It will
+ * finish the completion using VEE_FLUSH completion record.
+ *
+ * If this bit is '0', firmware will not treat ring_id as virtio
+ * ring and ignore prod_idx, opaque fields.
+ *
+ * This feature is not applicable for L2 or RoCE.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
- UINT32_C(0x4)
+ #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
+ #define HWRM_RING_FREE_INPUT_FLAGS_LAST \
+ HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID
+ /* Physical number of ring allocated. */
+ uint16_t ring_id;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
- * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
+ * Ring BD producer index posted by the virtio block.
+ * This field is valid if virtio_ring_valid flag is set.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
- UINT32_C(0x8)
+ uint32_t prod_idx;
/*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
+ * User defined opaque field to be inserted into VEE_FLUSH completion
+ * record. This field is valid if virtio_ring_valid flag is set.
*/
- #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
- UINT32_C(0x10)
- /* This is the address for rss ring group table */
- uint64_t ring_grp_tbl_addr;
- /* This is the address for rss hash key table */
- uint64_t hash_key_tbl_addr;
- /* Index to the rss indirection table. */
- uint16_t rss_ctx_idx;
- uint8_t unused_1[6];
+ uint32_t opaque;
+ uint32_t unused_1;
} __rte_packed;
-/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
-struct hwrm_vnic_rss_cfg_output {
+/* hwrm_ring_free_output (size:128b/16B) */
+struct hwrm_ring_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint8_t valid;
} __rte_packed;
-/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
-struct hwrm_vnic_rss_cfg_cmd_err {
- /*
- * command specific error codes that goes to
- * the cmd_err field in Common HWRM Error Response.
- */
- uint8_t code;
- /* Unknown error */
- #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
- UINT32_C(0x0)
- /*
- * Unable to change global RSS mode to outer due to all active
- * interfaces are not ready to support outer RSS hashing.
- */
- #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
- UINT32_C(0x1)
- #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
- HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
- uint8_t unused_0[7];
-} __rte_packed;
-
-/**********************
- * hwrm_vnic_rss_qcfg *
- **********************/
+/*******************
+ * hwrm_ring_reset *
+ *******************/
-/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
-struct hwrm_vnic_rss_qcfg_input {
+/* hwrm_ring_reset_input (size:192b/24B) */
+struct hwrm_ring_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Index to the rss indirection table. */
- uint16_t rss_ctx_idx;
- uint8_t unused_0[6];
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* L2 Completion Ring (CR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ /* RoCE Notification Completion Ring (ROCE_CR) */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
+ /*
+ * Rx Ring Group. This is to reset rx and aggregation in an atomic
+ * operation. Completion ring associated with this ring group is
+ * not reset.
+ */
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
+ #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
+ HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
+ uint8_t unused_0;
+ /*
+ * Physical number of the ring. When ring type is rx_ring_grp, ring id
+ * actually refers to ring group id.
+ */
+ uint16_t ring_id;
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
-struct hwrm_vnic_rss_qcfg_output {
+/* hwrm_ring_reset_output (size:128b/16B) */
+struct hwrm_ring_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t hash_type;
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv4
- * packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of TCP/IPv4 packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv4 addresses and
- * source/destination ports of UDP/IPv4 packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source and destination IPv4 addresses of IPv6
- * packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
- /*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of TCP/IPv6 packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
/*
- * When this bit is '1', the RSS hash shall be computed
- * over source/destination IPv6 addresses and
- * source/destination ports of UDP/IPv6 packets.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
- uint8_t unused_0[4];
- /* This is the value of rss hash key */
- uint32_t hash_key[10];
- /* Flags to specify different RSS hash modes. */
- uint8_t hash_mode_flags;
- /*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * This field will tell whether to use ping or pong buffer
+ * for first push operation.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
+ uint8_t push_buffer_index;
+ /* Start push from ping buffer index */
+ #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
+ UINT32_C(0x0)
+ /* Start push from pong buffer index */
+ #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
UINT32_C(0x1)
- /*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
- * l4.src, l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
- UINT32_C(0x2)
- /*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
- UINT32_C(0x4)
- /*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
- * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
- * packets, the RSS hash is computed over the normal
- * src/dest l3 and src/dest l4 headers.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
- UINT32_C(0x8)
- /*
- * When this bit is '1', it indicates requesting support of
- * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
- * tunnel packets. For none-tunnel packets, the RSS hash is
- * computed over the normal src/dest l3 headers.
- */
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
- UINT32_C(0x10)
- uint8_t unused_1[6];
+ #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
+ HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
+ uint8_t unused_0[3];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/**************************
- * hwrm_vnic_plcmodes_cfg *
- **************************/
+/*****************
+ * hwrm_ring_cfg *
+ *****************/
-/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
-struct hwrm_vnic_plcmodes_cfg_input {
+/* hwrm_ring_cfg_input (size:320b/40B) */
+struct hwrm_ring_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /*
- * When this bit is '1', the VNIC shall be configured to
- * use regular placement algorithm.
- * By default, the regular placement algorithm shall be
- * enabled on the VNIC.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
- UINT32_C(0x1)
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* TX Ring (TR) */
+ #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
+ HWRM_RING_CFG_INPUT_RING_TYPE_RX
+ uint8_t unused_0;
+ /* Physical number of the ring. */
+ uint16_t ring_id;
+ /* Ring config enable bits. */
+ uint16_t enables;
/*
- * When this bit is '1', the VNIC shall be configured
- * use the jumbo placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
+ * For Rx rings, the incoming packet data can be placed at either
+ * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
+ * buffer.
+ * When '1', the received packet will be padded with 2B, 10B or 12B
+ * of zeros at the front of the packet. The exact offset is specified
+ * by rx_sop_pad_bytes parameter.
+ * When '0', the received packet will not be padded.
+ * Note that this flag is only used for Rx rings and is ignored
+ * for all other rings included Rx Aggregation rings.
+ */
+ #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
+ * When rings are allocated, the PCI function on which driver issues
+ * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
+ * the buffer descriptors (BDs) from those rings is assumed to issue
+ * packet payload DMA using same PCI function. When proxy mode is
+ * enabled, hardware can perform payload DMA using another PCI
+ * function on same or different host.
+ * When set to '0', the PCI function on which driver issues
+ * HWRM_RING_CFG command is used for host payload DMA operation.
+ * When set to '1', the host PCI function specified by proxy_fid is
+ * used for host payload DMA operation.
+ */
+ #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
UINT32_C(0x2)
/*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for IPv4 packets according
- * to the following rules:
- * # If the packet is identified as TCP/IPv4, then the
- * packet is split at the beginning of the TCP payload.
- * # If the packet is identified as UDP/IPv4, then the
- * packet is split at the beginning of UDP payload.
- * # If the packet is identified as non-TCP and non-UDP
- * IPv4 packet, then the packet is split at the beginning
- * of the upper layer protocol header carried in the IPv4
- * packet.
+ * Tx ring packet source interface override, for Tx rings only.
+ * When TX rings are allocated, the PCI function on which driver
+ * issues HWRM_RING_CFG is assumed to be source interface of
+ * packets sent from TX ring.
+ * When set to '1', the host PCI function specified by proxy_fid
+ * is used as source interface of the transmitted packets.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
+ #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
UINT32_C(0x4)
- /*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for IPv6 packets according
- * to the following rules:
- * # If the packet is identified as TCP/IPv6, then the
- * packet is split at the beginning of the TCP payload.
- * # If the packet is identified as UDP/IPv6, then the
- * packet is split at the beginning of UDP payload.
- * # If the packet is identified as non-TCP and non-UDP
- * IPv6 packet, then the packet is split at the beginning
- * of the upper layer protocol header carried in the IPv6
- * packet.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
+ /* The schq_id field is valid */
+ #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
UINT32_C(0x8)
- /*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for FCoE packets at the
- * beginning of FC payload.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
+ /* Update completion ring ID associated with Tx or Rx ring. */
+ #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
UINT32_C(0x10)
/*
- * When this bit is '1', the VNIC shall be configured
- * to enable Header-Data split for RoCE packets at the
- * beginning of RoCE payload (after BTH/GRH headers).
+ * When set to '1', metadata value provided by tx_metadata
+ * field in this command is inserted in the lb_header_metadata
+ * QP context field. When set to '0', no change done to metadata.
+ * Firmware rejects the tx ring metadata programming with
+ * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
+ * metadata feature is not disabled.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
+ #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
UINT32_C(0x20)
- uint32_t enables;
- /*
- * This bit must be '1' for the jumbo_thresh_valid field to be
- * configured.
- */
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
- UINT32_C(0x1)
/*
- * This bit must be '1' for the hds_offset_valid field to be
- * configured.
+ * Proxy function FID value.
+ * This value is only used when either proxy_mode_enable flag or
+ * tx_proxy_svif_override is set to '1'.
+ * When proxy_mode_enable is set to '1', it identifies a host PCI
+ * function used for host payload DMA operations.
+ * When tx_proxy_src_intf is set to '1', it identifies a host PCI
+ * function as source interface for all transmitted packets from
+ * the TX ring.
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
- UINT32_C(0x2)
+ uint16_t proxy_fid;
/*
- * This bit must be '1' for the hds_threshold_valid field to be
- * configured.
+ * Identifies the new scheduler queue (SCHQ) to associate with the
+ * ring. Only valid for Tx rings.
+ * A value of zero indicates that the Tx ring should be associated
+ * with the default scheduler queue (SCHQ).
*/
- #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
- UINT32_C(0x4)
- /* Logical vnic ID */
- uint32_t vnic_id;
+ uint16_t schq_id;
/*
- * When jumbo placement algorithm is enabled, this value
- * is used to determine the threshold for jumbo placement.
- * Packets with length larger than this value will be
- * placed according to the jumbo placement algorithm.
+ * This field is valid for TX or Rx rings. This value identifies the
+ * new completion ring ID to associate with the TX or Rx ring.
*/
- uint16_t jumbo_thresh;
+ uint16_t cmpl_ring_id;
/*
- * This value is used to determine the offset into
- * packet buffer where the split data (payload) will be
- * placed according to one of HDS placement algorithm.
- *
- * The lengths of packet buffers provided for split data
- * shall be larger than this value.
+ * Rx SOP padding amount in bytes.
+ * This value is only used when rx_sop_pad_enable flag is set to '1'.
*/
- uint16_t hds_offset;
+ uint8_t rx_sop_pad_bytes;
+ uint8_t unused_1[3];
/*
- * When one of the HDS placement algorithm is enabled, this
- * value is used to determine the threshold for HDS
- * placement.
- * Packets with length larger than this value will be
- * placed according to the HDS placement algorithm.
- * This value shall be in multiple of 4 bytes.
+ * When tx_metadata enable bit is set, value specified in this field
+ * is copied to lb_header_metadata in the QP context.
*/
- uint16_t hds_threshold;
- uint8_t unused_0[6];
+ uint32_t tx_metadata;
+ uint8_t unused_2[4];
} __rte_packed;
-/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
-struct hwrm_vnic_plcmodes_cfg_output {
+/* hwrm_ring_cfg_output (size:128b/16B) */
+struct hwrm_ring_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/***************************
- * hwrm_vnic_plcmodes_qcfg *
- ***************************/
+/******************
+ * hwrm_ring_qcfg *
+ ******************/
-/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
-struct hwrm_vnic_plcmodes_qcfg_input {
+/* hwrm_ring_qcfg_input (size:192b/24B) */
+struct hwrm_ring_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Logical vnic ID */
- uint32_t vnic_id;
- uint8_t unused_0[4];
+ /* Ring Type. */
+ uint8_t ring_type;
+ /* TX Ring (TR) */
+ #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
+ /* RX Ring (RR) */
+ #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
+ #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
+ HWRM_RING_QCFG_INPUT_RING_TYPE_RX
+ uint8_t unused_0[5];
+ /* Physical number of the ring. */
+ uint16_t ring_id;
} __rte_packed;
-/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
-struct hwrm_vnic_plcmodes_qcfg_output {
+/* hwrm_ring_qcfg_output (size:256b/32B) */
+struct hwrm_ring_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t flags;
- /*
- * When this bit is '1', the VNIC is configured to
- * use regular placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
- UINT32_C(0x1)
+ /* Ring config enable bits. */
+ uint16_t enables;
/*
- * When this bit is '1', the VNIC is configured to
- * use the jumbo placement algorithm.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
+ * For Rx rings, the incoming packet data can be placed at either
+ * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
+ * buffer.
+ * When '1', the received packet will be padded with 2B, 10B or 12B
+ * of zeros at the front of the packet. The exact offset is specified
+ * by rx_sop_pad_bytes parameter.
+ * When '0', the received packet will not be padded.
+ * Note that this flag is only used for Rx rings and is ignored
+ * for all other rings included Rx Aggregation rings.
+ */
+ #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
+ * When rings are allocated, the PCI function on which driver issues
+ * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
+ * the buffer descriptors (BDs) from those rings is assumed to issue
+ * packet payload DMA using same PCI function. When proxy mode is
+ * enabled, hardware can perform payload DMA using another PCI
+ * function on same or different host.
+ * When set to '0', the PCI function on which driver issues
+ * HWRM_RING_CFG command is used for host payload DMA operation.
+ * When set to '1', the host PCI function specified by proxy_fid is
+ * used for host payload DMA operation.
+ */
+ #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
UINT32_C(0x2)
/*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for IPv4 packets.
+ * Tx ring packet source interface override, for Tx rings only.
+ * When TX rings are allocated, the PCI function on which driver
+ * issues HWRM_RING_CFG is assumed to be source interface of
+ * packets sent from TX ring.
+ * When set to '1', the host PCI function specified by proxy_fid is
+ * used as source interface of the transmitted packets.
*/
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
+ #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
UINT32_C(0x4)
/*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for IPv6 packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
- UINT32_C(0x8)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for FCoE packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
- UINT32_C(0x10)
- /*
- * When this bit is '1', the VNIC is configured
- * to enable Header-Data split for RoCE packets.
- */
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
- UINT32_C(0x20)
- /*
- * When this bit is '1', the VNIC is configured
- * to be the default VNIC of the requesting function.
+ * Proxy function FID value.
+ * This value is only used when either proxy_mode_enable flag or
+ * tx_proxy_svif_override is set to '1'.
+ * When proxy_mode_enable is set to '1', it identifies a host PCI
+ * function used for host payload DMA operations.
+ * When tx_proxy_src_intf is set to '1', it identifies a host PCI
+ * function as source interface for all transmitted packets from the TX
+ * ring.
*/
- #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
- UINT32_C(0x40)
+ uint16_t proxy_fid;
/*
- * When jumbo placement algorithm is enabled, this value
- * is used to determine the threshold for jumbo placement.
- * Packets with length larger than this value will be
- * placed according to the jumbo placement algorithm.
+ * Identifies the new scheduler queue (SCHQ) to associate with the
+ * ring. Only valid for Tx rings.
+ * A value of zero indicates that the Tx ring should be associated with
+ * the default scheduler queue (SCHQ).
*/
- uint16_t jumbo_thresh;
+ uint16_t schq_id;
/*
- * This value is used to determine the offset into
- * packet buffer where the split data (payload) will be
- * placed according to one of HDS placement algorithm.
- *
- * The lengths of packet buffers provided for split data
- * shall be larger than this value.
+ * This field is used when ring_type is a TX or Rx ring.
+ * This value indicates what completion ring the TX or Rx ring
+ * is associated with.
*/
- uint16_t hds_offset;
+ uint16_t cmpl_ring_id;
/*
- * When one of the HDS placement algorithm is enabled, this
- * value is used to determine the threshold for HDS
- * placement.
- * Packets with length larger than this value will be
- * placed according to the HDS placement algorithm.
- * This value shall be in multiple of 4 bytes.
+ * Rx SOP padding amount in bytes.
+ * This value is only used when rx_sop_pad_enable flag is set to '1'.
*/
- uint16_t hds_threshold;
- uint8_t unused_0[5];
+ uint8_t rx_sop_pad_bytes;
+ uint8_t unused_0[3];
+ /* lb_header_metadata in the QP context is copied to this field. */
+ uint32_t tx_metadata;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/**********************************
- * hwrm_vnic_rss_cos_lb_ctx_alloc *
- **********************************/
+/**************************
+ * hwrm_ring_aggint_qcaps *
+ **************************/
-/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
+/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
+struct hwrm_ring_aggint_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
uint64_t resp_addr;
} __rte_packed;
-/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
+/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
+struct hwrm_ring_aggint_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* rss_cos_lb_ctx_id is 16 b */
- uint16_t rss_cos_lb_ctx_id;
- uint8_t unused_0[5];
+ uint32_t cmpl_params;
+ /*
+ * When this bit is set to '1', int_lat_tmr_min can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', int_lat_tmr_max can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
+ UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', timer_reset can be enabled
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
+ UINT32_C(0x4)
+ /*
+ * When this bit is set to '1', ring_idle can be enabled
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
+ UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', num_cmpl_dma_aggr can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
+ UINT32_C(0x10)
+ /*
+ * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
+ UINT32_C(0x20)
+ /*
+ * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
+ UINT32_C(0x40)
+ /*
+ * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
+ UINT32_C(0x80)
+ /*
+ * When this bit is set to '1', num_cmpl_aggr_int can be configured
+ * on completion rings.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
+ UINT32_C(0x100)
+ uint32_t nq_params;
+ /*
+ * When this bit is set to '1', int_lat_tmr_min can be configured
+ * on notification queues.
+ */
+ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
+ UINT32_C(0x1)
+ /* Minimum value for num_cmpl_dma_aggr */
+ uint16_t num_cmpl_dma_aggr_min;
+ /* Maximum value for num_cmpl_dma_aggr */
+ uint16_t num_cmpl_dma_aggr_max;
+ /* Minimum value for num_cmpl_dma_aggr_during_int */
+ uint16_t num_cmpl_dma_aggr_during_int_min;
+ /* Maximum value for num_cmpl_dma_aggr_during_int */
+ uint16_t num_cmpl_dma_aggr_during_int_max;
+ /* Minimum value for cmpl_aggr_dma_tmr */
+ uint16_t cmpl_aggr_dma_tmr_min;
+ /* Maximum value for cmpl_aggr_dma_tmr */
+ uint16_t cmpl_aggr_dma_tmr_max;
+ /* Minimum value for cmpl_aggr_dma_tmr_during_int */
+ uint16_t cmpl_aggr_dma_tmr_during_int_min;
+ /* Maximum value for cmpl_aggr_dma_tmr_during_int */
+ uint16_t cmpl_aggr_dma_tmr_during_int_max;
+ /* Minimum value for int_lat_tmr_min */
+ uint16_t int_lat_tmr_min_min;
+ /* Maximum value for int_lat_tmr_min */
+ uint16_t int_lat_tmr_min_max;
+ /* Minimum value for int_lat_tmr_max */
+ uint16_t int_lat_tmr_max_min;
+ /* Maximum value for int_lat_tmr_max */
+ uint16_t int_lat_tmr_max_max;
+ /* Minimum value for num_cmpl_aggr_int */
+ uint16_t num_cmpl_aggr_int_min;
+ /* Maximum value for num_cmpl_aggr_int */
+ uint16_t num_cmpl_aggr_int_max;
+ /* The units for timer parameters, in nanoseconds. */
+ uint16_t timer_units;
+ uint8_t unused_0[1];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*********************************
- * hwrm_vnic_rss_cos_lb_ctx_free *
- *********************************/
+/**************************************
+ * hwrm_ring_cmpl_ring_qaggint_params *
+ **************************************/
-/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
-struct hwrm_vnic_rss_cos_lb_ctx_free_input {
+/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
+struct hwrm_ring_cmpl_ring_qaggint_params_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* rss_cos_lb_ctx_id is 16 b */
- uint16_t rss_cos_lb_ctx_id;
- uint8_t unused_0[6];
+ /* Physical number of completion ring. */
+ uint16_t ring_id;
+ uint16_t flags;
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
+ UINT32_C(0x3)
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
+ /*
+ * Set this flag to 1 when querying parameters on a notification
+ * queue. Set this flag to 0 when querying parameters on a
+ * completion queue or completion ring.
+ */
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
+ UINT32_C(0x4)
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
-struct hwrm_vnic_rss_cos_lb_ctx_free_output {
+/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
+struct hwrm_ring_cmpl_ring_qaggint_params_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ uint16_t flags;
+ /*
+ * When this bit is set to '1', interrupt max
+ * timer is reset whenever a completion is received.
+ */
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', ring idle mode
+ * aggregation will be enabled.
+ */
+ #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
+ UINT32_C(0x2)
+ /*
+ * Number of completions to aggregate before DMA
+ * during the normal mode.
+ */
+ uint16_t num_cmpl_dma_aggr;
+ /*
+ * Number of completions to aggregate before DMA
+ * during the interrupt mode.
+ */
+ uint16_t num_cmpl_dma_aggr_during_int;
+ /*
+ * Timer used to aggregate completions before
+ * DMA during the normal mode (not in interrupt mode).
+ */
+ uint16_t cmpl_aggr_dma_tmr;
+ /*
+ * Timer used to aggregate completions before
+ * DMA when in interrupt mode.
+ */
+ uint16_t cmpl_aggr_dma_tmr_during_int;
+ /* Minimum time between two interrupts. */
+ uint16_t int_lat_tmr_min;
+ /*
+ * Maximum wait time spent aggregating
+ * completions before signaling the interrupt after the
+ * interrupt is enabled.
+ */
+ uint16_t int_lat_tmr_max;
+ /*
+ * Minimum number of completions aggregated before signaling
+ * an interrupt.
+ */
+ uint16_t num_cmpl_aggr_int;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
uint8_t valid;
} __rte_packed;
-/*******************
- * hwrm_ring_alloc *
- *******************/
+/*****************************************
+ * hwrm_ring_cmpl_ring_cfg_aggint_params *
+ *****************************************/
-/* hwrm_ring_alloc_input (size:704b/88B) */
-struct hwrm_ring_alloc_input {
+/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
+struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
- /*
- * This bit must be '1' for the ring_arb_cfg field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
- UINT32_C(0x2)
- /*
- * This bit must be '1' for the stat_ctx_id_valid field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
- UINT32_C(0x8)
- /*
- * This bit must be '1' for the max_bw_valid field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
- UINT32_C(0x20)
- /*
- * This bit must be '1' for the rx_ring_id field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
- UINT32_C(0x40)
- /*
- * This bit must be '1' for the nq_ring_id field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
- UINT32_C(0x80)
- /*
- * This bit must be '1' for the rx_buf_size field to be
- * configured.
- */
- #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
- UINT32_C(0x100)
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- /* RX Aggregation Ring */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
- /* Notification Queue */
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
- #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
- HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
- uint8_t unused_0;
- /* Ring allocation flags. */
+ /* Physical number of completion ring. */
+ uint16_t ring_id;
uint16_t flags;
/*
- * For Rx rings, the incoming packet data can be placed at either
- * a 0B or 2B offset from the start of the Rx packet buffer. When
- * '1', the received packet will be padded with 2B of zeros at the
- * front of the packet. Note that this flag is only used for
- * Rx rings and is ignored for all other rings included Rx
- * Aggregation rings.
- */
- #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
- /*
- * This value is a pointer to the page table for the
- * Ring.
- */
- uint64_t page_tbl_addr;
- /* First Byte Offset of the first entry in the first page. */
- uint32_t fbo;
- /*
- * Actual page size in 2^page_size. The supported range is increments
- * in powers of 2 from 16 bytes to 1GB.
- * - 4 = 16 B
- * Page size is 16 B.
- * - 12 = 4 KB
- * Page size is 4 KB.
- * - 13 = 8 KB
- * Page size is 8 KB.
- * - 16 = 64 KB
- * Page size is 64 KB.
- * - 21 = 2 MB
- * Page size is 2 MB.
- * - 22 = 4 MB
- * Page size is 4 MB.
- * - 30 = 1 GB
- * Page size is 1 GB.
+ * When this bit is set to '1', interrupt latency max
+ * timer is reset whenever a completion is received.
*/
- uint8_t page_size;
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
+ UINT32_C(0x1)
/*
- * This value indicates the depth of page table.
- * For this version of the specification, value other than 0 or
- * 1 shall be considered as an invalid value.
- * When the page_tbl_depth = 0, then it is treated as a
- * special case with the following.
- * 1. FBO and page size fields are not valid.
- * 2. page_tbl_addr is the physical address of the first
- * element of the ring.
+ * When this bit is set to '1', ring idle mode
+ * aggregation will be enabled.
*/
- uint8_t page_tbl_depth;
- uint8_t unused_1[2];
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
+ UINT32_C(0x2)
/*
- * Number of 16B units in the ring. Minimum size for
- * a ring is 16 16B entries.
+ * Set this flag to 1 when configuring parameters on a
+ * notification queue. Set this flag to 0 when configuring
+ * parameters on a completion queue or completion ring.
*/
- uint32_t length;
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
+ UINT32_C(0x4)
/*
- * Logical ring number for the ring to be allocated.
- * This value determines the position in the doorbell
- * area where the update to the ring will be made.
- *
- * For completion rings, this value is also the MSI-X
- * vector number for the function the completion ring is
- * associated with.
+ * Number of completions to aggregate before DMA
+ * during the normal mode.
*/
- uint16_t logical_id;
+ uint16_t num_cmpl_dma_aggr;
/*
- * This field is used only when ring_type is a TX ring.
- * This value indicates what completion ring the TX ring
- * is associated with.
+ * Number of completions to aggregate before DMA
+ * during the interrupt mode.
*/
- uint16_t cmpl_ring_id;
+ uint16_t num_cmpl_dma_aggr_during_int;
/*
- * This field is used only when ring_type is a TX ring.
- * This value indicates what CoS queue the TX ring
- * is associated with.
+ * Timer used to aggregate completions before
+ * DMA during the normal mode (not in interrupt mode).
*/
- uint16_t queue_id;
+ uint16_t cmpl_aggr_dma_tmr;
/*
- * When allocating a Rx ring or Rx aggregation ring, this field
- * specifies the size of the buffer descriptors posted to the ring.
+ * Timer used to aggregate completions before
+ * DMA while in interrupt mode.
*/
- uint16_t rx_buf_size;
+ uint16_t cmpl_aggr_dma_tmr_during_int;
+ /* Minimum time between two interrupts. */
+ uint16_t int_lat_tmr_min;
/*
- * When allocating an Rx aggregation ring, this field
- * specifies the associated Rx ring ID.
+ * Maximum wait time spent aggregating
+ * completions before signaling the interrupt after the
+ * interrupt is enabled.
*/
- uint16_t rx_ring_id;
+ uint16_t int_lat_tmr_max;
/*
- * When allocating a completion ring, this field
- * specifies the associated NQ ring ID.
+ * Minimum number of completions aggregated before signaling
+ * an interrupt.
*/
- uint16_t nq_ring_id;
+ uint16_t num_cmpl_aggr_int;
/*
- * This field is used only when ring_type is a TX ring.
- * This field is used to configure arbitration related
- * parameters for a TX ring.
+ * Bitfield that indicates which parameters are to be applied. Only
+ * required when configuring devices with notification queues, and
+ * used in that case to set certain parameters on completion queues
+ * and others on notification queues.
*/
- uint16_t ring_arb_cfg;
- /* Arbitration policy used for the ring. */
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
- UINT32_C(0xf)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
+ uint16_t enables;
/*
- * Use strict priority for the TX ring.
- * Priority value is specified in arb_policy_param
+ * This bit must be '1' for the num_cmpl_dma_aggr field to be
+ * configured.
*/
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
UINT32_C(0x1)
/*
- * Use weighted fair queue arbitration for the TX ring.
- * Weight is specified in arb_policy_param
+ * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
+ * configured.
*/
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
UINT32_C(0x2)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
- HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
- /* Reserved field. */
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
- UINT32_C(0xf0)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
- /*
- * Arbitration policy specific parameter.
- * # For strict priority arbitration policy, this field
- * represents a priority value. If set to 0, then the priority
- * is not specified and the HWRM is allowed to select
- * any priority for this TX ring.
- * # For weighted fair queue arbitration policy, this field
- * represents a weight value. If set to 0, then the weight
- * is not specified and the HWRM is allowed to select
- * any weight for this TX ring.
- */
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
- UINT32_C(0xff00)
- #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
- uint16_t unused_3;
/*
- * This field is reserved for the future use.
- * It shall be set to 0.
- */
- uint32_t reserved3;
- /*
- * This field is used only when ring_type is a TX ring.
- * This input indicates what statistics context this ring
- * should be associated with.
- */
- uint32_t stat_ctx_id;
- /*
- * This field is reserved for the future use.
- * It shall be set to 0.
+ * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
+ * configured.
*/
- uint32_t reserved4;
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
+ UINT32_C(0x4)
/*
- * This field is used only when ring_type is a TX ring
- * to specify maximum BW allocated to the TX ring.
- * The HWRM will translate this value into byte counter and
- * time interval used for this ring inside the device.
+ * This bit must be '1' for the int_lat_tmr_min field to be
+ * configured.
*/
- uint32_t max_bw;
- /* The bandwidth value. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
- UINT32_C(0xfffffff)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
- /* The granularity of the value (bits or bytes). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
- UINT32_C(0x10000000)
- /* Value is in bits. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
- (UINT32_C(0x0) << 28)
- /* Value is in bytes. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
- (UINT32_C(0x1) << 28)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
- HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
- /* bw_value_unit is 3 b */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
- UINT32_C(0xe0000000)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
- /* Value is in Mb or MB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
- (UINT32_C(0x0) << 29)
- /* Value is in Kb or KB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
- (UINT32_C(0x2) << 29)
- /* Value is in bits or bytes. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
- (UINT32_C(0x4) << 29)
- /* Value is in Gb or GB (base 10). */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
- (UINT32_C(0x6) << 29)
- /* Value is in 1/100th of a percentage of total bandwidth. */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
- (UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
- (UINT32_C(0x7) << 29)
- #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
- HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
+ UINT32_C(0x8)
/*
- * This field is used only when ring_type is a Completion ring.
- * This value indicates what interrupt mode should be used
- * on this completion ring.
- * Note: In the legacy interrupt mode, no more than 16
- * completion rings are allowed.
+ * This bit must be '1' for the int_lat_tmr_max field to be
+ * configured.
*/
- uint8_t int_mode;
- /* Legacy INTA */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
- /* Reserved */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
- /* MSI-X */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
- /* No Interrupt - Polled mode */
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
- #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
- HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
- uint8_t unused_4[3];
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
+ UINT32_C(0x10)
/*
- * The cq_handle is specified when allocating a completion ring. For
- * devices that support NQs, this cq_handle will be included in the
- * NQE to specify which CQ should be read to retrieve the completion
- * record.
+ * This bit must be '1' for the num_cmpl_aggr_int field to be
+ * configured.
*/
- uint64_t cq_handle;
+ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
+ UINT32_C(0x20)
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_ring_alloc_output (size:128b/16B) */
-struct hwrm_ring_alloc_output {
+/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
+struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /*
- * Physical number of ring allocated.
- * This value shall be unique for a ring type.
- */
- uint16_t ring_id;
- /* Logical number of ring allocated. */
- uint16_t logical_ring_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/******************
- * hwrm_ring_free *
- ******************/
+/***********************
+ * hwrm_ring_grp_alloc *
+ ***********************/
-/* hwrm_ring_free_input (size:192b/24B) */
-struct hwrm_ring_free_input {
+/* hwrm_ring_grp_alloc_input (size:192b/24B) */
+struct hwrm_ring_grp_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- /* RX Aggregation Ring */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
- /* Notification Queue */
- #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
- #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
- HWRM_RING_FREE_INPUT_RING_TYPE_NQ
- uint8_t unused_0;
- /* Physical number of ring allocated. */
- uint16_t ring_id;
- uint8_t unused_1[4];
+ /*
+ * This value identifies the CR associated with the ring
+ * group.
+ */
+ uint16_t cr;
+ /*
+ * This value identifies the main RR associated with the ring
+ * group.
+ */
+ uint16_t rr;
+ /*
+ * This value identifies the aggregation RR associated with
+ * the ring group. If this value is 0xFF... (All Fs), then no
+ * Aggregation ring will be set.
+ */
+ uint16_t ar;
+ /*
+ * This value identifies the statistics context associated
+ * with the ring group.
+ */
+ uint16_t sc;
} __rte_packed;
-/* hwrm_ring_free_output (size:128b/16B) */
-struct hwrm_ring_free_output {
+/* hwrm_ring_grp_alloc_output (size:128b/16B) */
+struct hwrm_ring_grp_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /*
+ * This is the ring group ID value. Use this value to program
+ * the default ring group for the VNIC or as table entries
+ * in an RSS/COS context.
+ */
+ uint32_t ring_group_id;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*******************
- * hwrm_ring_reset *
- *******************/
+/**********************
+ * hwrm_ring_grp_free *
+ **********************/
-/* hwrm_ring_reset_input (size:192b/24B) */
-struct hwrm_ring_reset_input {
+/* hwrm_ring_grp_free_input (size:192b/24B) */
+struct hwrm_ring_grp_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Ring Type. */
- uint8_t ring_type;
- /* L2 Completion Ring (CR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
- /* TX Ring (TR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
- /* RX Ring (RR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
- /* RoCE Notification Completion Ring (ROCE_CR) */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
- /*
- * Rx Ring Group. This is to reset rx and aggregation in an atomic
- * operation. Completion ring associated with this ring group is
- * not reset.
- */
- #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
- #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
- HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
- uint8_t unused_0;
- /*
- * Physical number of the ring. When ring type is rx_ring_grp, ring id
- * actually refers to ring group id.
- */
- uint16_t ring_id;
- uint8_t unused_1[4];
+ /* This is the ring group ID value. */
+ uint32_t ring_group_id;
+ uint8_t unused_0[4];
} __rte_packed;
-/* hwrm_ring_reset_output (size:128b/16B) */
-struct hwrm_ring_reset_output {
+/* hwrm_ring_grp_free_output (size:128b/16B) */
+struct hwrm_ring_grp_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[4];
- /* Position of consumer index after ring reset completes. */
- uint8_t consumer_idx[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/**************************
- * hwrm_ring_aggint_qcaps *
- **************************/
+/************************
+ * hwrm_ring_schq_alloc *
+ ************************/
-/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
-struct hwrm_ring_aggint_qcaps_input {
+/* hwrm_ring_schq_alloc_input (size:1088b/136B) */
+struct hwrm_ring_schq_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
-} __rte_packed;
-
-/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
-struct hwrm_ring_aggint_qcaps_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint32_t cmpl_params;
+ uint32_t enables;
/*
- * When this bit is set to '1', int_lat_tmr_min can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring0 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
- UINT32_C(0x1)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
/*
- * When this bit is set to '1', int_lat_tmr_max can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring1 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
- UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
/*
- * When this bit is set to '1', timer_reset can be enabled
- * on completion rings.
+ * This bit must be '1' for the tqm_ring2 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
- UINT32_C(0x4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
/*
- * When this bit is set to '1', ring_idle can be enabled
- * on completion rings.
+ * This bit must be '1' for the tqm_ring3 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
- UINT32_C(0x8)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
/*
- * When this bit is set to '1', num_cmpl_dma_aggr can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring4 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
- UINT32_C(0x10)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
/*
- * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring5 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
- UINT32_C(0x20)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
/*
- * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring6 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
- UINT32_C(0x40)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
/*
- * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
- * on completion rings.
+ * This bit must be '1' for the tqm_ring7 fields to be
+ * configured.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
- UINT32_C(0x80)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
+ /* Reserved for future use. */
+ uint32_t reserved;
+ /* TQM ring 0 page size and level. */
+ uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
+ /* TQM ring 0 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * When this bit is set to '1', num_cmpl_aggr_int can be configured
- * on completion rings.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
- UINT32_C(0x100)
- uint32_t nq_params;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
+ /* TQM ring 0 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
+ /* TQM ring 1 page size and level. */
+ uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
+ /* TQM ring 1 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * When this bit is set to '1', int_lat_tmr_min can be configured
- * on notification queues.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
+ /* TQM ring 1 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
+ /* TQM ring 2 page size and level. */
+ uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
+ /* TQM ring 2 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
UINT32_C(0x1)
- /* Minimum value for num_cmpl_dma_aggr */
- uint16_t num_cmpl_dma_aggr_min;
- /* Maximum value for num_cmpl_dma_aggr */
- uint16_t num_cmpl_dma_aggr_max;
- /* Minimum value for num_cmpl_dma_aggr_during_int */
- uint16_t num_cmpl_dma_aggr_during_int_min;
- /* Maximum value for num_cmpl_dma_aggr_during_int */
- uint16_t num_cmpl_dma_aggr_during_int_max;
- /* Minimum value for cmpl_aggr_dma_tmr */
- uint16_t cmpl_aggr_dma_tmr_min;
- /* Maximum value for cmpl_aggr_dma_tmr */
- uint16_t cmpl_aggr_dma_tmr_max;
- /* Minimum value for cmpl_aggr_dma_tmr_during_int */
- uint16_t cmpl_aggr_dma_tmr_during_int_min;
- /* Maximum value for cmpl_aggr_dma_tmr_during_int */
- uint16_t cmpl_aggr_dma_tmr_during_int_max;
- /* Minimum value for int_lat_tmr_min */
- uint16_t int_lat_tmr_min_min;
- /* Maximum value for int_lat_tmr_min */
- uint16_t int_lat_tmr_min_max;
- /* Minimum value for int_lat_tmr_max */
- uint16_t int_lat_tmr_max_min;
- /* Maximum value for int_lat_tmr_max */
- uint16_t int_lat_tmr_max_max;
- /* Minimum value for num_cmpl_aggr_int */
- uint16_t num_cmpl_aggr_int_min;
- /* Maximum value for num_cmpl_aggr_int */
- uint16_t num_cmpl_aggr_int_max;
- /* The units for timer parameters, in nanoseconds. */
- uint16_t timer_units;
- uint8_t unused_0[1];
/*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- uint8_t valid;
-} __rte_packed;
-
-/**************************************
- * hwrm_ring_cmpl_ring_qaggint_params *
- **************************************/
-
-
-/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
-struct hwrm_ring_cmpl_ring_qaggint_params_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
+ /* TQM ring 2 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
+ /* TQM ring 3 page size and level. */
+ uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
+ /* TQM ring 3 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- uint16_t cmpl_ring;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
+ /* TQM ring 3 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
+ /* TQM ring 4 page size and level. */
+ uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
+ /* TQM ring 4 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- uint16_t seq_id;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
+ /* TQM ring 4 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
+ /* TQM ring 5 page size and level. */
+ uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
+ /* TQM ring 5 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- uint16_t target_id;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
+ /* TQM ring 5 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
+ /* TQM ring 6 page size and level. */
+ uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
+ /* TQM ring 6 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- uint64_t resp_addr;
- /* Physical number of completion ring. */
- uint16_t ring_id;
- uint16_t flags;
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
- UINT32_C(0x3)
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
+ /* TQM ring 6 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
+ /* TQM ring 7 page size and level. */
+ uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
+ /* TQM ring 7 PBL indirect levels. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
+ UINT32_C(0xf)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
+ /* PBL pointer is physical start address. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
+ UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
+ UINT32_C(0x1)
/*
- * Set this flag to 1 when querying parameters on a notification
- * queue. Set this flag to 0 when querying parameters on a
- * completion queue or completion ring.
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
*/
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
- UINT32_C(0x4)
- uint8_t unused_0[4];
-} __rte_packed;
-
-/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
-struct hwrm_ring_cmpl_ring_qaggint_params_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint16_t flags;
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
+ UINT32_C(0x2)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
+ /* TQM ring 7 page size. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
+ UINT32_C(0xf0)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
+ /* 4KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
+ (UINT32_C(0x0) << 4)
+ /* 8KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
+ (UINT32_C(0x1) << 4)
+ /* 64KB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
+ (UINT32_C(0x2) << 4)
+ /* 2MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
+ (UINT32_C(0x3) << 4)
+ /* 8MB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
+ (UINT32_C(0x4) << 4)
+ /* 1GB. */
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
+ (UINT32_C(0x5) << 4)
+ #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
+ HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
+ /* TQM ring 0 page directory. */
+ uint64_t tqm_ring0_page_dir;
+ /* TQM ring 1 page directory. */
+ uint64_t tqm_ring1_page_dir;
+ /* TQM ring 2 page directory. */
+ uint64_t tqm_ring2_page_dir;
+ /* TQM ring 3 page directory. */
+ uint64_t tqm_ring3_page_dir;
+ /* TQM ring 4 page directory. */
+ uint64_t tqm_ring4_page_dir;
+ /* TQM ring 5 page directory. */
+ uint64_t tqm_ring5_page_dir;
+ /* TQM ring 6 page directory. */
+ uint64_t tqm_ring6_page_dir;
+ /* TQM ring 7 page directory. */
+ uint64_t tqm_ring7_page_dir;
/*
- * When this bit is set to '1', interrupt max
- * timer is reset whenever a completion is received.
+ * Number of TQM ring 0 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
- UINT32_C(0x1)
+ uint32_t tqm_ring0_num_entries;
/*
- * When this bit is set to '1', ring idle mode
- * aggregation will be enabled.
+ * Number of TQM ring 1 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
- UINT32_C(0x2)
+ uint32_t tqm_ring1_num_entries;
/*
- * Number of completions to aggregate before DMA
- * during the normal mode.
+ * Number of TQM ring 2 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t num_cmpl_dma_aggr;
+ uint32_t tqm_ring2_num_entries;
/*
- * Number of completions to aggregate before DMA
- * during the interrupt mode.
+ * Number of TQM ring 3 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t num_cmpl_dma_aggr_during_int;
+ uint32_t tqm_ring3_num_entries;
/*
- * Timer used to aggregate completions before
- * DMA during the normal mode (not in interrupt mode).
+ * Number of TQM ring 4 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t cmpl_aggr_dma_tmr;
+ uint32_t tqm_ring4_num_entries;
/*
- * Timer used to aggregate completions before
- * DMA when in interrupt mode.
+ * Number of TQM ring 5 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t cmpl_aggr_dma_tmr_during_int;
- /* Minimum time between two interrupts. */
- uint16_t int_lat_tmr_min;
+ uint32_t tqm_ring5_num_entries;
/*
- * Maximum wait time spent aggregating
- * completions before signaling the interrupt after the
- * interrupt is enabled.
+ * Number of TQM ring 6 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t int_lat_tmr_max;
+ uint32_t tqm_ring6_num_entries;
/*
- * Minimum number of completions aggregated before signaling
- * an interrupt.
+ * Number of TQM ring 7 entries.
+ *
+ * TQM fastpath rings should be sized large enough to accommodate the
+ * maximum number of QPs (either L2 or RoCE, or both if shared)
+ * that can be enqueued to the TQM ring.
+ *
+ * Note that TQM ring sizes cannot be extended while the system is
+ * operational. If a PF driver needs to extend a TQM ring, it needs
+ * to delete the SCHQ and then reallocate it.
*/
- uint16_t num_cmpl_aggr_int;
- uint8_t unused_0[7];
+ uint32_t tqm_ring7_num_entries;
+ /* Number of bytes that have been allocated for each context entry. */
+ uint16_t tqm_entry_size;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_ring_schq_alloc_output (size:128b/16B) */
+struct hwrm_ring_schq_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * This is an identifier for the SCHQ to be used in other HWRM commands
+ * that need to reference this SCHQ. This value is greater than zero
+ * (i.e. a schq_id of zero references the default SCHQ).
+ */
+ uint16_t schq_id;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __rte_packed;
-/*****************************************
- * hwrm_ring_cmpl_ring_cfg_aggint_params *
- *****************************************/
+/**********************
+ * hwrm_ring_schq_cfg *
+ **********************/
-/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
-struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
+/* hwrm_ring_schq_cfg_input (size:768b/96B) */
+struct hwrm_ring_schq_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Physical number of completion ring. */
- uint16_t ring_id;
- uint16_t flags;
- /*
- * When this bit is set to '1', interrupt latency max
- * timer is reset whenever a completion is received.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
- UINT32_C(0x1)
/*
- * When this bit is set to '1', ring idle mode
- * aggregation will be enabled.
+ * Identifies the SCHQ being configured. A schq_id of zero refers to
+ * the default SCHQ.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
- UINT32_C(0x2)
+ uint16_t schq_id;
/*
- * Set this flag to 1 when configuring parameters on a
- * notification queue. Set this flag to 0 when configuring
- * parameters on a completion queue or completion ring.
+ * This field is an 8 bit bitmap that indicates which TCs are enabled
+ * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
+ * traffic class 7.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
- UINT32_C(0x4)
- /*
- * Number of completions to aggregate before DMA
- * during the normal mode.
- */
- uint16_t num_cmpl_dma_aggr;
- /*
- * Number of completions to aggregate before DMA
- * during the interrupt mode.
- */
- uint16_t num_cmpl_dma_aggr_during_int;
- /*
- * Timer used to aggregate completions before
- * DMA during the normal mode (not in interrupt mode).
- */
- uint16_t cmpl_aggr_dma_tmr;
- /*
- * Timer used to aggregate completions before
- * DMA while in interrupt mode.
- */
- uint16_t cmpl_aggr_dma_tmr_during_int;
- /* Minimum time between two interrupts. */
- uint16_t int_lat_tmr_min;
- /*
- * Maximum wait time spent aggregating
- * completions before signaling the interrupt after the
- * interrupt is enabled.
- */
- uint16_t int_lat_tmr_max;
- /*
- * Minimum number of completions aggregated before signaling
- * an interrupt.
- */
- uint16_t num_cmpl_aggr_int;
- /*
- * Bitfield that indicates which parameters are to be applied. Only
- * required when configuring devices with notification queues, and
- * used in that case to set certain parameters on completion queues
- * and others on notification queues.
- */
- uint16_t enables;
- /*
- * This bit must be '1' for the num_cmpl_dma_aggr field to be
- * configured.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
+ uint8_t tc_enabled;
+ uint8_t unused_0;
+ uint32_t flags;
+ /* The tc_max_bw array and the max_bw parameters are valid */
+ #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
- * configured.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
+ /* The tc_min_bw array is valid */
+ #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
UINT32_C(0x2)
- /*
- * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
- * configured.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
- UINT32_C(0x4)
- /*
- * This bit must be '1' for the int_lat_tmr_min field to be
- * configured.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
- UINT32_C(0x8)
- /*
- * This bit must be '1' for the int_lat_tmr_max field to be
- * configured.
- */
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
- UINT32_C(0x10)
- /*
- * This bit must be '1' for the num_cmpl_aggr_int field to be
- * configured.
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc0;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc1;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc2;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc3;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc4;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc5;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc6;
+ /* Maximum bandwidth of the traffic class, specified in Mbps. */
+ uint32_t max_bw_tc7;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc0;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc1;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc2;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc3;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc4;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc5;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc6;
+ /*
+ * Bandwidth reservation for the traffic class, specified in Mbps.
+ * A value of zero signifies that traffic belonging to this class
+ * shares the bandwidth reservation for the same traffic class of
+ * the default SCHQ.
+ */
+ uint32_t min_bw_tc7;
+ /*
+ * Indicates the max bandwidth for all enabled traffic classes in
+ * this SCHQ, specified in Mbps.
*/
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
- UINT32_C(0x20)
- uint8_t unused_0[4];
+ uint32_t max_bw;
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
-struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
+/* hwrm_ring_schq_cfg_output (size:128b/16B) */
+struct hwrm_ring_schq_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
} __rte_packed;
/***********************
- * hwrm_ring_grp_alloc *
+ * hwrm_ring_schq_free *
***********************/
-/* hwrm_ring_grp_alloc_input (size:192b/24B) */
-struct hwrm_ring_grp_alloc_input {
+/* hwrm_ring_schq_free_input (size:192b/24B) */
+struct hwrm_ring_schq_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * This value identifies the CR associated with the ring
- * group.
- */
- uint16_t cr;
- /*
- * This value identifies the main RR associated with the ring
- * group.
- */
- uint16_t rr;
- /*
- * This value identifies the aggregation RR associated with
- * the ring group. If this value is 0xFF... (All Fs), then no
- * Aggregation ring will be set.
- */
- uint16_t ar;
- /*
- * This value identifies the statistics context associated
- * with the ring group.
- */
- uint16_t sc;
-} __rte_packed;
-
-/* hwrm_ring_grp_alloc_output (size:128b/16B) */
-struct hwrm_ring_grp_alloc_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /*
- * This is the ring group ID value. Use this value to program
- * the default ring group for the VNIC or as table entries
- * in an RSS/COS context.
- */
- uint32_t ring_group_id;
- uint8_t unused_0[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/**********************
- * hwrm_ring_grp_free *
- **********************/
-
-
-/* hwrm_ring_grp_free_input (size:192b/24B) */
-struct hwrm_ring_grp_free_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* This is the ring group ID value. */
- uint32_t ring_group_id;
- uint8_t unused_0[4];
+ /* Identifies the SCHQ being freed. */
+ uint16_t schq_id;
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_ring_grp_free_output (size:128b/16B) */
-struct hwrm_ring_grp_free_output {
+/* hwrm_ring_schq_free_output (size:128b/16B) */
+struct hwrm_ring_schq_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
UINT32_C(0x1)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
- /* Setting of this flag indicates the applicability to the loopback path. */
+ /*
+ * Setting of this flag indicates the applicability to the loopback
+ * path.
+ */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x2)
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
UINT32_C(0x4)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
UINT32_C(0x2)
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
*/
uint64_t resp_addr;
/*
- * Function ID of the function that is being queried.
- * Only valid for a VF FID queried by the PF.
- */
- uint16_t fid;
- uint8_t unused_0[2];
- /*
- * Maximum number of VLAN entries the firmware is allowed to DMA
- * to vlan_tag_mask_tbl.
- */
- uint32_t max_vlan_entries;
- /*
- * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
- * antispoof table to which firmware will DMA to. Each table
- * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
- * 16-bit VLAN ID, and a 16-bit mask, all in network order to
- * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
- * the mask value should be 0xfff for the 12-bit VLAN ID.
- */
- uint64_t vlan_tag_mask_tbl_addr;
-} __rte_packed;
-
-/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
-struct hwrm_cfa_vlan_antispoof_qcfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
- uint32_t num_vlan_entries;
- uint8_t unused_0[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/********************************
- * hwrm_cfa_tunnel_filter_alloc *
- ********************************/
-
-
-/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
-struct hwrm_cfa_tunnel_filter_alloc_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Function ID of the function that is being queried.
+ * Only valid for a VF FID queried by the PF.
+ */
+ uint16_t fid;
+ uint8_t unused_0[2];
+ /*
+ * Maximum number of VLAN entries the firmware is allowed to DMA
+ * to vlan_tag_mask_tbl.
+ */
+ uint32_t max_vlan_entries;
+ /*
+ * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
+ * antispoof table to which firmware will DMA to. Each table
+ * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
+ * 16-bit VLAN ID, and a 16-bit mask, all in network order to
+ * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
+ * the mask value should be 0xfff for the 12-bit VLAN ID.
+ */
+ uint64_t vlan_tag_mask_tbl_addr;
+} __rte_packed;
+
+/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
+struct hwrm_cfa_vlan_antispoof_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
+ uint32_t num_vlan_entries;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/********************************
+ * hwrm_cfa_tunnel_filter_alloc *
+ ********************************/
+
+
+/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
+struct hwrm_cfa_tunnel_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Setting of this flag indicates the applicability to the loopback
+ * path.
*/
- uint64_t resp_addr;
- uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
uint32_t enables;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
/* Tunnel alloc flags. */
uint8_t flags;
- /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
+ /*
+ * Setting of this flag indicates modify existing redirect tunnel
+ * to new destination function ID.
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
UINT32_C(0x1)
uint8_t unused_0[4];
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint16_t dst_port;
/* VXLAN Network Identifier. */
uint32_t vni;
- /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
+ /*
+ * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
+ * header.
+ */
uint8_t hdr_rsvd0[3];
/* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
uint8_t hdr_rsvd1;
*/
uint64_t resp_addr;
uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
+ /*
+ * Setting of this flag indicates the applicability to the loopback
+ * path.
+ */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
/*
- * Setting of this flag indicates this encap record is external encap record.
- * Resetting of this flag indicates this flag is internal encap record and
- * this is the default setting.
+ * Setting of this flag indicates this encap record is external
+ * encap record. Resetting of this flag indicates this flag is
+ * internal encap record and this is the default setting.
*/
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
UINT32_C(0x2)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
*/
uint64_t resp_addr;
uint32_t flags;
- /* Setting of this flag indicates the applicability to the loopback path. */
+ /*
+ * Setting of this flag indicates the applicability to the loopback
+ * path.
+ */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
UINT32_C(0x2)
/*
- * Setting of this flag indicates that a meter is expected to be attached
- * to this flow. This hint can be used when choosing the action record
- * format required for the flow.
+ * Setting of this flag indicates that a meter is expected to be
+ * attached to this flow. This hint can be used when choosing the
+ * action record format required for the flow.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
/*
- * Setting of this flag indicates that the dst_id field contains function ID.
- * If this is not set it indicates dest_id is VNIC or VPORT.
+ * Setting of this flag indicates that the dst_id field contains
+ * function ID. If this is not set it indicates dest_id is VNIC
+ * or VPORT.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
UINT32_C(0x8)
/*
- * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
- * If this is not set it indicates no specific arp opcode matching.
+ * Setting of this flag indicates match on arp reply when ethertype
+ * is 0x0806. If this is not set it indicates no specific arp opcode
+ * matching.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
UINT32_C(0x10)
/*
- * Setting of this flag indicates that the dst_id field contains RFS ring
- * table index. If this is not set it indicates dst_id is VNIC or VPORT
- * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
- * the same time.
+ * Setting of this flag indicates that the dst_id field contains RFS
+ * ring table index. If this is not set it indicates dst_id is VNIC
+ * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
+ * can’t be set at the same time.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
UINT32_C(0x20)
+ /*
+ * Setting of this flag indicates that when the ntuple filter is
+ * created, the L2 context should not be used in the filter. This
+ * allows packet from different L2 contexts to match and be directed
+ * to the same destination.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \
+ UINT32_C(0x40)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint32_t flags;
/*
* Setting this bit to 1 indicates that dest_id field contains FID.
- * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ * Setting this to 0 indicates that dest_id field contains VNIC or
+ * VPORT.
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
UINT32_C(0x1)
/*
* Setting of this flag indicates that the new_dst_id field contains
- * RFS ring table index. If this is not set it indicates new_dst_id is
- * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
- * can’t be set at the same time.
+ * RFS ring table index. If this is not set it indicates new_dst_id
+ * is VNIC or VPORT or function ID. Note dest_fid and
+ * dest_rfs_ring_idx can’t be set at the same time.
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates that when the ntuple filter is
+ * created, the L2 context should not be used in the filter. This
+ * allows packet from different L2 contexts to match and be directed
+ * to the same destination.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \
+ UINT32_C(0x4)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
/*
- * Setting of this flag indicates enabling of a byte counter for a given
- * flow.
+ * Setting of this flag indicates enabling of a byte counter for a
+ * given flow.
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
/*
- * Setting of this flag indicates enabling of a packet counter for a given
- * flow.
+ * Setting of this flag indicates enabling of a packet counter for a
+ * given flow.
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
- /* Setting of this flag indicates de-capsulation action for the given flow. */
+ /*
+ * Setting of this flag indicates de-capsulation action for the
+ * given flow.
+ */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
- /* Setting of this flag indicates encapsulation action for the given flow. */
+ /*
+ * Setting of this flag indicates encapsulation action for the
+ * given flow.
+ */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
/*
- * Setting of this flag indicates that a meter is expected to be attached
- * to this flow. This hint can be used when choosing the action record
- * format required for the flow.
+ * Setting of this flag indicates that a meter is expected to be
+ * attached to this flow. This hint can be used when choosing the
+ * action record format required for the flow.
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
uint32_t enables;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint16_t resp_len;
uint32_t flags;
/*
- * Enumeration denoting the clock at which the Meter is running with.
- * This enumeration is used for resources that are similar for both
- * TX and RX paths of the chip.
+ * Enumeration denoting the clock at which the Meter is running
+ * with. This enumeration is used for resources that are similar
+ * for both TX and RX paths of the chip.
*/
#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
/*
- * This value identifies the ID of a meter instance that needs to be updated with
- * a new meter profile specified in this command.
+ * This value identifies the ID of a meter instance that needs to be
+ * updated with a new meter profile specified in this command.
*/
uint16_t meter_instance_id;
uint8_t unused_1[2];
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
*/
uint16_t dst_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * If set, this value shall represent the L2 context that matches the
+ * L2 information of the decap filter.
*/
uint16_t l2_ctxt_ref_id;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
+ * when set to 1, indicates TX flow offload for function specified
+ * in src_fid and the dst_fid should be set to invalid value. To
+ * indicate a VM to VM flow, both of the path_tx and path_rx flags
+ * need to be set. For virtio vSwitch offload case, the src_fid and
+ * dst_fid is set to the same fid value. For the SRIOV vSwitch
+ * offload case, the src_fid and dst_fid must be set to the same VF
+ * FID belong to the children VFs of the same PF to indicate VM to
+ * VM flow.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
+ * when set to 1, indicates RX flow offload for function specified
+ * in dst_fid and the src_fid should be set to invalid value.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
+ * header is required and the VXLAN VNI value is stored in the first
+ * 24 bits of the dmac field. This flag is only valid when the flow
+ * direction is RX.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
- /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ /*
+ * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
+ * field.
+ */
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
UINT32_C(0x200)
/*
uint32_t tunnel_handle;
uint16_t action_flags;
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
UINT32_C(0x1)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
UINT32_C(0x2)
/*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
+ * Setting of this flag indicates drop action. If this flag is not
+ * set, then it should be considered accept action.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
UINT32_C(0x4)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
+ * If set to 1 and flow direction is TX, it indicates decap of L2
+ * header and encap of tunnel header. If set to 1 and flow direction
+ * is RX, it indicates decap of tunnel header and encap L2 header.
+ * The type of tunnel is specified in the tunnel_type field.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
/*
- * If set to 1 an attempt will be made to try to offload this flow to the
- * most optimal flow table resource. If set to 0, the flow will be
- * placed to the default flow table resource.
+ * If set to 1 an attempt will be made to try to offload this flow
+ * to the most optimal flow table resource. If set to 0, the flow
+ * will be placed to the default flow table resource.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
/*
- * If set to 1 there will be no attempt to allocate an on-chip try to
- * offload this flow. If set to 0, which will keep compatibility with the
- * older drivers, will cause the FW to attempt to allocate an on-chip flow
- * counter for the newly created flow. This will keep the existing behavior
- * with EM flows which always had an associated flow counter.
+ * If set to 1 there will be no attempt to allocate an on-chip try
+ * to offload this flow. If set to 0, which will keep compatibility
+ * with the older drivers, will cause the FW to attempt to allocate
+ * an on-chip flow counter for the newly created flow. This will
+ * keep the existing behavior with EM flows which always had an
+ * associated flow counter.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
UINT32_C(0x2000)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
/* No more wild-card TCAM */
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
- /* Hash collsion in exact match tables */
+ /* Hash collision in exact match tables */
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
/* Key is already installed */
#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
UINT32_C(0x10)
/*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header.
+ * If set to 1 and flow direction is TX, it indicates decap of L2
+ * header and encap of tunnel header. If set to 1 and flow direction
+ * is RX, it indicates decap of tunnel header and encap L2 header.
*/
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x20)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
UINT32_C(0xb)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
/* Any tunneled traffic */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* flags is 32 b */
uint32_t flags;
/*
- * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
- * fields are valid. The flow flush operation should only flush the flows from the
- * flow table specified. This flag is set to 0 by older driver. For older firmware,
- * setting this flag has no effect.
+ * Set to 1 to indicate the page size, page layers, and
+ * flow_handle_table_dma_addr fields are valid. The flow flush
+ * operation should only flush the flows from the flow table
+ * specified. This flag is set to 0 by older driver. For older
+ * firmware, setting this flag has no effect.
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
UINT32_C(0x1)
/*
- * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
- * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
- * setting this flag has no effect.
+ * Set to 1 to indicate flow flush operation to cleanup all the
+ * flows, meters, CFA context memory tables etc. This flag is set to
+ * 0 by older driver. For older firmware, setting this flag has no
+ * effect.
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
/*
- * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
- * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
+ * Set to 1 to indicate flow flush operation to cleanup all the
+ * flows by the caller. This flag is set to 0 by older driver. For
+ * older firmware, setting this flag has no effect.
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
UINT32_C(0x4)
- /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ /*
+ * Set to 1 to indicate the flow counter IDs are included in the
+ * flow table.
+ */
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
UINT32_C(0x8000000)
/*
- * This specifies the size of flow handle entries provided by the driver
- * in the flow table specified below. Only two flow handle size enums are defined.
+ * This specifies the size of flow handle entries provided by the
+ * driver in the flow table specified below. Only two flow handle
+ * size enums are defined.
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
UINT32_C(0xc0000000)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
/* PBL pointer points to PTE table. */
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
- /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ /*
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
+ */
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint64_t resp_addr;
/* The bit field to enable per flow aging configuration. */
uint16_t enables;
- /* This bit must be '1' for the tcp flow timer field to be configured */
+ /*
+ * This bit must be '1' for the tcp flow timer field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
UINT32_C(0x1)
- /* This bit must be '1' for the tcp finish timer field to be configured */
+ /*
+ * This bit must be '1' for the tcp finish timer field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
UINT32_C(0x2)
- /* This bit must be '1' for the udp flow timer field to be configured */
+ /*
+ * This bit must be '1' for the udp flow timer field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* This bit must be '1' for the eem dma interval field to be configured */
+ /*
+ * This bit must be '1' for the eem dma interval field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
UINT32_C(0x8)
- /* This bit must be '1' for the eem notice interval field to be configured */
+ /*
+ * This bit must be '1' for the eem notice interval field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
UINT32_C(0x10)
- /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ /*
+ * This bit must be '1' for the eem context memory maximum entries
+ * field to be configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
UINT32_C(0x20)
- /* This bit must be '1' for the eem context memory ID field to be configured */
+ /*
+ * This bit must be '1' for the eem context memory ID field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
UINT32_C(0x40)
- /* This bit must be '1' for the eem context memory type field to be configured */
+ /*
+ * This bit must be '1' for the eem context memory type field to be
+ * configured
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
UINT32_C(0x80)
uint8_t flags;
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
- /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ /*
+ * Enumeration denoting the enable, disable eem flow aging
+ * configuration.
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
/* tx path */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
- /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ /*
+ * The flow aging timer for all TCP flows, the unit is 100
+ * milliseconds.
+ */
uint32_t tcp_flow_timer;
- /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ /*
+ * The TCP finished timer for all TCP flows, the unit is 100
+ * milliseconds.
+ */
uint32_t tcp_fin_timer;
- /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ /*
+ * The flow aging timer for all UDP flows, the unit is 100
+ * milliseconds.
+ */
uint32_t udp_flow_timer;
- /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ /*
+ * The interval to dma eem ejection data to host memory, the unit is
+ * milliseconds.
+ */
uint16_t eem_dma_interval;
- /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ /*
+ * The interval to notify driver to read the eem ejection data, the
+ * unit is milliseconds.
+ */
uint16_t eem_notice_interval;
/* The maximum entries number in the eem context memory. */
uint32_t eem_ctx_max_entries;
/* The context memory ID for eem flow aging. */
uint16_t eem_ctx_id;
uint16_t eem_ctx_mem_type;
- /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ /*
+ * The content of context memory is eem ejection data, the size of
+ * each entry is 4 bytes.
+ */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
UINT32_C(0x0)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /*
+ * The direction for the flow aging configuration, 1 is rx path, 2 is
+ * tx path.
+ */
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ /*
+ * The current flow aging timer for all TCP flows, the unit is 100
+ * millisecond.
+ */
uint32_t tcp_flow_timer;
- /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ /*
+ * The current TCP finished timer for all TCP flows, the unit is 100
+ * millisecond.
+ */
uint32_t tcp_fin_timer;
- /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ /*
+ * The current flow aging timer for all UDP flows, the unit is 100
+ * millisecond.
+ */
uint32_t udp_flow_timer;
- /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ /*
+ * The interval to dma eem ejection data to host memory, the unit is
+ * milliseconds.
+ */
uint16_t eem_dma_interval;
- /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ /*
+ * The interval to notify driver to read the eem ejection data, the
+ * unit is milliseconds.
+ */
uint16_t eem_notice_interval;
/* The maximum entries number in the eem context memory. */
uint32_t eem_ctx_max_entries;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
+
+
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The direction for the flow aging configuration, 1 is rx path, 2 is
+ * tx path.
+ */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
+} __rte_packed;
+
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * The maximum flow aging timer for all TCP flows, the unit is 100
+ * millisecond.
+ */
+ uint32_t max_tcp_flow_timer;
+ /*
+ * The maximum TCP finished timer for all TCP flows, the unit is 100
+ * millisecond.
+ */
+ uint32_t max_tcp_fin_timer;
+ /*
+ * The maximum flow aging timer for all UDP flows, the unit is 100
+ * millisecond.
+ */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
+
+
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /*
+ * The port 0 RX action record ID for TX TCP flag packets from
+ * loopback path.
+ */
+ uint16_t tx_ar_id_port0;
+ /*
+ * The port 1 RX action record ID for TX TCP flag packets from
+ * loopback path.
+ */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_cfa_vf_pair_alloc *
+ **************************/
+
+
+/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
+struct hwrm_cfa_vf_pair_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_a_id;
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_b_id;
+ uint8_t unused_0[4];
+ /* VF Pair name (32 byte string). */
+ char pair_name[32];
+} __rte_packed;
+
+/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
+struct hwrm_cfa_vf_pair_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_cfa_vf_pair_free *
+ *************************/
+
+
+/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
+struct hwrm_cfa_vf_pair_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* VF Pair name (32 byte string). */
+ char pair_name[32];
+} __rte_packed;
+
+/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
+struct hwrm_cfa_vf_pair_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_cfa_vf_pair_info *
+ *************************/
+
+
+/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_vf_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* vf pair table index. */
+ uint16_t vf_pair_index;
+ uint8_t unused_0[2];
+ /* VF Pair name (32 byte string). */
+ char vf_pair_name[32];
+} __rte_packed;
+
+/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
+struct hwrm_cfa_vf_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* vf pair table index. */
+ uint16_t next_vf_pair_index;
+ /* vf pair member a's vf_fid. */
+ uint16_t vf_a_fid;
+ /* vf pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* vf pair member b's vf_fid. */
+ uint16_t vf_b_fid;
+ /* vf pair member a's Linux logical VF number. */
+ uint16_t vf_b_index;
+ /* vf pair state. */
+ uint8_t pair_state;
+ /* Pair has been allocated */
+ #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
+ /* Both pair members are active */
+ #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
+ #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
+ HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
+ uint8_t unused_0[5];
+ /* VF Pair name (32 byte string). */
+ char pair_name[32];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_cfa_pair_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_pair_alloc_input (size:576b/72B) */
+struct hwrm_cfa_pair_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+ * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+ */
+ uint16_t pair_mode;
+ /* Pair between VF on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
+ UINT32_C(0x0)
+ /* Pair between REP on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
+ UINT32_C(0x1)
+ /* Pair between REP on local host with REP on specified host. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
+ UINT32_C(0x2)
+ /* Pair for the proxy interface. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
+ UINT32_C(0x3)
+ /* Pair for the PF interface. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
+ UINT32_C(0x4)
+ /* Modify existing rep2fn pair and move pair to new PF. */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
+ UINT32_C(0x5)
+ /*
+ * Modify existing rep2fn pairs paired with same PF and move pairs
+ * to new PF.
+ */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
+ UINT32_C(0x6)
+ /*
+ * Truflow pair between REP on local host with PF or VF on specified
+ * host.
+ */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
+ UINT32_C(0x7)
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
+ HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_a_id;
+ /* Logical Host (0xff-local host). */
+ uint8_t host_b_id;
+ /* Logical PF (0xff-PF for command channel). */
+ uint8_t pf_b_id;
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_b_id;
+ /* Loopback port (0xff-internal loopback), valid for mode-3. */
+ uint8_t port_id;
+ /* Priority used for encap of loopback packets valid for mode-3. */
+ uint8_t pri;
+ /* New PF for rep2fn modify, valid for mode 5. */
+ uint16_t new_pf_fid;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the q_ab field to be
+ * configured.
+ */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the q_ba field to be
+ * configured.
+ */
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the fc_ab field to be
+ * configured.
*/
- uint8_t valid;
-} __rte_packed;
-
-/*****************************
- * hwrm_cfa_flow_aging_qcaps *
- *****************************/
-
-
-/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
-struct hwrm_cfa_flow_aging_qcaps_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This bit must be '1' for the fc_ba field to be
+ * configured.
*/
- uint16_t cmpl_ring;
+ #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
+ /* VF Pair name (32 byte string). */
+ char pair_name[32];
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * The q_ab value specifies the logical index of the TX/RX CoS
+ * queue to be assigned for traffic in the A to B direction of
+ * the interface pair. The default value is 0.
*/
- uint16_t seq_id;
+ uint8_t q_ab;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * The q_ba value specifies the logical index of the TX/RX CoS
+ * queue to be assigned for traffic in the B to A direction of
+ * the interface pair. The default value is 1.
*/
- uint16_t target_id;
+ uint8_t q_ba;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Specifies whether RX ring flow control is disabled (0) or enabled
+ * (1) in the A to B direction. The default value is 0, meaning that
+ * packets will be dropped when the B-side RX rings are full.
*/
- uint64_t resp_addr;
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
- uint8_t flags;
- /* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* tx path */
- #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* rx path */
- #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
- uint8_t unused_0[7];
+ uint8_t fc_ab;
+ /*
+ * Specifies whether RX ring flow control is disabled (0) or enabled
+ * (1) in the B to A direction. The default value is 1, meaning that
+ * the RX CoS queue will be flow controlled when the A-side RX rings
+ * are full.
+ */
+ uint8_t fc_ba;
+ uint8_t unused_1[4];
} __rte_packed;
-/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
-struct hwrm_cfa_flow_aging_qcaps_output {
+/* hwrm_cfa_pair_alloc_output (size:192b/24B) */
+struct hwrm_cfa_pair_alloc_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
- uint32_t max_tcp_flow_timer;
- /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
- uint32_t max_tcp_fin_timer;
- /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
- uint32_t max_udp_flow_timer;
- /* The maximum aging flows that HW can support. */
- uint32_t max_aging_flows;
+ /* Only valid for modes 1 and 2. */
+ uint16_t rx_cfa_code_a;
+ /* Only valid for modes 1 and 2. */
+ uint16_t tx_cfa_action_a;
+ /* Only valid for mode 2. */
+ uint16_t rx_cfa_code_b;
+ /* Only valid for mode 2. */
+ uint16_t tx_cfa_action_b;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/**********************************
- * hwrm_cfa_tcp_flag_process_qcfg *
- **********************************/
+/**********************
+ * hwrm_cfa_pair_free *
+ **********************/
-/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
-struct hwrm_cfa_tcp_flag_process_qcfg_input {
+/* hwrm_cfa_pair_free_input (size:448b/56B) */
+struct hwrm_cfa_pair_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* VF Pair name (32 byte string). */
+ char pair_name[32];
+ /* Logical PF (0xff-PF for command channel). */
+ uint8_t pf_b_id;
+ uint8_t unused_0[3];
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_id;
+ /*
+ * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+ * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+ */
+ uint16_t pair_mode;
+ /* Pair between VF on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
+ /* Pair between REP on local host with PF or VF on specified host. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
+ /* Pair between REP on local host with REP on specified host. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
+ /* Pair for the proxy interface. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
+ /* Pair for the PF interface. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
+ /* Modify existing rep2fn pair and move pair to new PF. */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
+ /*
+ * Modify existing rep2fn pairs paired with same PF and move pairs
+ * to new PF.
+ */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
+ /*
+ * Truflow pair between REP on local host with PF or VF on
+ * specified host.
+ */
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
+ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
+ HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
} __rte_packed;
-/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
-struct hwrm_cfa_tcp_flag_process_qcfg_output {
+/* hwrm_cfa_pair_free_output (size:128b/16B) */
+struct hwrm_cfa_pair_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* The port 0 RX mirror action record ID. */
- uint16_t rx_ar_id_port0;
- /* The port 1 RX mirror action record ID. */
- uint16_t rx_ar_id_port1;
- /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
- uint16_t tx_ar_id_port0;
- /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
- uint16_t tx_ar_id_port1;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_cfa_vfr_alloc *
+ **********************/
+
+
+/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
+struct hwrm_cfa_vfr_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_id;
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint16_t reserved;
+ uint8_t unused_0[4];
+ /* VF Representor name (32 byte string). */
+ char vfr_name[32];
+} __rte_packed;
+
+/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
+struct hwrm_cfa_vfr_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_cfa_vfr_free *
+ *********************/
+
+
+/* hwrm_cfa_vfr_free_input (size:448b/56B) */
+struct hwrm_cfa_vfr_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* VF Representor name (32 byte string). */
+ char vfr_name[32];
+ /* Logical VF number (range: 0 -> MAX_VFS -1). */
+ uint16_t vf_id;
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint16_t reserved;
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_cfa_vfr_free_output (size:128b/16B) */
+struct hwrm_cfa_vfr_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ /*
+ * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
+ * datagram payload
+ */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
UINT32_C(0x400)
/* Any tunneled traffic */
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ /*
+ * IPV6 over virtual eXtensible Local Area Network with GPE header
+ * (IPV6oVXLANGPE)
+ */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
UINT32_C(0x2000)
uint8_t unused_0[3];
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
/* PBL pointer points to PTE table. */
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
- /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ /*
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
+ */
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * Id/Handle to the recently register context memory. This handle is passed
- * to the CFA feature.
+ * Id/Handle to the recently register context memory. This handle is
+ * passed to the CFA feature.
*/
uint16_t ctx_id;
uint8_t unused_0[5];
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
*/
uint64_t resp_addr;
/*
- * Id/Handle to the recently register context memory. This handle is passed
- * to the CFA feature.
+ * Id/Handle to the recently register context memory. This handle is
+ * passed to the CFA feature.
*/
uint16_t ctx_id;
uint8_t unused_0[6];
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is
+ * passed to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing to PTE
+ * tables.
+ */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Indicates the maximum number of context memory which can be
+ * registered.
+ */
+ uint16_t max_entries;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_cfa_counter_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_counter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
+struct hwrm_cfa_counter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /* Enumeration denoting the supported CFA counter format. */
+ #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
+ UINT32_C(0x1)
+ /* CFA counter types are not supported. */
+ #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
+ UINT32_C(0x0)
+ /* 64-bit packet counters followed by 64-bit byte counters format. */
+ #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
+ UINT32_C(0x1)
+ #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
+ HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
+ uint32_t unused_0;
+ /*
+ * Minimum guaranteed number of flow counters supported for this
+ * function, in RX direction.
+ */
+ uint32_t min_rx_fc;
+ /*
+ * Maximum non-guaranteed number of flow counters supported for this
+ * function, in RX direction.
+ */
+ uint32_t max_rx_fc;
+ /*
+ * Minimum guaranteed number of flow counters supported for this
+ * function, in TX direction.
+ */
+ uint32_t min_tx_fc;
+ /*
+ * Maximum non-guaranteed number of flow counters supported for this
+ * function, in TX direction.
+ */
+ uint32_t max_tx_fc;
+ /*
+ * Minimum guaranteed number of extension flow counters supported for
+ * this function, in RX direction.
+ */
+ uint32_t min_rx_efc;
+ /*
+ * Maximum non-guaranteed number of extension flow counters supported
+ * for this function, in RX direction.
+ */
+ uint32_t max_rx_efc;
+ /*
+ * Minimum guaranteed number of extension flow counters supported for
+ * this function, in TX direction.
+ */
+ uint32_t min_tx_efc;
+ /*
+ * Maximum non-guaranteed number of extension flow counters supported
+ * for this function, in TX direction.
+ */
+ uint32_t max_tx_efc;
+ /*
+ * Minimum guaranteed number of meter drop counters supported for
+ * this function, in RX direction.
+ */
+ uint32_t min_rx_mdc;
+ /*
+ * Maximum non-guaranteed number of meter drop counters supported for
+ * this function, in RX direction.
+ */
+ uint32_t max_rx_mdc;
+ /*
+ * Minimum guaranteed number of meter drop counters supported for this
+ * function, in TX direction.
+ */
+ uint32_t min_tx_mdc;
+ /*
+ * Maximum non-guaranteed number of meter drop counters supported for
+ * this function, in TX direction.
+ */
+ uint32_t max_tx_mdc;
+ /*
+ * Maximum guaranteed number of flow counters which can be used during
+ * flow alloc.
+ */
+ uint32_t max_flow_alloc_fc;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/*************************
- * hwrm_cfa_ctx_mem_qctx *
- *************************/
+/************************
+ * hwrm_cfa_counter_cfg *
+ ************************/
-/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
-struct hwrm_cfa_ctx_mem_qctx_input {
+/* hwrm_cfa_counter_cfg_input (size:256b/32B) */
+struct hwrm_cfa_counter_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Id/Handle to the recently register context memory. This handle is passed
- * to the CFA feature.
- */
+ uint16_t flags;
+ /* Enumeration denoting the configuration mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
+ UINT32_C(0x1)
+ /* Disable the configuration mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
+ UINT32_C(0x0)
+ /* Enable the configuration mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
+ UINT32_C(0x1)
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
+ HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
+ UINT32_C(0x2)
+ /* Tx path. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
+ (UINT32_C(0x0) << 1)
+ /* Rx path. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the data transfer mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
+ UINT32_C(0xc)
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
+ /* Push mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
+ (UINT32_C(0x0) << 2)
+ /* Pull mode. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
+ (UINT32_C(0x1) << 2)
+ /* Pull on async update. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
+ (UINT32_C(0x2) << 2)
+ #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
+ HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
+ uint16_t counter_type;
+ /* Flow counters. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
+ /* Extended flow counters. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
+ /* Meter drop counters. */
+ #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
+ #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
+ HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
+ /* Ctx memory handle to be used for the counter. */
uint16_t ctx_id;
- uint8_t unused_0[6];
+ /* Counter update cadence hint (only in Push mode). */
+ uint16_t update_tmr_ms;
+ /* Total number of entries. */
+ uint32_t num_entries;
+ uint32_t unused_0;
} __rte_packed;
-/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
-struct hwrm_cfa_ctx_mem_qctx_output {
+/* hwrm_cfa_counter_cfg_output (size:128b/16B) */
+struct hwrm_cfa_counter_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint16_t flags;
- /* Counter PBL indirect levels. */
- uint8_t page_level;
- /* PBL pointer is physical start address. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
- /* PBL pointer points to PTE table. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
- /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
- HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
- /* Page size. */
- uint8_t page_size;
- /* 4KB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
- /* 8KB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
- /* 64KB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
- /* 256KB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
- /* 1MB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
- /* 2MB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
- /* 4MB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
- /* 1GB page size. */
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
- #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
- HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
- uint8_t unused_0[4];
- /* Pointer to the PBL, or PDL depending on number of levels */
- uint64_t page_dir;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/**************************
- * hwrm_cfa_ctx_mem_qcaps *
- **************************/
+/***************************
+ * hwrm_cfa_counter_qstats *
+ ***************************/
-/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_qcaps_input {
+/* hwrm_cfa_counter_qstats_input (size:320b/40B) */
+struct hwrm_cfa_counter_qstats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ uint16_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* Tx path. */
+ #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* Rx path. */
+ #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
+ uint16_t counter_type;
+ uint16_t input_flow_ctx_id;
+ uint16_t num_entries;
+ uint16_t delta_time_ms;
+ uint16_t meter_instance_id;
+ uint16_t mdc_ctx_id;
+ uint8_t unused_0[2];
+ uint64_t expected_count;
} __rte_packed;
-/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
-struct hwrm_cfa_ctx_mem_qcaps_output {
+/* hwrm_cfa_counter_qstats_output (size:128b/16B) */
+struct hwrm_cfa_counter_qstats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Indicates the maximum number of context memory which can be registered. */
- uint16_t max_entries;
- uint8_t unused_0[5];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
/*
- * When set to 1, indicates the the FW supports the Centralized
+ * When set to 1, indicates the FW supports the Centralized
* Memory Model. The concept designates one entity for the
* memory allocation while all others ‘subscribe’ to it.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
UINT32_C(0x4)
/*
- * When set to 1, indicates the the FW supports the Detached
+ * When set to 1, indicates the FW supports the Detached
* Centralized Memory Model. The memory is allocated and managed
* as a separate entity. All PFs and VFs will be granted direct
* or semi-direct access to the allocated memory while none of
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
UINT32_C(0x8)
/*
- * If set to 1, then FID table used for implicit flow flush is supported.
- * If set to 0, then FID table used for implicit flow flush is not supported.
+ * If set to 1, then FID table used for implicit flow flush is
+ * supported.
+ * If set to 0, then FID table used for implicit flow flush is
+ * not supported.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
UINT32_C(0x10)
/*
- * The maximum number of entries supported by EEM. When configuring the host memory
- * the number of numbers of entries that can supported are -
- * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
- * Any value that are not these values, the FW will round down to the closest support
- * number of entries.
+ * The maximum number of entries supported by EEM. When configuring
+ * the host memory, the number of numbers of entries that can
+ * supported are:
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
+ * entries.
+ * Any value that are not these values, the FW will round down to the
+ * closest support number of entries.
*/
uint32_t max_entries_supported;
/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint16_t group_id;
uint16_t unused_0;
/*
- * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
- * RECORD, EFC all have the same number of entries and all tables will be configured
- * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ * Configured EEM with the given number of entries. All the EEM tables
+ * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
+ * tables will be configured using this value. Current minimum value
+ * is 32k. Current maximum value is 128M.
*/
uint32_t num_entries;
uint32_t unused_1;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __rte_packed;
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete
+ * operation through HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow
+ * batch delete operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all
+ * operation through HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as
+ * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as
+ * dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
+ UINT32_C(0x10)
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
+ UINT32_C(0x20)
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
+ UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic
+ * allocation of an on-chip flow counter which can be used for EEM
+ * flows. Value of 0 indicates firmware does not support the dynamic
+ * allocation of an on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, firmware is capable of supporting ARP ethertype as
+ * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
+ * RX direction. By default, this flag should be 0 for older version
+ * of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
+ UINT32_C(0x1000)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
+ * command. Value of 0 indicates firmware does not support
+ * rfs_ring_tbl_idx in dst_id field.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ UINT32_C(0x2000)
+ /*
+ * If set to 1, firmware is capable of supporting IPv4/IPv6 as
+ * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
+ * direction. By default, this flag should be 0 for older version
+ * of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
+ UINT32_C(0x4000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
+ * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
+ UINT32_C(0x8000)
+ /*
+ * If set to 1, firmware is capable of supporting L2/ROCE as
+ * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
+ * By default, this flag should be 0 for older version of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
+ UINT32_C(0x10000)
+ /*
+ * If set to 1, firmware is capable of HW LAG. This bit is only
+ * advertised if the calling function is a PAXC function.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \
+ UINT32_C(0x20000)
+ /*
+ * If set to 1, firmware is capable installing ntuple rules without
+ * additional classification on the L2 Context.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \
+ UINT32_C(0x40000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __rte_packed;
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************************
+ * hwrm_cfa_lag_group_member_rgtr *
+ **********************************/
+
+
+/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */
+struct hwrm_cfa_lag_group_member_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t mode;
/*
- * When set to 1, indicates the host memory which is passed will be
- * used for the TX flow offload function specified in fid.
- * Note if this bit is set then the path_rx bit can't be set.
+ * Transmit only on the active port. Automatically failover
+ * to backup port.
*/
- #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
- /*
- * When set to 1, indicates the host memory which is passed will be
- * used for the RX flow offload function specified in fid.
- * Note if this bit is set then the path_tx bit can't be set.
- */
- #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
- uint16_t unused_0;
- /* The number of EEM key table entries to be configured. */
- uint16_t op;
- /* This value is reserved and should not be used. */
- #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
- /*
- * To properly stop EEM and ensure there are no DMA's, the caller
- * must disable EEM for the given PF, using this call. This will
- * safely disable EEM and ensure that all DMA'ed to the
- * keys/records/efc have been completed.
- */
- #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
- /*
- * Once the EEM host memory has been configured, EEM options have
- * been configured. Then the caller should enable EEM for the given
- * PF. Note once this call has been made, then the EEM mechanism
- * will be active and DMA's will occur as packets are processed.
- */
- #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
- /*
- * Clear EEM settings for the given PF so that the register values
- * are reset back to there initial state.
- */
- #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
- #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
- HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
-} __rte_packed;
-
-/* hwrm_cfa_eem_op_output (size:128b/16B) */
-struct hwrm_cfa_eem_op_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/********************************
- * hwrm_cfa_adv_flow_mgnt_qcaps *
- ********************************/
-
-
-/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
-struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \
+ UINT32_C(0x1)
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * Transmit based on packet header ntuple hash. Packet with only
+ * layer 2 headers will hash using the destination MAC, source MAC
+ * and Ethertype fields. Packets with layer 3 (IP) headers will
+ * hash using the destination MAC, source MAC, IP protocol/next
+ * header, source IP address and destination IP address. Packets
+ * with layer 4 (TCP/UDP) headers will hash using the destination
+ * MAC, source MAC, IP protocol/next header, source IP address,
+ * destination IP address, source port and destination port fields.
*/
- uint16_t target_id;
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \
+ UINT32_C(0x2)
+ /* Transmit packets on all specified ports. */
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \
+ UINT32_C(0x3)
+ #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \
+ HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
+ * bit2 = port 2, bit3 = port 4, bit4 = loopback port
*/
- uint64_t resp_addr;
- uint32_t unused_0[4];
+ uint8_t port_bitmap;
+ /* Specify the active port when active-backup mode is specified */
+ uint8_t active_port;
+ uint8_t unused_0[5];
} __rte_packed;
-/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
-struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_lag_group_member_rgtr_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint32_t flags;
- /*
- * Value of 1 to indicate firmware support 16-bit flow handle.
- * Value of 0 to indicate firmware not support 16-bit flow handle.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
- UINT32_C(0x1)
- /*
- * Value of 1 to indicate firmware support 64-bit flow handle.
- * Value of 0 to indicate firmware not support 64-bit flow handle.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
- UINT32_C(0x2)
- /*
- * Value of 1 to indicate firmware support flow batch delete operation through
- * HWRM_CFA_FLOW_FLUSH command.
- * Value of 0 to indicate that the firmware does not support flow batch delete
- * operation.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
- UINT32_C(0x4)
- /*
- * Value of 1 to indicate that the firmware support flow reset all operation through
- * HWRM_CFA_FLOW_FLUSH command.
- * Value of 0 indicates firmware does not support flow reset all operation.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
- UINT32_C(0x8)
- /*
- * Value of 1 to indicate that firmware supports use of FID as dest_id in
- * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
- * Value of 0 indicates firmware does not support use of FID as dest_id.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
- UINT32_C(0x10)
- /*
- * Value of 1 to indicate that firmware supports TX EEM flows.
- * Value of 0 indicates firmware does not support TX EEM flows.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
- UINT32_C(0x20)
- /*
- * Value of 1 to indicate that firmware supports RX EEM flows.
- * Value of 0 indicates firmware does not support RX EEM flows.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
- UINT32_C(0x40)
- /*
- * Value of 1 to indicate that firmware supports the dynamic allocation of an
- * on-chip flow counter which can be used for EEM flows.
- * Value of 0 indicates firmware does not support the dynamic allocation of an
- * on-chip flow counter.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
- UINT32_C(0x80)
- /*
- * Value of 1 to indicate that firmware supports setting of
- * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
- * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
- UINT32_C(0x100)
- /*
- * Value of 1 to indicate that firmware supports untagged matching
- * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
- * indicates firmware does not support untagged matching.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
- UINT32_C(0x200)
- /*
- * Value of 1 to indicate that firmware supports XDP filter. Value
- * of 0 indicates firmware does not support XDP filter.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
- UINT32_C(0x400)
- /*
- * Value of 1 to indicate that the firmware support L2 header source
- * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
- * Value of 0 indicates firmware does not support L2 header source
- * fields matching.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
- UINT32_C(0x800)
- /*
- * If set to 1, firmware is capable of supporting ARP ethertype as
- * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
- * RX direction. By default, this flag should be 0 for older version
- * of firmware.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
- UINT32_C(0x1000)
- /*
- * Value of 1 to indicate that firmware supports setting of
- * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
- * command. Value of 0 indicates firmware does not support
- * rfs_ring_tbl_idx in dst_id field.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
- UINT32_C(0x2000)
- /*
- * If set to 1, firmware is capable of supporting IPv4/IPv6 as
- * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
- * direction. By default, this flag should be 0 for older version
- * of firmware.
- */
- #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
- UINT32_C(0x4000)
- uint8_t unused_0[3];
+ /* lag group ID configured for the function */
+ uint16_t lag_id;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/******************
- * hwrm_cfa_tflib *
- ******************/
+/************************************
+ * hwrm_cfa_lag_group_member_unrgtr *
+ ************************************/
-/* hwrm_cfa_tflib_input (size:1024b/128B) */
-struct hwrm_cfa_tflib_input {
+/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_lag_group_member_unrgtr_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* TFLIB message type. */
- uint16_t tf_type;
- /* TFLIB message subtype. */
- uint16_t tf_subtype;
- /* unused. */
- uint8_t unused0[4];
- /* TFLIB request data. */
- uint32_t tf_req[26];
+ /* lag group ID configured for the function */
+ uint16_t lag_id;
+ uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_cfa_tflib_output (size:5632b/704B) */
-struct hwrm_cfa_tflib_output {
+/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_lag_group_member_unrgtr_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* TFLIB message type. */
- uint16_t tf_type;
- /* TFLIB message subtype. */
- uint16_t tf_subtype;
- /* TFLIB response code */
- uint32_t tf_resp_code;
- /* TFLIB response data. */
- uint32_t tf_resp[170];
- /* unused. */
- uint8_t unused1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
uint64_t resp_addr;
} __rte_packed;
-/* hwrm_tf_version_get_output (size:128b/16B) */
+/* hwrm_tf_version_get_output (size:256b/32B) */
struct hwrm_tf_version_get_output {
/* The specific error status for the command. */
uint16_t error_code;
/* Version Update number. */
uint8_t update;
/* unused. */
- uint8_t unused0[4];
+ uint8_t unused0[5];
+ /*
+ * This field is used to indicate device's capabilities and
+ * configurations.
+ */
+ uint64_t dev_caps_cfg;
+ /* unused. */
+ uint8_t unused1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* the newly created session.
*/
uint32_t fw_session_client_id;
- /* unused. */
- uint32_t unused0;
+ /* This field is used to return the status of fw session to host. */
+ uint32_t flags;
+ /*
+ * Indicates if the shared session has been created. Shared session
+ * should be the first session created ever. Its fw_rm_client_id
+ * should be 1. The AFM session's fw_rm_client_id is 0.
+ */
+ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
+ UINT32_C(0x1)
+ /*
+ * If this bit set to 0, then it indicates the shared session
+ * has been created by another session.
+ */
+ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \
+ UINT32_C(0x0)
+ /*
+ * If this bit is set to 1, then it indicates the shared session
+ * is created by this session.
+ */
+ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \
+ UINT32_C(0x1)
+ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \
+ HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR
/* unused. */
uint8_t unused1[3];
/*
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
* qcaps_size.
*/
uint16_t size;
+ /*
+ * SRAM profile number that sets the partition of SRAM memory
+ * between TF and AFM within the 4 internal memory banks (Thor).
+ */
+ uint8_t sram_profile;
/* unused. */
- uint16_t unused0;
+ uint8_t unused0;
/* unused. */
uint8_t unused1[7];
/*
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
uint8_t valid;
} __rte_packed;
+/*****************************
+ * hwrm_tf_session_resc_info *
+ *****************************/
+
+
+/* hwrm_tf_session_resc_info_input (size:320b/40B) */
+struct hwrm_tf_session_resc_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX
+ /*
+ * Defines the array size of the provided req_addr and
+ * resv_addr array buffers. Should be set to the number of
+ * request entries.
+ */
+ uint16_t req_size;
+ /*
+ * This is the DMA address for the request input data array
+ * buffer. Array is of tf_rm_resc_req_entry type. Size of the
+ * array buffer is provided by the 'req_size' field in this
+ * message.
+ */
+ uint64_t req_addr;
+ /*
+ * This is the DMA address for the resc output data array
+ * buffer. Array is of tf_rm_resc_entry type. Size of the array
+ * buffer is provided by the 'req_size' field in this
+ * message.
+ */
+ uint64_t resc_addr;
+} __rte_packed;
+
+/* hwrm_tf_session_resc_info_output (size:128b/16B) */
+struct hwrm_tf_session_resc_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Size of the returned tf_rm_resc_entry data array. The value
+ * cannot exceed the req_size defined by the input msg. The data
+ * array is returned using the resv_addr specified DMA
+ * address also provided by the input msg.
+ */
+ uint16_t size;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/* TruFlow RM capability of a resource. */
/* tf_rm_resc_req_entry (size:64b/8B) */
struct tf_rm_resc_req_entry {
/* Control flags. */
uint16_t flags;
/* Indicates the flow direction. */
- #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
- #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * When set use the special access register access to clear
+ * the table entry on read.
+ */
+ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
/* unused. */
uint8_t unused0[2];
/*
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
uint8_t valid;
} __rte_packed;
+/**************************
+ * hwrm_tf_ctxt_mem_alloc *
+ **************************/
+
+
+/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
+struct hwrm_tf_ctxt_mem_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Size in KB of memory to be allocated. */
+ uint32_t mem_size;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+} __rte_packed;
+
+/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
+struct hwrm_tf_ctxt_mem_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ /* Size of memory allocated. */
+ uint32_t mem_size;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing
+ * to PTE tables.
+ */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 128KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
+ /* 256KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 512KB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
+ /* 1MB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 8MB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
+ /* 1GB page size. */
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
+ /* unused. */
+ uint8_t unused0;
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_tf_ctxt_mem_free *
+ *************************/
+
+
+/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
+struct hwrm_tf_ctxt_mem_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /*
+ * PBL pointer points to PDE table with each entry pointing
+ * to PTE tables.
+ */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
+ HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 128KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
+ /* 256KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 512KB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
+ /* 1MB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 8MB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
+ /* 1GB page size. */
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
+ HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
+ /* unused. */
+ uint8_t unused0[2];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ /* Size of memory allocated. */
+ uint32_t mem_size;
+ /* unused. */
+ uint8_t unused1[4];
+} __rte_packed;
+
+/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
+struct hwrm_tf_ctxt_mem_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/*************************
* hwrm_tf_ctxt_mem_rgtr *
*************************/
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
/* 64KB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 128KB page size. */
+ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
/* 256KB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 512KB page size. */
+ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
/* 1MB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
/* 2MB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
/* 4MB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 8MB page size. */
+ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
/* 1GB page size. */
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
- /* unused. */
- uint32_t unused0;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
/* Pointer to the PBL, or PDL depending on number of levels */
uint64_t page_dir;
} __rte_packed;
*/
uint16_t ctx_id;
/* unused. */
- uint8_t unused0[6];
+ uint8_t unused0[2];
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
} __rte_packed;
/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
/* When set to 1, all offloaded flows will be sent to EXT EM. */
#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x2)
- /* unused. */
- uint32_t unused0;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
} __rte_packed;
-/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
+/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
struct hwrm_tf_ext_em_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
uint16_t resp_len;
uint32_t flags;
/*
- * When set to 1, indicates the the FW supports the Centralized
+ * When set to 1, indicates the FW supports the Centralized
* Memory Model. The concept designates one entity for the
* memory allocation while all others ‘subscribe’ to it.
*/
#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
UINT32_C(0x1)
/*
- * When set to 1, indicates the the FW supports the Detached
+ * When set to 1, indicates the FW supports the Detached
* Centralized Memory Model. The memory is allocated and managed
* as a separate entity. All PFs and VFs will be granted direct
* or semi-direct access to the allocated memory while none of
*/
#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
UINT32_C(0x2)
+ /* When set to 1, indicates FW support for host based EEM memory. */
+ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
+ UINT32_C(0x4)
+ /* When set to 1, indicates FW support for on-chip based EEM memory. */
+ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
+ UINT32_C(0x8)
/* unused. */
uint32_t unused0;
/* Support flags. */
*/
#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
UINT32_C(0x10)
+ /*
+ * If set to 1, then table scopes are supported.
+ * If set to 0, then table scopes are not supported.
+ */
+ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
+ UINT32_C(0x20)
/*
* The maximum number of entries supported by EXT EM. When
* configuring the host memory the number of numbers of
uint16_t efc_entry_size;
/* The FID size in bytes of each entry in the EXT EM FID tables. */
uint16_t fid_entry_size;
+ /* Maximum number of ctxt mem allocations allowed. */
+ uint32_t max_ctxt_mem_allocs;
+ /*
+ * Maximum number of static buckets that can be assigned to lookup
+ * table scopes.
+ */
+ uint32_t max_static_buckets;
/* unused. */
uint8_t unused1[7];
/*
*********************/
-/* hwrm_tf_ext_em_op_input (size:192b/24B) */
+/* hwrm_tf_ext_em_op_input (size:256b/32B) */
struct hwrm_tf_ext_em_op_input {
/* The HWRM command request type. */
uint16_t req_type;
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
/* unused. */
uint16_t unused1;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* unused. */
+ uint32_t unused2;
} __rte_packed;
/* hwrm_tf_ext_em_op_output (size:128b/16B) */
**********************/
-/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
+/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
struct hwrm_tf_ext_em_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
* maximum value is 128M.
*/
uint32_t num_entries;
- /* unused. */
- uint32_t unused1;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the group_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the flush_interval field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the num_entries field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the key0_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the key1_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the record_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the efc_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the fid_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the action_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the action_tbl_scope field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the lkup_ctx_id field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the lkup_tbl_scope field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the lkup_static_buckets field to be
+ * configured.
+ */
+ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
+ UINT32_C(0x1000)
/* Configured EXT EM with the given context if for KEY0 table. */
uint16_t key0_ctx_id;
/* Configured EXT EM with the given context if for KEY1 table. */
uint16_t efc_ctx_id;
/* Configured EXT EM with the given context if for EFC table. */
uint16_t fid_ctx_id;
+ /* Context id of action table scope. */
+ uint16_t action_ctx_id;
+ /* Table scope id used for action record entries. */
+ uint16_t action_tbl_scope;
+ /* Context id of lookup table scope. */
+ uint16_t lkup_ctx_id;
+ /* Table scope id used for EM lookup entries. */
+ uint16_t lkup_tbl_scope;
/* unused. */
- uint16_t unused2;
+ uint16_t unused1;
+ /*
+ * Number of 32B static buckets to be allocated at the beginning
+ * of table scope.
+ */
+ uint32_t lkup_static_buckets;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
/* unused. */
- uint32_t unused3;
+ uint32_t unused2;
} __rte_packed;
/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
- /* unused. */
- uint32_t unused0;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
} __rte_packed;
-/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
+/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
struct hwrm_tf_ext_em_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
UINT32_C(0x1)
#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
/* Configured EXT EM with the given context if for EFC table. */
uint16_t fid_ctx_id;
/* unused. */
- uint8_t unused0[5];
+ uint16_t unused0;
+ uint32_t supported;
+ /* This bit must be '1' for the group_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the flush_interval field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the num_entries field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
+ UINT32_C(0x4)
+ /* This bit must be '1' for the key0_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the key1_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the record_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the efc_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the fid_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
+ UINT32_C(0x80)
+ /* This bit must be '1' for the action_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
+ UINT32_C(0x100)
+ /* This bit must be '1' for the action_tbl_scope field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
+ UINT32_C(0x200)
+ /* This bit must be '1' for the lkup_ctx_id field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
+ UINT32_C(0x400)
+ /* This bit must be '1' for the lkup_tbl_scope field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
+ UINT32_C(0x800)
+ /* This bit must be '1' for the lkup_static_buckets field is set. */
+ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
+ UINT32_C(0x1000)
+ /*
+ * Group id is used by firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ /* EEM pending cache flush interval in 1/10th of second. */
+ uint8_t flush_interval;
+ /* unused. */
+ uint8_t unused1;
+ /* Context id of action table scope. */
+ uint16_t action_ctx_id;
+ /* Table scope id used for action record entries. */
+ uint16_t action_tbl_scope;
+ /* Context id of lookup table scope. */
+ uint16_t lkup_ctx_id;
+ /* Table scope id used for EM lookup entries. */
+ uint16_t lkup_tbl_scope;
+ /*
+ * Number of 32B static buckets to be allocated at the beginning
+ * of table scope.
+ */
+ uint32_t lkup_static_buckets;
+ /* unused. */
+ uint8_t unused2[7];
/*
* This field is used in Output records to indicate that the
* output is completely written to RAM. This field should be
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
uint32_t unused0;
} __rte_packed;
+/**************************
+ * hwrm_tf_em_hash_insert *
+ **************************/
+
+
+/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
+struct hwrm_tf_em_hash_insert_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware Session Id. */
+ uint32_t fw_session_id;
+ /* Control Flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
+ /* Number of bits in the EM record. */
+ uint16_t em_record_size_bits;
+ /* CRC32 hash of key. */
+ uint32_t key0_hash;
+ /* Lookup3 hash of key. */
+ uint32_t key1_hash;
+ /* Index of EM record. */
+ uint32_t em_record_idx;
+ /* Unused. */
+ uint32_t unused0;
+ /* EM record. */
+ uint64_t em_record[11];
+} __rte_packed;
+
+/* hwrm_tf_em_hash_insert_output (size:128b/16B) */
+struct hwrm_tf_em_hash_insert_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* EM record pointer index. */
+ uint16_t rptr_index;
+ /* EM record offset 0~3. */
+ uint8_t rptr_entry;
+ /* Number of word entries consumed by the key. */
+ uint8_t num_of_entries;
+ /* unused. */
+ uint32_t unused0;
+} __rte_packed;
+
/*********************
* hwrm_tf_em_delete *
*********************/
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
/* Unused0 */
uint16_t unused0;
- /* EM internal flow hanndle. */
+ /* EM internal flow handle. */
uint64_t flow_handle;
/* EM Key value */
uint64_t em_key[8];
uint16_t unused0[3];
} __rte_packed;
+/*******************
+ * hwrm_tf_em_move *
+ *******************/
+
+
+/* hwrm_tf_em_move_input (size:320b/40B) */
+struct hwrm_tf_em_move_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Session Id. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX
+ /* Number of EM entry blocks */
+ uint16_t num_blocks;
+ /* New index for entry */
+ uint32_t new_index;
+ /* Unused */
+ uint32_t unused0;
+ /* EM internal flow handle. */
+ uint64_t flow_handle;
+} __rte_packed;
+
+/* hwrm_tf_em_move_output (size:128b/16B) */
+struct hwrm_tf_em_move_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Index of old entry. */
+ uint16_t em_index;
+ /* unused. */
+ uint16_t unused0[3];
+} __rte_packed;
+
/********************
* hwrm_tf_tcam_set *
********************/
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
/* unused. */
uint8_t unused0[6];
/*
- * TCAM key located at offset 0, mask located at mask_offsec
- * and result at result_offsec for the device.
+ * TCAM key located at offset 0, mask located at mask_offset
+ * and result at result_offset for the device.
*/
uint8_t dev_data[88];
} __rte_packed;
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
+ /* If this bit is set to 1, then it indicates tx flow. */
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
/* unused. */
uint8_t unused0[4];
/*
- * TCAM key located at offset 0, mask located at mask_offsec
- * and result at result_offsec for the device.
+ * TCAM key located at offset 0, mask located at mask_offset
+ * and result at result_offset for the device.
*/
uint8_t dev_data[272];
/* unused. */
/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
uint32_t fw_session_id;
/* Control flags. */
- uint32_t flags;
+ uint32_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
+ /*
+ * TCAM type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Number of TCAM index pairs to be swapped for the device. */
+ uint16_t count;
+ /* unused. */
+ uint16_t unused0;
+ /* TCAM index pairs to be swapped for the device. */
+ uint16_t idx_pairs[48];
+} __rte_packed;
+
+/* hwrm_tf_tcam_move_output (size:128b/16B) */
+struct hwrm_tf_tcam_move_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_tf_tcam_free *
+ *********************/
+
+
+/* hwrm_tf_tcam_free_input (size:1024b/128B) */
+struct hwrm_tf_tcam_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint32_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
+ /*
+ * TCAM type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Number of TCAM index to be deleted for the device. */
+ uint16_t count;
+ /* unused. */
+ uint16_t unused0;
+ /* TCAM index list to be deleted for the device. */
+ uint16_t idx_list[48];
+} __rte_packed;
+
+/* hwrm_tf_tcam_free_output (size:128b/16B) */
+struct hwrm_tf_tcam_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_tf_global_cfg_set *
+ **************************/
+
+
+/* hwrm_tf_global_cfg_set_input (size:448b/56B) */
+struct hwrm_tf_global_cfg_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint32_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
+ /* Global Cfg type */
+ uint32_t type;
+ /* Offset of the type */
+ uint32_t offset;
+ /* Size of the data to set in bytes */
+ uint16_t size;
+ /* unused. */
+ uint8_t unused0[6];
+ /* Data to set */
+ uint8_t data[8];
+ /* Mask of data to set, 0 indicates no mask */
+ uint8_t mask[8];
+} __rte_packed;
+
+/* hwrm_tf_global_cfg_set_output (size:128b/16B) */
+struct hwrm_tf_global_cfg_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_tf_global_cfg_get *
+ **************************/
+
+
+/* hwrm_tf_global_cfg_get_input (size:320b/40B) */
+struct hwrm_tf_global_cfg_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint32_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
+ /* Global Cfg type */
+ uint32_t type;
+ /* Offset of the type */
+ uint32_t offset;
+ /* Size of the data to set in bytes */
+ uint16_t size;
+ /* unused. */
+ uint8_t unused0[6];
+} __rte_packed;
+
+/* hwrm_tf_global_cfg_get_output (size:256b/32B) */
+struct hwrm_tf_global_cfg_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Size of the data read in bytes */
+ uint16_t size;
+ /* unused. */
+ uint8_t unused0[6];
+ /* Data to set */
+ uint8_t data[16];
+} __rte_packed;
+
+/**********************
+ * hwrm_tf_if_tbl_get *
+ **********************/
+
+
+/* hwrm_tf_if_tbl_get_input (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
/* Indicates the flow direction. */
- #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
- #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
- #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
+ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
+ /* Size of the data to set. */
+ uint16_t size;
/*
- * TCAM type of the resource, defined globally in the
+ * Type of the resource, defined globally in the
* hwrm_tf_resc_type enum.
*/
uint32_t type;
- /* Number of TCAM index pairs to be swapped for the device. */
- uint16_t count;
- /* unused. */
+ /* Index of the type to retrieve. */
+ uint32_t index;
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_get_output (size:256b/32B) */
+struct hwrm_tf_if_tbl_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Response code. */
+ uint32_t resp_code;
+ /* Response size. */
+ uint16_t size;
+ /* unused */
uint16_t unused0;
- /* TCAM index pairs to be swapped for the device. */
- uint16_t idx_pairs[48];
+ /* Response data. */
+ uint8_t data[8];
+ /* unused */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
} __rte_packed;
-/* hwrm_tf_tcam_move_output (size:128b/16B) */
-struct hwrm_tf_tcam_move_output {
+/***************************
+ * hwrm_tf_if_tbl_type_set *
+ ***************************/
+
+
+/* hwrm_tf_if_tbl_set_input (size:384b/48B) */
+struct hwrm_tf_if_tbl_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Index of the type to set. */
+ uint32_t index;
+ /* Size of the data to set. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused1[6];
+ /* Data to be set. */
+ uint8_t data[8];
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
+struct hwrm_tf_if_tbl_set_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
/* unused. */
uint8_t unused0[7];
/*
- * This field is used in Output records to indicate that the
- * output is completely written to RAM. This field should be
- * read as '1' to indicate that the output has been
- * completely written. When writing a command completion or
- * response to an internal processor, the order of writes has
- * to be such that this field is written last.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __rte_packed;
-/*********************
- * hwrm_tf_tcam_free *
- *********************/
+/*****************************
+ * hwrm_tf_tbl_type_bulk_get *
+ *****************************/
-/* hwrm_tf_tcam_free_input (size:1024b/128B) */
-struct hwrm_tf_tcam_free_input {
+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
+struct hwrm_tf_tbl_type_bulk_get_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
uint32_t fw_session_id;
/* Control flags. */
- uint32_t flags;
+ uint16_t flags;
/* Indicates the flow direction. */
- #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates that tx flow. */
- #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
- #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
/*
- * TCAM type of the resource, defined globally in the
+ * When set use the special access register access to clear
+ * the table entries on read.
+ */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
* hwrm_tf_resc_type enum.
*/
uint32_t type;
- /* Number of TCAM index to be deleted for the device. */
- uint16_t count;
- /* unused. */
- uint16_t unused0;
- /* TCAM index list to be deleted for the device. */
- uint16_t idx_list[48];
+ /* Starting index of the type to retrieve. */
+ uint32_t start_index;
+ /* Number of entries to retrieve. */
+ uint32_t num_entries;
+ /* Number of entries to retrieve. */
+ uint32_t unused1;
+ /* Host memory where data will be stored. */
+ uint64_t host_addr;
} __rte_packed;
-/* hwrm_tf_tcam_free_output (size:128b/16B) */
-struct hwrm_tf_tcam_free_output {
+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
+struct hwrm_tf_tbl_type_bulk_get_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* unused. */
- uint8_t unused0[7];
+ /* Response code. */
+ uint32_t resp_code;
+ /* Response size. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused0;
/*
- * This field is used in Output records to indicate that the
- * output is completely written to RAM. This field should be
- * read as '1' to indicate that the output has been
- * completely written. When writing a command completion or
- * response to an internal processor, the order of writes has
- * to be such that this field is written last.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __rte_packed;
* support TPA v2, additional TPA related stats exist and can be retrieved
* by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
*/
-/* ctx_hw_stats_ext (size:1344b/168B) */
+/* ctx_hw_stats_ext (size:1408b/176B) */
struct ctx_hw_stats_ext {
/* Number of received unicast packets */
uint64_t rx_ucast_pkts;
uint64_t rx_tpa_bytes;
/* Number of TPA errors */
uint64_t rx_tpa_errors;
+ /* Number of TPA events */
+ uint64_t rx_tpa_events;
} __rte_packed;
/* Periodic Engine statistics context DMA to host. */
uint64_t tx_mcast_pkts;
/* Number of transmitted broadcast packets */
uint64_t tx_bcast_pkts;
- /* Number of transmitted packets with error */
- uint64_t tx_err_pkts;
- /* Number of dropped packets on transmit path */
- uint64_t tx_drop_pkts;
+ /* Number of packets discarded in transmit path */
+ uint64_t tx_discard_pkts;
+ /* Number of packets in transmit path with error */
+ uint64_t tx_error_pkts;
/* Number of transmitted bytes for unicast traffic */
uint64_t tx_ucast_bytes;
/* Number of transmitted bytes for multicast traffic */
uint64_t rx_mcast_pkts;
/* Number of received broadcast packets */
uint64_t rx_bcast_pkts;
- /* Number of received packets with error */
- uint64_t rx_err_pkts;
- /* Number of dropped packets on receive path */
- uint64_t rx_drop_pkts;
+ /* Number of packets discarded in receive path */
+ uint64_t rx_discard_pkts;
+ /* Number of packets in receive path with errors */
+ uint64_t rx_error_pkts;
/* Number of received bytes for unicast traffic */
uint64_t rx_ucast_bytes;
/* Number of received bytes for multicast traffic */
uint8_t unused_0[3];
} __rte_packed;
-/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
+/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
struct hwrm_stat_ext_ctx_query_output {
/* The specific error status for the command. */
uint16_t error_code;
uint64_t rx_tpa_bytes;
/* Number of TPA errors */
uint64_t rx_tpa_errors;
+ /* Number of TPA events */
+ uint64_t rx_tpa_events;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
******************/
-/* hwrm_nvm_write_input (size:384b/48B) */
+/* hwrm_nvm_write_input (size:448b/56B) */
struct hwrm_nvm_write_input {
/* The HWRM command request type. */
uint16_t req_type;
* This is where the source data is.
*/
uint64_t host_src_addr;
- /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
+ /*
+ * The Directory Entry Type (valid values are defined in the
+ * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
+ */
uint16_t dir_type;
/*
* Directory ordinal.
* The 0-based instance of the combined Directory Entry Type and Extension.
*/
uint16_t dir_ordinal;
- /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
+ /*
+ * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file
+ * bnxnvm_defs.h).
+ */
uint16_t dir_ext;
- /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
+ /*
+ * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file
+ * bnxnvm_defs.h).
+ */
uint16_t dir_attr;
/*
- * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
- * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
+ * Length of data to write, in bytes. May be less than or equal to the
+ * allocated size for the directory entry.
+ * The data length stored in the directory entry will be updated to
+ * reflect this value once the write is complete.
*/
uint32_t dir_data_length;
/* Option. */
#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
UINT32_C(0x1)
/*
- * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
+ * This flag indicates the sender wants to modify a continuous
+ * NVRAM area using a batch of this HWRM requests. The
+ * offset of a request must be continuous to the end of previous
+ * request's. Firmware does not update the directory entry until
+ * receiving the last request, which is indicated by the batch_last
+ * flag. This flag is set usually when a sender does not have a
+ * block of memory that is big enough to hold the entire NVRAM
+ * data for send at one time.
+ */
+ #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \
+ UINT32_C(0x2)
+ /*
+ * This flag can be used only when the batch_mode flag is set. It
+ * indicates this request is the last of batch requests.
+ */
+ #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \
+ UINT32_C(0x4)
+ /*
+ * The requested length of the allocated NVM for the item, in bytes.
+ * This value may be greater than or equal to the specified data
+ * length (dir_data_length).
* If this value is less than the specified data length, it will be ignored.
- * The response will contain the actual allocated item length, which may be greater than the requested item length.
- * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
- * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
+ * The response will contain the actual allocated item length,
+ * which may be greater than the requested item length.
+ * The purpose for allocating more than the required number of bytes
+ * for an item's data is to pre-allocate extra storage (padding) to
+ * accommodate the potential future growth of an item (e.g. upgraded
+ * firmware with a size increase, log growth, expanded configuration data).
*/
uint32_t dir_item_length;
+ /*
+ * 32-bit offset of data blob from where data is being written.
+ * Only valid for batch mode. For non-batch writes 'dont care'.
+ */
+ uint32_t offset;
+ /*
+ * Length of data to be written.Should be non-zero.
+ * Only valid for batch mode. For non-batch writes 'dont care'.
+ */
+ uint32_t len;
uint32_t unused_0;
} __rte_packed;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
- * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
+ * Length of the allocated NVM for the item, in bytes. The value may be
+ * greater than or equal to the specified data length or the requested
+ * item length.
+ * The actual item length used when creating a new directory entry will
+ * be a multiple of an NVM block size.
*/
uint32_t dir_item_length;
/* The directory index of the created or modified item. */
uint32_t dir_data_length;
/*
* Firmware version.
- * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
+ * Only valid if the directory entry is for embedded firmware stored
+ * in APE_BIN Format.
*/
uint32_t fw_ver;
/* Directory ordinal. */
uint64_t resp_addr;
} __rte_packed;
-/* hwrm_nvm_get_dev_info_output (size:256b/32B) */
+/* hwrm_nvm_get_dev_info_output (size:640b/80B) */
struct hwrm_nvm_get_dev_info_output {
/* The specific error status for the command. */
uint16_t error_code;
/* Total size, in bytes of the NVRAM device. */
uint32_t nvram_size;
uint32_t reserved_size;
- /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
+ /*
+ * Available size that can be used, in bytes. Available size is the
+ * NVRAM size take away the used size and reserved size.
+ */
uint32_t available_size;
/* This field represents the major version of NVM cfg */
uint8_t nvm_cfg_ver_maj;
uint8_t nvm_cfg_ver_min;
/* This field represents the update version of NVM cfg */
uint8_t nvm_cfg_ver_upd;
+ uint8_t flags;
+ /*
+ * If set to 1, firmware will provide various firmware version
+ * information stored in the flash.
+ */
+ #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
+ UINT32_C(0x1)
+ /*
+ * This field represents the board package name stored in the flash.
+ * (ASCII chars with NULL at the end).
+ */
+ char pkg_name[16];
+ /*
+ * This field represents the major version of HWRM firmware, stored in
+ * the flash.
+ */
+ uint16_t hwrm_fw_major;
+ /*
+ * This field represents the minor version of HWRM firmware, stored in
+ * the flash.
+ */
+ uint16_t hwrm_fw_minor;
+ /*
+ * This field represents the build version of HWRM firmware, stored in
+ * the flash.
+ */
+ uint16_t hwrm_fw_build;
+ /*
+ * This field can be used to represent firmware branches or customer
+ * specific releases tied to a specific (major, minor, build) version
+ * of the HWRM firmware.
+ */
+ uint16_t hwrm_fw_patch;
+ /*
+ * This field represents the major version of mgmt firmware, stored in
+ * the flash.
+ */
+ uint16_t mgmt_fw_major;
+ /*
+ * This field represents the minor version of mgmt firmware, stored in
+ * the flash.
+ */
+ uint16_t mgmt_fw_minor;
+ /*
+ * This field represents the build version of mgmt firmware, stored in
+ * the flash.
+ */
+ uint16_t mgmt_fw_build;
+ /*
+ * This field can be used to represent firmware branches or customer
+ * specific releases tied to a specific (major, minor, build) version
+ * of the mgmt firmware.
+ */
+ uint16_t mgmt_fw_patch;
+ /*
+ * This field represents the major version of roce firmware, stored in
+ * the flash.
+ */
+ uint16_t roce_fw_major;
+ /*
+ * This field represents the minor version of roce firmware, stored in
+ * the flash.
+ */
+ uint16_t roce_fw_minor;
+ /*
+ * This field represents the build version of roce firmware, stored in
+ * the flash.
+ */
+ uint16_t roce_fw_build;
+ /*
+ * This field can be used to represent firmware branches or customer
+ * specific releases tied to a specific (major, minor, build) version
+ * of the roce firmware.
+ */
+ uint16_t roce_fw_patch;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* The (0-based) instance of this Directory Type.
*/
uint16_t dir_ordinal;
- /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
+ /*
+ * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
+ * extension flag definitions).
+ */
uint16_t dir_ext;
- /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
+ /*
+ * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute
+ * flag definitions).
+ */
uint16_t dir_attr;
/*
* If valid, then this field updates the checksum
/*
* The Directory Entry Extension flags.
* The "UPDATE" extension flag must be set in this value.
- * A corresponding directory entry with the same type and ordinal values but *without*
- * the "UPDATE" extension flag must also exist. The other flags of the extension must
+ * A corresponding directory entry with the same type and ordinal
+ * values but *without*
+ * the "UPDATE" extension flag must also exist. The other flags of
+ * the extension must
* be identical between the active and update entries.
*/
uint16_t dir_ext;
#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
uint16_t flags;
- /* If set to 1, then securely erase all unused locations in persistent storage. */
+ /*
+ * If set to 1, then securely erase all unused locations in
+ * persistent storage.
+ */
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
UINT32_C(0x1)
/*
- * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
- * When combined with erase_unused_space then unspecified images will be securely erased.
+ * If set to 1, then unspecified images, images not in the package
+ * file, will be safely deleted.
+ * When combined with erase_unused_space then unspecified images will
+ * be securely erased.
*/
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
UINT32_C(0x2)
/*
- * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
- * Allow additional time for this command to complete if this bit is set to 1.
+ * If set to 1, FW will defragment the NVM if defragmentation is
+ * required for the update.
+ * Allow additional time for this command to complete if this bit is
+ * set to 1.
*/
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
UINT32_C(0x4)
* A value of 0 indicates that no items were successfully installed.
*/
uint64_t installed_items;
- /* result is 8 b */
+ /* result is 8 b corresponding to BCMRETVAL error codes */
uint8_t result;
/* There was no problem with the package installation. */
- #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \
+ UINT32_C(0x0)
+ /* Generic failure */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \
+ UINT32_C(0xff)
+ /* Allocation error malloc failure */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \
+ UINT32_C(0xfd)
+ /* NVM install error due to invalid index */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \
+ UINT32_C(0xfb)
+ /* NVM install error due to invalid type */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \
+ UINT32_C(0xf3)
+ /* Invalid package due to invalid prerequisite */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \
+ UINT32_C(0xf2)
+ /* Invalid package due to invalid file header */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \
+ UINT32_C(0xec)
+ /* Invalid package due to invalid format */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \
+ UINT32_C(0xeb)
+ /* Invalid package due to invalid property stream */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \
+ UINT32_C(0xea)
+ /* Invalid package due to invalid property length */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \
+ UINT32_C(0xe9)
+ /* Invalid package due to invalid manifest */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \
+ UINT32_C(0xe8)
+ /* Invalid package due to invalid trailer */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \
+ UINT32_C(0xe7)
+ /* Invalid package due to invalid checksum */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \
+ UINT32_C(0xe6)
+ /* Invalid package due to invalid item checksum */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \
+ UINT32_C(0xe5)
+ /* Invalid package due to invalid length */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \
+ UINT32_C(0xe4)
+ /* Invalid package due to invalid directive */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \
+ UINT32_C(0xe1)
+ /* Invalid device due to unsupported chip revision */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \
+ UINT32_C(0xce)
+ /* Invalid device due to unsupported device ID */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \
+ UINT32_C(0xcd)
+ /* Invalid device due to unsupported subsystem vendor */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \
+ UINT32_C(0xcc)
+ /* Invalid device due to unsupported subsystem ID */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \
+ UINT32_C(0xcb)
+ /* Invalid device due to unsupported product ID or customer ID */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \
+ UINT32_C(0xc5)
+ /* Invalid package due to duplicate item */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \
+ UINT32_C(0xc4)
+ /* Invalid package due to zero length item */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \
+ UINT32_C(0xc3)
+ /* NVM integrity error checksum */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \
+ UINT32_C(0xb9)
+ /* NVM integrity error */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \
+ UINT32_C(0xb8)
+ /* Authentication error */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \
+ UINT32_C(0xb7)
+ /* NVM install error item not found */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \
+ UINT32_C(0xb0)
+ /* NVM install error item locked */
+ #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \
+ UINT32_C(0xa7)
#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
- HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
+ HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED
/* problem_item is 8 b */
uint8_t problem_item;
/* There was no problem with any packaged items. */
*/
uint8_t code;
/* Unknown error */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
/* Unable to complete operation due to fragmentation */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \
+ UINT32_C(0x1)
/* nvm is completely full. */
- #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \
+ UINT32_C(0x2)
+ /* Firmware update failed due to Anti-rollback. */
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
+ UINT32_C(0x3)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
- HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
+ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
uint8_t unused_0[7];
} __rte_packed;
/* size of data of the actual variable retrieved in bits */
uint16_t data_len;
/*
- * option_num is the option number for the data retrieved. It is possible in the
- * future that the option number returned would be different than requested. This
- * condition could occur if an option is deprecated and a new option id is defined
- * with similar characteristics, but has a slightly different definition. This
- * also makes it convenient for the caller to identify the variable result with
- * the option id from the response.
+ * option_num is the option number for the data retrieved. It is
+ * possible in the future that the option number returned would be
+ * different than requested. This condition could occur if an option is
+ * deprecated and a new option id is defined with similar
+ * characteristics, but has a slightly different definition. This
+ * also makes it convenient for the caller to identify the variable
+ * result with the option id from the response.
*/
uint16_t option_num;
/* reserved. */
/* index for the 4th dimensions */
uint16_t index_3;
uint8_t flags;
- /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
+ /*
+ * When this bit is 1, flush internal cache after this write
+ * operation (see hwrm_nvm_flush command.)
+ */
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
UINT32_C(0x1)
/* encryption method */
/* The length of the response data in number of bytes. */
uint16_t resp_len;
uint8_t result;
- /* indicates that the value provided for the option is not matching with the saved data. */
+ /*
+ * indicates that the value provided for the option is not matching
+ * with the saved data.
+ */
#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
- /* indicates that the value provided for the option is matching the saved data. */
+ /*
+ * indicates that the value provided for the option is matching the
+ * saved data.
+ */
#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
uint8_t unused_0[7];
} __rte_packed;
+/*******************
+ * hwrm_nvm_defrag *
+ *******************/
+
+
+/* hwrm_nvm_defrag_input (size:192b/24B) */
+struct hwrm_nvm_defrag_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* This bit must be '1' to perform NVM defragmentation. */
+ #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_nvm_defrag_output (size:128b/16B) */
+struct hwrm_nvm_defrag_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */
+struct hwrm_nvm_defrag_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* NVM defragmentation could not be performed */
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \
+ HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL
+ uint8_t unused_0[7];
+} __rte_packed;
+
/****************
* hwrm_oem_cmd *
****************/
*/
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
UINT32_C(0x4)
- /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
+ /*
+ * AP processor complex (in multi-host environment).
+ * Use host_idx to control which core is reset
+ */
#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
UINT32_C(0x5)
/* Reset all blocks of the chip (including all processors) */
#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
/**************************
- * hwrm_cfa_counter_qcaps *
+ * hwrm_port_phy_i2c_read *
**************************/
-/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
-struct hwrm_cfa_counter_qcaps_input {
+/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
+struct hwrm_port_phy_i2c_read_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
-} __rte_packed;
-
-/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
-struct hwrm_cfa_counter_qcaps_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
uint32_t flags;
- /* Enumeration denoting the supported CFA counter format. */
- #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
- UINT32_C(0x1)
- /* CFA counter types are not supported. */
- #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
- UINT32_C(0x0)
- /* 64-bit packet counters followed by 64-bit byte counters format. */
- #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
- UINT32_C(0x1)
- #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
- HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
- uint32_t unused_0;
- /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
- uint32_t min_rx_fc;
- /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
- uint32_t max_rx_fc;
- /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
- uint32_t min_tx_fc;
- /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
- uint32_t max_tx_fc;
- /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
- uint32_t min_rx_efc;
- /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
- uint32_t max_rx_efc;
- /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
- uint32_t min_tx_efc;
- /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
- uint32_t max_tx_efc;
- /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
- uint32_t min_rx_mdc;
- /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
- uint32_t max_rx_mdc;
- /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
- uint32_t min_tx_mdc;
- /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
- uint32_t max_tx_mdc;
- /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
- uint32_t max_flow_alloc_fc;
- uint8_t unused_1[3];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/************************
- * hwrm_cfa_counter_cfg *
- ************************/
-
-
-/* hwrm_cfa_counter_cfg_input (size:256b/32B) */
-struct hwrm_cfa_counter_cfg_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* Enumeration denoting the configuration mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
- UINT32_C(0x1)
- /* Disable the configuration mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
- UINT32_C(0x0)
- /* Enable the configuration mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
- UINT32_C(0x1)
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
- HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
- /* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
- UINT32_C(0x2)
- /* Tx path. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
- (UINT32_C(0x0) << 1)
- /* Rx path. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
- (UINT32_C(0x1) << 1)
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
- /* Enumeration denoting the data transfer mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
- UINT32_C(0xc)
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
- /* Push mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
- (UINT32_C(0x0) << 2)
- /* Pull mode. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
- (UINT32_C(0x1) << 2)
- /* Pull on async update. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
- (UINT32_C(0x2) << 2)
- #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
- HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
- uint16_t counter_type;
- /* Flow counters. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
- /* Extended flow counters. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
- /* Meter drop counters. */
- #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
- #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
- HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
- /* Ctx memory handle to be used for the counter. */
- uint16_t ctx_id;
- /* Counter update cadence hint (only in Push mode). */
- uint16_t update_tmr_ms;
- /* Total number of entries. */
- uint32_t num_entries;
- uint32_t unused_0;
-} __rte_packed;
-
-/* hwrm_cfa_counter_cfg_output (size:128b/16B) */
-struct hwrm_cfa_counter_cfg_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- uint8_t unused_0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/***************************
- * hwrm_cfa_counter_qstats *
- ***************************/
-
-
-/* hwrm_cfa_counter_qstats_input (size:320b/40B) */
-struct hwrm_cfa_counter_qstats_input {
- /* The HWRM command request type. */
- uint16_t req_type;
- /*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
- */
- uint16_t cmpl_ring;
- /*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
- */
- uint16_t seq_id;
+ uint32_t enables;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
+ * This bit must be '1' for the page_offset field to be
+ * configured.
*/
- uint16_t target_id;
+ #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* 8-bit I2C slave address. */
+ uint8_t i2c_slave_addr;
+ uint8_t unused_0;
+ /* The page number that is being accessed over I2C. */
+ uint16_t page_number;
+ /* Offset within the page that is being accessed over I2C. */
+ uint16_t page_offset;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * Length of data to read, in bytes starting at the offset
+ * specified above. If the offset is not specified, then
+ * the data shall be read from the beginning of the page.
*/
- uint64_t resp_addr;
- uint16_t flags;
- /* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
- /* Tx path. */
- #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
- /* Rx path. */
- #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
- #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
- uint16_t counter_type;
- uint16_t input_flow_ctx_id;
- uint16_t num_entries;
- uint16_t delta_time_ms;
- uint16_t meter_instance_id;
- uint16_t mdc_ctx_id;
- uint8_t unused_0[2];
- uint64_t expected_count;
+ uint8_t data_length;
+ uint8_t unused_1[7];
} __rte_packed;
-/* hwrm_cfa_counter_qstats_output (size:128b/16B) */
-struct hwrm_cfa_counter_qstats_output {
+/* hwrm_port_phy_i2c_read_output (size:640b/80B) */
+struct hwrm_port_phy_i2c_read_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* Up to 64B of data. */
+ uint32_t data[16];
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
*/
uint8_t valid;
} __rte_packed;
-
#endif /* _HSI_STRUCT_DEF_DPDK_H_ */
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