#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
-/* Engine CKV - The device's serial number. */
-#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
-/* Engine CKV - Per-function random nonce data. */
-#define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
+/* Engine CKV - The Alias key EC curve and ECC public key information. */
+#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
/* Engine CKV - Initialization vector. */
#define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
/* Engine CKV - Authentication tag. */
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
/* Engine CKV - The encrypted data. */
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
-/* Engine CKV - Supported algorithms. */
-#define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
-/* Engine CKV - The EC curve name and ECC public key information. */
-#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
+/* Engine CKV - Supported host_algorithms. */
+#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
+/* Engine CKV - The Host EC curve name and ECC public key information. */
+#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
/* Engine CKV - The ECDSA signature. */
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
+/* Engine CKV - The firmware EC curve name and ECC public key information. */
+#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
+/* Engine CKV - Supported firmware algorithms. */
+#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
#define TLV_TYPE_LAST \
- TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
+ TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
/* tlv (size:64b/8B) */
#define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
#define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
#define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
- /* Experimental */
#define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
- /* Experimental */
#define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
- /* Experimental */
#define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
#define HWRM_VNIC_ALLOC UINT32_C(0x40)
#define HWRM_VNIC_FREE UINT32_C(0x41)
#define HWRM_RESERVED6 UINT32_C(0x65)
#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
#define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
+ #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
+ #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
#define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
#define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
#define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
#define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
#define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
+ #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
+ #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
#define HWRM_FW_SYNC UINT32_C(0xc3)
+ #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
+ #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
+ #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
+ #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
/* Experimental */
#define HWRM_FW_SET_TIME UINT32_C(0xc8)
/* Experimental */
#define HWRM_OEM_CMD UINT32_C(0xd4)
/* Tells the fw to run PRBS test on a given port and lane. */
#define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
+ #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
+ #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
+ /* Tells the fw to collect dsc dump on a given port and lane. */
+ #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
+ #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
+ #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Experimental */
#define HWRM_CFA_TFLIB UINT32_C(0x125)
- /* Engine CKV - Ping the device and SRT firmware to get the public key. */
- #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
#define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
/* Engine CKV - Add a new CKEK used to encrypt keys. */
#define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
/* Engine - Query the statistics accumulator for an Engine. */
#define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
+ /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
+ #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
/* Engine - Allocate an Engine RQ. */
#define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
/* Engine - Free an Engine RQ. */
#define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
/* Queries the BW of any VF */
#define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
+ /* Queries pf ids belong to specified host(s) */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
#define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* This error code is only reported by the firmware when during
- * flow allocation when a requeest for a flow counter fails because
+ * flow allocation when a request for a flow counter fails because
* the number of flow counters are exhausted.
*/
#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
* internal error.
*/
#define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * Firmware is unable to service the request at the present time. Caller
+ * may try again later.
+ */
+ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
- * hwrm_resp_hdr TLV. This value is not an indicatation of any error
- * by itself, just an indicatation that the response should be parsed
+ * hwrm_resp_hdr TLV. This value is not an indication of any error
+ * by itself, just an indication that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
-#define HWRM_VERSION_UPDATE 0
+#define HWRM_VERSION_UPDATE 1
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 74
-#define HWRM_VERSION_STR "1.10.0.74"
+#define HWRM_VERSION_RSVD 6
+#define HWRM_VERSION_STR "1.10.1.6"
/****************
* hwrm_ver_get *
*/
uint8_t flags;
/*
- * If set to 1, device is not ready.
+ * If set to 1, it will indicate to host drivers that firmware is
+ * not ready to start full blown HWRM commands. Host drivers should
+ * re-try HWRM_VER_GET with some timeout period. The timeout period
+ * can be selected up to 5 seconds.
+ * For Example, PCIe hot-plug:
+ * Hot plug timing is system dependent. It generally takes up to
+ * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
* If set to 0, device is ready to accept all HWRM commands.
*/
#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
#define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
/*
* Indicates that this BD is 1BB long and is an empty
- * TX BD. Not valid for use by the driver.
+ * TX BD. Not valid for use by the driver.
*/
#define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
/*
* Indicates that this BD is 16B long and is an RX Producer
- * (ie. empty) buffer descriptor.
+ * (i.e. empty) buffer descriptor.
*/
#define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
/*
#define TX_BD_SHORT_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
- * pointed to by this descriptor. This flag must be
+ * pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
* This value indicates how many 16B BD locations are consumed
* in the ring by this packet.
* A value of 1 indicates that this BD is the only BD (and that
- * the it is a short BD). A value
+ * it is a short BD). A value
* of 3 indicates either 3 short BDs or 1 long BD and one short
- * BD in the packet. A value of 0 indicates
+ * BD in the packet. A value of 0 indicates
* that there are 32 BD locations in the packet (the maximum).
*
* This field is valid only on the first BD of a packet.
#define TX_BD_LONG_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
- * pointed to by this descriptor. This flag must be
+ * pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
* This value indicates how many 16B BD locations are consumed
* in the ring by this packet.
* A value of 1 indicates that this BD is the only BD (and that
- * the it is a short BD). A value
+ * it is a short BD). A value
* of 3 indicates either 3 short BDs or 1 long BD and one short
- * BD in the packet. A value of 0 indicates
+ * BD in the packet. A value of 0 indicates
* that there are 32 BD locations in the packet (the maximum).
*
* This field is valid only on the first BD of a packet.
*/
#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
/*
- * If set to 1, the controller replaces the IP checksum of the
+ * If set to 1, the controller replaces the IP checksum of the
* normal packets, or the inner IP checksum of the encapsulated
* packets with the hardware calculated IP checksum for the
* packet associated with this descriptor.
*
* This bit must be valid on the first BD of a packet.
*
- * Packet must be 64B or longer when this flag is set. It is not
+ * Packet must be 64B or longer when this flag is set. It is not
* useful to use this bit with any form of TX offload such as
- * CSO or LSO. The intent is that the packet from the host already
+ * CSO or LSO. The intent is that the packet from the host already
* has a valid Ethernet CRC on the packet.
*/
#define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
*/
#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
/*
- * If set to 1, the device will treat this packet with LSO(Large
+ * If set to 1, the device will treat this packet with LSO(Large
* Send Offload) processing for both normal or encapsulated
- * packets, which is a form of TCP segmentation. When this bit
+ * packets, which is a form of TCP segmentation. When this bit
* is 1, the hdr_size and mss fields must be valid. The driver
* doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
* flags since the controller will replace the appropriate
#define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
/*
* If set to '1', then the RoCE ICRC will be appended to the
- * packet. Packet must be a valid RoCE format packet.
+ * packet. Packet must be a valid RoCE format packet.
*/
#define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
/*
* If set to '1', then the FCoE CRC will be appended to the
- * packet. Packet must be a valid FCoE format packet.
+ * packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
uint16_t hdr_size;
/*
* When LSO is '1', this field must contain the offset of the
* TCP payload from the beginning of the packet in as
- * 16b words. In case of encapsulated/tunneling packet, this field
+ * 16b words. In case of encapsulated/tunneling packet, this field
* contains the offset of the inner TCP payload from beginning of the
* packet as 16-bit words.
*
#define TX_BD_LONG_INLINE_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
- * pointed to by this descriptor. This flag must be
+ * pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
#define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
/*
* If set to '1', then the RoCE ICRC will be appended to the
- * packet. Packet must be a valid RoCE format packet.
+ * packet. Packet must be a valid RoCE format packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
/*
* If set to '1', then the FCoE CRC will be appended to the
- * packet. Packet must be a valid FCoE format packet.
+ * packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
uint16_t unused2;
#define TX_BD_EMPTY_TYPE_SFT 0
/*
* Indicates that this BD is 1BB long and is an empty
- * TX BD. Not valid for use by the driver.
+ * TX BD. Not valid for use by the driver.
*/
#define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
#define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
#define RX_PROD_PKT_BD_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is an RX Producer
- * (ie. empty) buffer descriptor.
+ * (i.e. empty) buffer descriptor.
*/
#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
#define RX_PROD_PKT_BD_TYPE_LAST \
#define RX_PROD_PKT_BD_FLAGS_SFT 6
/*
* If set to 1, the packet will be placed at the address plus
- * 2B. The 2 Bytes of padding will be written as zero.
+ * 2B. The 2 Bytes of padding will be written as zero.
*/
#define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
/*
#define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
/*
* This value is the number of additional buffers in the ring that
- * describe the buffer space to be consumed for the this packet.
+ * describe the buffer space to be consumed for this packet.
* If the value is zero, then the packet must fit within the
- * space described by this BD. If this value is 1 or more, it
+ * space described by this BD. If this value is 1 or more, it
* indicates how many additional "buffer" BDs are in the ring
* immediately following this BD to be used for the same
* network packet.
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
- * by placed in host memory.
+ * be placed in host memory.
*/
uint64_t address;
} __attribute__((packed));
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
- * by placed in host memory.
+ * be placed in host memory.
*/
uint64_t address;
} __attribute__((packed));
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
- * by placed in host memory.
+ * be placed in host memory.
*/
uint64_t address;
} __attribute__((packed));
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
/*
* RX Aggregation Buffer completion :
* Completion of an L2 aggregation buffer in support of
- * TPA, HDS, or Jumbo packet completion. Length = 16B
+ * TPA, HDS, or Jumbo packet completion. Length = 16B
*/
#define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
/*
uint32_t info2;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
uint32_t info3_v;
#define CMPL_BASE_V UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
#define TX_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
+ * error of some type. Type of error is indicated in
* error_flags.
*/
#define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet completed
* was transmitted using the push acceleration data provided
- * by the driver. When this bit is '0', it indicates that the
+ * by the driver. When this bit is '0', it indicates that the
* packet had not push acceleration data written or was executed
* as a normal packet even though push data was provided.
*/
uint16_t errors_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define TX_CMPL_V UINT32_C(0x1)
#define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
/*
* When this bit is '1', it indicates that the length of
- * the packet was zero. No packet was transmitted.
+ * the packet was zero. No packet was transmitted.
*/
#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
/*
#define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet was longer
- * than indicated by the hint. No packet was transmitted.
+ * than indicated by the hint. No packet was transmitted.
*/
#define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
/*
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
+ * error of some type. Type of error is indicated in
* error_flags.
*/
#define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
/*
* This is the length of the data for the packet stored in the
- * buffer(s) identified by the opaque value. This includes
- * the packet BD and any associated buffer BDs. This does not include
- * the the length of any data places in aggregation BDs.
+ * buffer(s) identified by the opaque value. This includes
+ * the packet BD and any associated buffer BDs. This does not include
+ * the length of any data places in aggregation BDs.
*/
uint16_t len;
/*
uint8_t agg_bufs_v1;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define RX_PKT_CMPL_V1 UINT32_C(0x1)
/*
#define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
#define RX_PKT_CMPL_UNUSED1_SFT 6
/*
- * This is the RSS hash type for the packet. The value is packed
+ * This is the RSS hash type for the packet. The value is packed
* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
*
* The value of tuple_extrac_op provides the information about
uint8_t rss_hash_type;
/*
* This value indicates the offset in bytes from the beginning of the packet
- * where the inner payload starts. This value is valid for TCP, UDP,
+ * where the inner payload starts. This value is valid for TCP, UDP,
* FCoE, and RoCE packets.
*
* A value of zero indicates that header is 256B into the packet.
/* This value indicates what format the metadata field is. */
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
- /* No metadata informtaion. Value is zero. */
+ /* No metadata information. Value is zero. */
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
/*
* - VXLAN = VNI[23:0] -> VXLAN Network ID
* - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
* - NVGRE = TNI[23:0] -> Tenant Network ID
- * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
* - IPV4 = 0 (not populated)
* - IPV6 = Flow Label[19:0]
* - PPPoE = sessionID[15:0]
RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
- * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
+ * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define RX_PKT_CMPL_V2 \
UINT32_C(0x1)
/*
* This error indicates that there was some sort of problem with
* the BDs for the packet that was found after part of the
- * packet was already placed. The packet should be treated as
+ * packet was already placed. The packet should be treated as
* invalid.
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
* Did Not Fit:
* Packet did not fit into packet buffer provided.
* For regular placement, this means the packet did not fit
- * in the buffer provided. For HDS and jumbo placement, this
+ * in the buffer provided. For HDS and jumbo placement, this
* means that the packet could not be placed into 7 physical
* buffers or less.
*/
UINT32_C(0x80)
/*
* This indicates that there was a CRC error on either an FCoE
- * or RoCE packet. The itype indicates the packet type.
+ * or RoCE packet. The itype indicates the packet type.
*/
#define RX_PKT_CMPL_ERRORS_CRC_ERROR \
UINT32_C(0x100)
* This value holds the reordering sequence number for the packet.
* If the reordering sequence is not valid, then this value is zero.
* The reordering domain for the packet is in the bottom 8 to 10b of
- * the rss_hash value. The bottom 20b of this value contain the
+ * the rss_hash value. The bottom 20b of this value contain the
* ordering domain value for the packet.
*/
#define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
#define RX_PKT_CMPL_REORDER_SFT 0
} __attribute__((packed));
+/*
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
+ */
/* rx_tpa_start_cmpl (size:128b/16B) */
struct rx_tpa_start_cmpl {
uint16_t flags_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
/*
* Jumbo:
- * TPA Packet was placed using jumbo algorithm. This means
+ * TPA Packet was placed using jumbo algorithm. This means
* that the first buffer will be filled with data before
- * moving to aggregation buffers. Each aggregation buffer
+ * moving to aggregation buffers. Each aggregation buffer
* will be filled before moving to the next aggregation
* buffer.
*/
uint32_t opaque;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
uint8_t v1;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
#define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
/*
- * This is the RSS hash type for the packet. The value is packed
+ * This is the RSS hash type for the packet. The value is packed
* {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
*
* The value of tuple_extrac_op provides the information about
uint8_t rss_hash_type;
/*
* This is the aggregation ID that the completion is associated
- * with. Use this number to correlate the TPA start completion
+ * with. Use this number to correlate the TPA start completion
* with the TPA end completion.
*/
uint16_t agg_id;
#define RX_TPA_START_CMPL_UNUSED2_SFT 0
/*
* This is the aggregation ID that the completion is associated
- * with. Use this number to correlate the TPA start completion
+ * with. Use this number to correlate the TPA start completion
* with the TPA end completion.
*/
#define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
uint32_t rss_hash;
} __attribute__((packed));
-/* Last 16 bytes of rx_tpq_start_cmpl. */
+/*
+ * Last 16 bytes of rx_tpa_start_cmpl.
+ *
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
+ */
/* rx_tpa_start_cmpl_hi (size:128b/16B) */
struct rx_tpa_start_cmpl_hi {
uint32_t flags2;
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ /*
+ * This indicates that the TCP, UDP or ICMP checksum was
+ * calculated for the inner packet and that the sum passed
+ * for all segments included in the aggregation.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ /*
+ * This indicates that the ip checksum was calculated for the
+ * tunnel header and that the sum passed for all segments
+ * included in the aggregation.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ /*
+ * This indicates that the UDP checksum was
+ * calculated for the tunnel packet and that the sum passed for
+ * all segments included in the aggregation.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ /* This value indicates what format the metadata field is. */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ /* No metadata information. Value is zero. */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
+ /*
+ * The metadata field contains the VLAN tag and TPID value.
+ * - metadata[11:0] contains the vlan VID value.
+ * - metadata[12] contains the vlan DE value.
+ * - metadata[15:13] contains the vlan PRI value.
+ * - metadata[31:16] contains the vlan TPID value.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ /*
+ * This field indicates the IP type for the inner-most IP header.
+ * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This is data from the CFA block as indicated by the meta_format
+ * field.
+ */
+ uint32_t metadata;
+ /* When meta_format=1, this value is the VLAN VID. */
+ #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
+ #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
+ /* When meta_format=1, this value is the VLAN DE. */
+ #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
+ /* When meta_format=1, this value is the VLAN PRI. */
+ #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
+ #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
+ /* When meta_format=1, this value is the VLAN TPID. */
+ #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
+ uint16_t v2;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ /*
+ * This field identifies the CFA action rule that was used for this
+ * packet.
+ */
+ uint16_t cfa_code;
+ /*
+ * This is the size in bytes of the inner most L4 header.
+ * This can be subtracted from the payload_offset to determine
+ * the start of the inner most L4 header.
+ */
+ uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
+ /*
+ * This is the offset from the beginning of the packet in bytes for
+ * the outer L3 header. If there is no outer L3 header, then this
+ * value is zero.
+ */
+ #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
+ #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
+ /*
+ * This is the offset from the beginning of the packet in bytes for
+ * the inner most L2 header.
+ */
+ #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
+ #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
+ /*
+ * This is the offset from the beginning of the packet in bytes for
+ * the inner most L3 header.
+ */
+ #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
+ #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
+ /*
+ * This is the size in bytes of the inner most L4 header.
+ * This can be subtracted from the payload_offset to determine
+ * the start of the inner most L4 header.
+ */
+ #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
+ #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
+} __attribute__((packed));
+
+/*
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
+ */
+/* rx_tpa_end_cmpl (size:128b/16B) */
+struct rx_tpa_end_cmpl {
+ uint16_t flags_type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define RX_TPA_END_CMPL_TYPE_SFT 0
+ /*
+ * RX L2 TPA End Completion:
+ * Completion at the end of a TPA operation.
+ * Length = 32B
+ */
+ #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
+ #define RX_TPA_END_CMPL_TYPE_LAST \
+ RX_TPA_END_CMPL_TYPE_RX_TPA_END
+ #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define RX_TPA_END_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
+ /* This field indicates how the packet was placed in the buffer. */
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
+ /*
+ * Jumbo:
+ * TPA Packet was placed using jumbo algorithm. This means
+ * that the first buffer will be filled with data before
+ * moving to aggregation buffers. Each aggregation buffer
+ * will be filled before moving to the next aggregation
+ * buffer.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
+ (UINT32_C(0x1) << 7)
+ /*
+ * Header/Data Separation:
+ * Packet was placed using Header/Data separation algorithm.
+ * The separation location is indicated by the itype field.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
+ (UINT32_C(0x2) << 7)
+ /*
+ * GRO/Jumbo:
+ * Packet will be placed using GRO/Jumbo where the first
+ * packet is filled with data. Subsequent packets will be
+ * placed such that any one packet does not span two
+ * aggregation buffers unless it starts at the beginning of
+ * an aggregation buffer.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
+ (UINT32_C(0x5) << 7)
+ /*
+ * GRO/Header-Data Separation:
+ * Packet will be placed using GRO/HDS where the header
+ * is in the first packet.
+ * Payload of each packet will be
+ * placed such that any one packet does not span two
+ * aggregation buffers unless it starts at the beginning of
+ * an aggregation buffer.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
+ (UINT32_C(0x6) << 7)
+ #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
+ RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
+ /* unused is 2 b */
+ #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
+ #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
+ /*
+ * This value indicates what the inner packet determined for the
+ * packet was.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
+ */
+ #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
+ #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
+ /*
+ * This value is zero for TPA End completions.
+ * There is no data in the buffer that corresponds to the opaque
+ * value in this completion.
+ */
+ uint16_t len;
+ /*
+ * This is a copy of the opaque field from the RX BD this completion
+ * corresponds to.
+ */
+ uint32_t opaque;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ uint8_t agg_bufs_v1;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
+ /*
+ * This value is the number of aggregation buffers that follow this
+ * entry in the completion ring that are a part of this aggregation
+ * packet.
+ * If the value is zero, then the packet is completely contained
+ * in the buffer space provided in the aggregation start completion.
+ */
+ #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
+ #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
+ /* This value is the number of segments in the TPA operation. */
+ uint8_t tpa_segs;
+ /*
+ * This value indicates the offset in bytes from the beginning of the packet
+ * where the inner payload starts. This value is valid for TCP, UDP,
+ * FCoE, and RoCE packets.
+ *
+ * A value of zero indicates an offset of 256 bytes.
+ */
+ uint8_t payload_offset;
+ uint8_t agg_id;
+ /* unused2 is 1 b */
+ #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
+ /*
+ * This is the aggregation ID that the completion is associated
+ * with. Use this number to correlate the TPA start completion
+ * with the TPA end completion.
+ */
+ #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
+ #define RX_TPA_END_CMPL_AGG_ID_SFT 1
+ /*
+ * For non-GRO packets, this value is the
+ * timestamp delta between earliest and latest timestamp values for
+ * TPA packet. If packets were not time stamped, then delta will be
+ * zero.
+ *
+ * For GRO packets, this field is zero except for the following
+ * sub-fields.
+ * - tsdelta[31]
+ * Timestamp present indication. When '0', no Timestamp
+ * option is in the packet. When '1', then a Timestamp
+ * option is present in the packet.
+ */
+ uint32_t tsdelta;
+} __attribute__((packed));
+
+/*
+ * Last 16 bytes of rx_tpa_end_cmpl.
+ *
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
+ */
+/* rx_tpa_end_cmpl_hi (size:128b/16B) */
+struct rx_tpa_end_cmpl_hi {
+ uint32_t tpa_dup_acks;
+ /*
+ * This value is the number of duplicate ACKs that have been
+ * received as part of the TPA operation.
+ */
+ #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
+ #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value is the valid when TPA completion is active. It
+ * indicates the length of the longest segment of the TPA operation
+ * for LRO mode and the length of the first segment in GRO mode.
+ *
+ * This value may be used by GRO software to re-construct the original
+ * packet stream from the TPA packet. This is the length of all
+ * but the last segment for GRO. In LRO mode this value may be used
+ * to indicate MSS size to the stack.
+ */
+ uint16_t tpa_seg_len;
+ /* unused4 is 16 b */
+ uint16_t unused3;
+ uint16_t errors_v2;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define RX_TPA_END_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /*
+ * This error occurs when there is a fatal HW problem in
+ * the chip only. It indicates that there were not
+ * BDs on chip but that there was adequate reservation.
+ * provided by the TPA block.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
+ (UINT32_C(0x2) << 1)
+ /*
+ * This error occurs when TPA block was not configured to
+ * reserve adequate BDs for TPA operations on this RX
+ * ring. All data for the TPA operation was not placed.
+ *
+ * This error can also be generated when the number of
+ * segments is not programmed correctly in TPA and the
+ * 33 total aggregation buffers allowed for the TPA
+ * operation has been exceeded.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
+ (UINT32_C(0x4) << 1)
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ /* unused5 is 16 b */
+ uint16_t unused_4;
+ /*
+ * This is the opaque value that was completed for the TPA start
+ * completion that corresponds to this TPA end completion.
+ */
+ uint32_t start_opaque;
+} __attribute__((packed));
+
+/*
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
+ */
+/* rx_tpa_v2_start_cmpl (size:128b/16B) */
+struct rx_tpa_v2_start_cmpl {
+ uint16_t flags_type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define RX_TPA_V2_START_CMPL_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
+ /*
+ * RX L2 TPA Start Completion:
+ * Completion at the beginning of a TPA operation.
+ * Length = 32B
+ */
+ #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
+ UINT32_C(0x13)
+ #define RX_TPA_V2_START_CMPL_TYPE_LAST \
+ RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
+ #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
+ UINT32_C(0xffc0)
+ #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
+ /* This bit will always be '0' for TPA start completions. */
+ #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
+ UINT32_C(0x40)
+ /* This field indicates how the packet was placed in the buffer. */
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
+ UINT32_C(0x380)
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
+ /*
+ * Jumbo:
+ * TPA Packet was placed using jumbo algorithm. This means
+ * that the first buffer will be filled with data before
+ * moving to aggregation buffers. Each aggregation buffer
+ * will be filled before moving to the next aggregation
+ * buffer.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
+ (UINT32_C(0x1) << 7)
+ /*
+ * Header/Data Separation:
+ * Packet was placed using Header/Data separation algorithm.
+ * The separation location is indicated by the itype field.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
+ (UINT32_C(0x2) << 7)
+ /*
+ * GRO/Jumbo:
+ * Packet will be placed using GRO/Jumbo where the first
+ * packet is filled with data. Subsequent packets will be
+ * placed such that any one packet does not span two
+ * aggregation buffers unless it starts at the beginning of
+ * an aggregation buffer.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
+ (UINT32_C(0x5) << 7)
+ /*
+ * GRO/Header-Data Separation:
+ * Packet will be placed using GRO/HDS where the header
+ * is in the first packet.
+ * Payload of each packet will be
+ * placed such that any one packet does not span two
+ * aggregation buffers unless it starts at the beginning of
+ * an aggregation buffer.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
+ (UINT32_C(0x6) << 7)
+ #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
+ RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
+ /* This bit is '1' if the RSS field in this completion is valid. */
+ #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
+ UINT32_C(0x400)
+ /*
+ * For devices that support timestamps, when this bit is cleared the
+ * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
+ * field contains the 32b timestamp for
+ * the packet from the MAC. When this bit is set, the
+ * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
+ * field contains the outer_l3_offset, inner_l2_offset,
+ * inner_l3_offset, and inner_l4_size.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
+ UINT32_C(0x800)
+ /*
+ * This value indicates what the inner packet determined for the
+ * packet was.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
+ UINT32_C(0xf000)
+ #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
+ /*
+ * TCP Packet:
+ * Indicates that the packet was IP and TCP.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
+ (UINT32_C(0x2) << 12)
+ #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
+ RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
+ /*
+ * This value indicates the amount of packet data written to the
+ * buffer the opaque field in this completion corresponds to.
+ */
+ uint16_t len;
+ /*
+ * This is a copy of the opaque field from the RX BD this completion
+ * corresponds to.
+ */
+ uint32_t opaque;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ uint8_t v1;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
+ #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
+ /*
+ * This is the RSS hash type for the packet. The value is packed
+ * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
+ *
+ * The value of tuple_extrac_op provides the information about
+ * what fields the hash was computed on.
+ * * 0: The RSS hash was computed over source IP address,
+ * destination IP address, source port, and destination port of inner
+ * IP and TCP or UDP headers. Note: For non-tunneled packets,
+ * the packet headers are considered inner packet headers for the RSS
+ * hash computation purpose.
+ * * 1: The RSS hash was computed over source IP address and destination
+ * IP address of inner IP header. Note: For non-tunneled packets,
+ * the packet headers are considered inner packet headers for the RSS
+ * hash computation purpose.
+ * * 2: The RSS hash was computed over source IP address,
+ * destination IP address, source port, and destination port of
+ * IP and TCP or UDP headers of outer tunnel headers.
+ * Note: For non-tunneled packets, this value is not applicable.
+ * * 3: The RSS hash was computed over source IP address and
+ * destination IP address of IP header of outer tunnel headers.
+ * Note: For non-tunneled packets, this value is not applicable.
+ *
+ * Note that 4-tuples values listed above are applicable
+ * for layer 4 protocols supported and enabled for RSS in the hardware,
+ * HWRM firmware, and drivers. For example, if RSS hash is supported and
+ * enabled for TCP traffic only, then the values of tuple_extract_op
+ * corresponding to 4-tuples are only valid for TCP traffic.
+ */
+ uint8_t rss_hash_type;
+ /*
+ * This is the aggregation ID that the completion is associated
+ * with. Use this number to correlate the TPA start completion
+ * with the TPA end completion.
+ */
+ uint16_t agg_id;
+ /*
+ * This value is the RSS hash value calculated for the packet
+ * based on the mode bits and key value in the VNIC.
+ */
+ uint32_t rss_hash;
+} __attribute__((packed));
+
+/*
+ * Last 16 bytes of rx_tpa_v2_start_cmpl.
+ *
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
+ */
+/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
+struct rx_tpa_v2_start_cmpl_hi {
+ uint32_t flags2;
+ /*
+ * This indicates that the ip checksum was calculated for the
+ * inner packet and that the sum passed for all segments
+ * included in the aggregation.
+ */
+ #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
- /* No metadata informtaion. Value is zero. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ /* No metadata informtaion. Value is zero. */
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
/*
* If ext_meta_format is equal to 1, the metadata field
* - MPLs = Outer label[19:0]
* - UPAR = Selected[31:0] with bit mask
*/
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
(UINT32_C(0x2) << 4)
/*
* if ext_meta_format is equal to 1, metadata field contains
* 16b metadata from the prepended header (chdr_data).
*/
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
(UINT32_C(0x3) << 4)
/*
* If ext_meta_format is equal to 1, the metadata field contains
* - metadata[26:18] contains the inner_l3_offset.
* - metadata[31:27] contains the inner_l4_size.
*/
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
(UINT32_C(0x4) << 4)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
+ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
+ RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
- * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
+ * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
UINT32_C(0x100)
/*
* This indicates that the complete 1's complement checksum was
* calculated for the packet.
*/
- #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
UINT32_C(0x200)
/*
* The combination of this value and meta_format indicated what
* format the metadata field is.
*/
- #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
UINT32_C(0xc00)
- #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
/*
* This value is the complete 1's complement checksum calculated from
* the start of the outer L3 header to the end of the packet (not
* the complete checksum is calculated for the first packet in the
* aggregation only.
*/
- #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
UINT32_C(0xffff0000)
- #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
+ #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
*/
uint32_t metadata;
- /* When meta_format=1, this value is the VLAN VID. */
- #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
- #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
- /* When meta_format=1, this value is the VLAN DE. */
- #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
- /* When meta_format=1, this value is the VLAN PRI. */
- #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
- #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
- /* When meta_format=1, this value is the VLAN TPID. */
- #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
- #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
+ /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
+ #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
+ #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
+ /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
+ #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
+ /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
+ #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
+ #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
+ /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
+ #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
+ #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
- #define RX_TPA_START_CMPL_ERRORS_MASK \
+ #define RX_TPA_V2_START_CMPL_V2 \
+ UINT32_C(0x1)
+ #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
UINT32_C(0xfffe)
- #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
/*
* This error indicates that there was some sort of problem with
* the BDs for the packet that was found after part of the
- * packet was already placed. The packet should be treated as
+ * packet was already placed. The packet should be treated as
* invalid.
*/
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
+ UINT32_C(0xe)
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
/* No buffer error */
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
(UINT32_C(0x0) << 1)
/*
* Bad Format:
* BDs were not formatted correctly.
*/
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
/*
* Flush:
* There was a bad_format error on the previous operation
*/
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
(UINT32_C(0x5) << 1)
- #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
*/
uint16_t cfa_code;
/*
- * This is the size in bytes of the inner most L4 header.
- * This can be subtracted from the payload_offset to determine
- * the start of the inner most L4 header.
+ * For devices that support timestamps this field is overridden
+ * with the timestamp value. When `flags.timestamp_fld_format` is
+ * cleared, this field contains the 32b timestamp for the packet from the
+ * MAC.
+ *
+ * When `flags.timestamp_fld_format` is set, this field contains the
+ * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
+ * as defined below.
*/
uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
/*
* This is the offset from the beginning of the packet in bytes for
- * the outer L3 header. If there is no outer L3 header, then this
+ * the outer L3 header. If there is no outer L3 header, then this
* value is zero.
*/
- #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
- #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
+ #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
+ #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
/*
* This is the offset from the beginning of the packet in bytes for
* the inner most L2 header.
*/
- #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
- #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
+ #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
+ #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
/*
* This is the offset from the beginning of the packet in bytes for
* the inner most L3 header.
*/
- #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
- #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
+ #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
+ #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
/*
* This is the size in bytes of the inner most L4 header.
* This can be subtracted from the payload_offset to determine
* the start of the inner most L4 header.
*/
- #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
- #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
+ #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
+ #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
} __attribute__((packed));
-/* rx_tpa_end_cmpl (size:128b/16B) */
-struct rx_tpa_end_cmpl {
+/*
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
+ */
+/* rx_tpa_v2_end_cmpl (size:128b/16B) */
+struct rx_tpa_v2_end_cmpl {
uint16_t flags_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
- #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define RX_TPA_END_CMPL_TYPE_SFT 0
+ #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
/*
* RX L2 TPA End Completion:
* Completion at the end of a TPA operation.
* Length = 32B
*/
- #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
- #define RX_TPA_END_CMPL_TYPE_LAST \
- RX_TPA_END_CMPL_TYPE_RX_TPA_END
- #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
- #define RX_TPA_END_CMPL_FLAGS_SFT 6
+ #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
+ #define RX_TPA_V2_END_CMPL_TYPE_LAST \
+ RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
+ #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
+ * error of some type. Type of error is indicated in
* error_flags.
*/
- #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
+ #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
/* This field indicates how the packet was placed in the buffer. */
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
/*
* Jumbo:
- * TPA Packet was placed using jumbo algorithm. This means
+ * TPA Packet was placed using jumbo algorithm. This means
* that the first buffer will be filled with data before
- * moving to aggregation buffers. Each aggregation buffer
+ * moving to aggregation buffers. Each aggregation buffer
* will be filled before moving to the next aggregation
* buffer.
*/
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
(UINT32_C(0x1) << 7)
/*
* Header/Data Separation:
* Packet was placed using Header/Data separation algorithm.
* The separation location is indicated by the itype field.
*/
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
(UINT32_C(0x2) << 7)
/*
* GRO/Jumbo:
* aggregation buffers unless it starts at the beginning of
* an aggregation buffer.
*/
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
(UINT32_C(0x5) << 7)
/*
* GRO/Header-Data Separation:
* aggregation buffers unless it starts at the beginning of
* an aggregation buffer.
*/
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
(UINT32_C(0x6) << 7)
- #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
- RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
+ #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
+ RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
/* unused is 2 b */
- #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
- #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
+ #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
+ #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
/*
* This value indicates what the inner packet determined for the
* packet was.
* - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
+ * Indicates that the packet was IP and TCP. This indicates
* that the ip_cs field is valid and that the tcp_udp_cs
* field is valid and contains the TCP checksum.
* This also indicates that the payload_offset field is valid.
*/
- #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
- #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
+ #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
+ #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
/*
* This value is zero for TPA End completions.
* There is no data in the buffer that corresponds to the opaque
* corresponds to.
*/
uint32_t opaque;
+ uint8_t v1;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
- */
- uint8_t agg_bufs_v1;
- /*
- * This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
- /*
- * This value is the number of aggregation buffers that follow this
- * entry in the completion ring that are a part of this aggregation
- * packet.
- * If the value is zero, then the packet is completely contained
- * in the buffer space provided in the aggregation start completion.
- */
- #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
- #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
+ #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
/* This value is the number of segments in the TPA operation. */
uint8_t tpa_segs;
- /*
- * This value indicates the offset in bytes from the beginning of the packet
- * where the inner payload starts. This value is valid for TCP, UDP,
- * FCoE, and RoCE packets.
- *
- * A value of zero indicates an offset of 256 bytes.
- */
- uint8_t payload_offset;
- uint8_t agg_id;
- /* unused2 is 1 b */
- #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
/*
* This is the aggregation ID that the completion is associated
- * with. Use this number to correlate the TPA start completion
+ * with. Use this number to correlate the TPA start completion
* with the TPA end completion.
*/
- #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
- #define RX_TPA_END_CMPL_AGG_ID_SFT 1
+ uint16_t agg_id;
/*
* For non-GRO packets, this value is the
* timestamp delta between earliest and latest timestamp values for
* For GRO packets, this field is zero except for the following
* sub-fields.
* - tsdelta[31]
- * Timestamp present indication. When '0', no Timestamp
- * option is in the packet. When '1', then a Timestamp
+ * Timestamp present indication. When '0', no Timestamp
+ * option is in the packet. When '1', then a Timestamp
* option is present in the packet.
*/
uint32_t tsdelta;
} __attribute__((packed));
-/* Last 16 bytes of rx_tpa_end_cmpl. */
-/* rx_tpa_end_cmpl_hi (size:128b/16B) */
-struct rx_tpa_end_cmpl_hi {
+/*
+ * Last 16 bytes of rx_tpa_v2_end_cmpl.
+ *
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
+ */
+/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
+struct rx_tpa_v2_end_cmpl_hi {
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
- #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
+ #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
/*
* This value indicated the offset in bytes from the beginning of
* the packet where the inner payload starts. This value is valid
*/
uint8_t tpa_agg_bufs;
/*
- * This value is the valid when TPA completion is active. It
+ * This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
* for LRO mode and the length of the first segment in GRO mode.
*
* This value may be used by GRO software to re-construct the original
- * packet stream from the TPA packet. This is the length of all
- * but the last segment for GRO. In LRO mode this value may be used
+ * packet stream from the TPA packet. This is the length of all
+ * but the last segment for GRO. In LRO mode this value may be used
* to indicate MSS size to the stack.
*/
uint16_t tpa_seg_len;
- /* unused4 is 16 b */
- uint16_t unused3;
+ uint16_t unused_1;
uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
- #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
- #define RX_TPA_END_CMPL_ERRORS_SFT 1
+ #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
/*
* This error indicates that there was some sort of problem with
* the BDs for the packet that was found after part of the
- * packet was already placed. The packet should be treated as
+ * packet was already placed. The packet should be treated as
* invalid.
*/
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
+ UINT32_C(0xe)
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
/* No buffer error */
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
(UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
- * the chip only. It indicates that there were not
+ * the chip only. It indicates that there were not
* BDs on chip but that there was adequate reservation.
* provided by the TPA block.
*/
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
/*
* Bad Format:
* BDs were not formatted correctly.
*/
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
- * ring. All data for the TPA operation was not placed.
+ * ring. All data for the TPA operation was not placed.
*
* This error can also be generated when the number of
* segments is not programmed correctly in TPA and the
* 33 total aggregation buffers allowed for the TPA
* operation has been exceeded.
*/
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
/*
* Flush:
* There was a bad_format error on the previous operation
*/
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
(UINT32_C(0x5) << 1)
- #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
- /* unused5 is 16 b */
- uint16_t unused_4;
+ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ uint16_t unused_2;
/*
* This is the opaque value that was completed for the TPA start
* completion that corresponds to this TPA end completion.
uint32_t start_opaque;
} __attribute__((packed));
+/*
+ * This TPA completion structure is used on devices where the
+ * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
+ */
+/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
+struct rx_tpa_v2_abuf_cmpl {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
+ /*
+ * RX TPA Aggregation Buffer completion :
+ * Completion of an L2 aggregation buffer in support of
+ * TPA packet completion. Length = 16B
+ */
+ #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
+ #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
+ RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
+ /*
+ * This is the length of the data for the packet stored in this
+ * aggregation buffer identified by the opaque value. This does not
+ * include the length of any
+ * data placed in other aggregation BDs or in the packet or buffer
+ * BDs. This length does not include any space added due to
+ * hdr_offset register during HDS placement mode.
+ */
+ uint16_t len;
+ /*
+ * This is a copy of the opaque field from the RX BD this aggregation
+ * buffer corresponds to.
+ */
+ uint32_t opaque;
+ uint16_t v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
+ /*
+ * This is the aggregation ID that the completion is associated with. Use
+ * this number to correlate the TPA agg completion with the TPA start
+ * completion and the TPA end completion.
+ */
+ uint16_t agg_id;
+ uint32_t unused_1;
+} __attribute__((packed));
+
/* rx_abuf_cmpl (size:128b/16B) */
struct rx_abuf_cmpl {
uint16_t type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
/*
* RX Aggregation Buffer completion :
* Completion of an L2 aggregation buffer in support of
- * TPA, HDS, or Jumbo packet completion. Length = 16B
+ * TPA, HDS, or Jumbo packet completion. Length = 16B
*/
#define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
#define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
/*
* This is the length of the data for the packet stored in this
- * aggregation buffer identified by the opaque value. This does not
+ * aggregation buffer identified by the opaque value. This does not
* include the length of any
* data placed in other aggregation BDs or in the packet or buffer
- * BDs. This length does not include any space added due to
+ * BDs. This length does not include any space added due to
* hdr_offset register during HDS placement mode.
*/
uint16_t len;
uint32_t v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define RX_ABUF_CMPL_V UINT32_C(0x1)
/* unused3 is 32 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define EJECT_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
+ * error of some type. Type of error is indicated in
* error_flags.
*/
#define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
uint16_t v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define EJECT_CMPL_V UINT32_C(0x1)
#define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
uint32_t v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_CMPL_V UINT32_C(0x1)
/* unused4 is 32 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
uint16_t req_len_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
uint32_t req_buf_addr_v[2];
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
/* Address of forwarded request. */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
uint32_t resp_buf_addr_v[2];
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
/* Address of forwarded request. */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
/*
- * A EEM flow cached memory flush request event being posted to the PF
- * driver.
+ * An EEM flow cached memory flush for all flows request event being
+ * posted to the PF driver.
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
UINT32_C(0x38)
/*
- * A EEM flow cache memory flush completion event being posted to the
+ * An EEM flow cache memory flush completion event being posted to the
* firmware by the PF driver. This is indication that host EEM flush
* has completed by the PF.
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
UINT32_C(0x3a)
/*
- * A eem flow active event being posted to the PF or trusted VF driver
+ * An EEM flow active event being posted to the PF or trusted VF driver
* by the firmware. The PF or trusted VF driver should update the
* flow's aging timer after receiving this async event.
*/
/* TFLIB unique link status changed */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
UINT32_C(0x3e)
+ /*
+ * An event signifying completion for HWRM_FW_STATE_QUIESCE
+ * (completion, timeout, or error)
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
+ UINT32_C(0x3f)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
6
/* Identifiers of events. */
uint16_t event_id;
- /* Notification of a default vnic allocaiton or free */
+ /* Notification of a default vnic allocation or free */
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
UINT32_C(0x35)
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
UINT32_C(0x1)
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
/* opaque is 7 b */
UINT32_C(0x2)
} __attribute__((packed));
+/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_quiesce_done {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Status of HWRM_FW_STATE_QUIESCE completion */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
+ 0
+ /*
+ * The quiesce operation started by HWRM_FW_STATE_QUIESCE
+ * completed successfully.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
+ UINT32_C(0x0)
+ /*
+ * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
+ * out.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
+ UINT32_C(0x1)
+ /*
+ * The quiesce operation started by HWRM_FW_STATE_QUIESCE
+ * encountered an error.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
+ HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
struct hwrm_async_event_cmpl_fw_trace_msg {
uint16_t type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
/* opaque is 7 b */
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
* records.
*/
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
- * for each pass through the completion queue. The even passes
- * will write 1. The odd passes will write 0.
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
/* opaque is 7 b */
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
UINT32_C(0x1000000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then host
+ * must initiate reset or reload (or fastboot) the firmware image
+ * upon detection of device shutdown state.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
+ UINT32_C(0x2000000)
+ /*
+ * If the query is for a VF, then this flag (always set to 0) shall
+ * be ignored. If this query is for a PF and this flag is set to 1,
+ * host, when registered for the default vnic change async event,
+ * receives async notification whenever a default vnic state is
+ * changed for any of child or adopted VFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
+ UINT32_C(0x4000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
UINT32_C(0x80)
+ /*
+ * If set to 1, then this PF is enabled with a preboot driver that
+ * requires access to the legacy L2 ring model and legacy 32b
+ * doorbells. If set to 0, then this PF is not allowed to use
+ * the legacy L2 rings. This feature is not allowed on VFs and
+ * is only relevant for devices that require a context backing
+ * store.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
+ UINT32_C(0x100)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
* the unregister request on PF in the HOT Reset Process.
*/
uint16_t registered_vfs;
- uint8_t unused_1[3];
+ /*
+ * The size of the doorbell BAR in KBytes reserved for L2 including
+ * any area that is shared between L2 and RoCE. The L2 driver
+ * should only map the L2 portion of the doorbell BAR. Any rounding
+ * of the BAR size to the native CPU page size should be performed
+ * by the driver. If the value is zero, no special partitioning
+ * of the doorbell BAR between L2 and RoCE is required.
+ */
+ uint16_t l2_doorbell_bar_size_kb;
+ uint8_t unused_1;
/*
* For backward compatibility this field must be set to 1.
* Older drivers might look for this field to be 1 before
* after receiving the RESET Notify event.
*/
uint32_t reset_addr_poll;
- uint8_t unused_2[3];
+ /*
+ * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
+ * this value to find out the doorbell page offset from the BAR.
+ */
+ uint16_t legacy_l2_db_size_kb;
+ uint8_t unused_2[1];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
UINT32_C(0x1000000)
+ /*
+ * This bit is used by preboot drivers on a PF that require access
+ * to the legacy L2 ring model and legacy 32b doorbells. This
+ * feature is not allowed on VFs and is only relevant for devices
+ * that require a context backing store.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
+ UINT32_C(0x2000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
* Function ID of the function that is being queried.
* 0xFF... (All Fs) if the query is for the requesting
* function.
+ * A privileged PF can query for other function's statistics.
*/
uint16_t fid;
- uint8_t unused_0[6];
+ /* This flags indicates the type of statistics request. */
+ uint8_t flags;
+ /* This value is not used to avoid backward compatibility issues. */
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
+ /*
+ * flags should be set to 1 when request is for only RoCE statistics.
+ * This will be honored only if the caller_fid is a privileged PF.
+ * In all other cases FID and caller_fid should be the same.
+ */
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
+ HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY
+ uint8_t unused_0[5];
} __attribute__((packed));
/* hwrm_func_qstats_output (size:1408b/176B) */
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
UINT32_C(0x20)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * Master capability. The Firmware will use this capability to select the
+ * Master function. The master function will be used to initiate
+ * designated functionality like error recovery etc… If none of the
+ * registered PF’s or trusted VF’s indicate this support, then
+ * firmware will select the 1st registered PF as Master capable instance.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
+ UINT32_C(0x40)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
uint64_t resp_addr;
} __attribute__((packed));
-/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
+/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
struct hwrm_func_backing_store_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
* limitations.
*/
uint8_t tqm_entries_multiple;
+ /*
+ * Initializer to be used by drivers
+ * to initialize context memory to ensure
+ * context subsystem flags an error for an attack
+ * before the first time context load.
+ */
+ uint8_t ctx_kind_initializer;
+ /* Reserved for future. */
+ uint32_t rsvd;
+ /* Reserved for future. */
+ uint16_t rsvd1;
+ /* Reserved for future. */
+ uint8_t rsvd2;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
uint8_t valid;
} __attribute__((packed));
+/*******************************
+ * hwrm_func_host_pf_ids_query *
+ *******************************/
+
+
+/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
+struct hwrm_func_host_pf_ids_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t host;
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to SOC host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP0 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP1 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP2 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
+ /*
+ * # If this bit is set to '1', the query will contain PF(s)
+ * belongs to EP3 host.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
+ /*
+ * This provides a filter of what PF(s) will be returned in the
+ * query..
+ */
+ uint8_t filter;
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field). This includes the hidden PFs.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field) that is available for L2 traffic.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
+ /*
+ * all available PF(s) belong to the host(s) (defined in the
+ * host field) that is available for ROCE traffic.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
+ HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
+ uint8_t unused_1[6];
+} __attribute__((packed));
+
+/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
+struct hwrm_func_host_pf_ids_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This provides the first PF ID of the device. */
+ uint16_t first_pf_id;
+ uint16_t pf_ordinal_mask;
+ /*
+ * When this bit is '1', it indicates first PF belongs to one of
+ * the hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates 2nd PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
+ UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates 3rd PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates 4th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates 5th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
+ UINT32_C(0x10)
+ /*
+ * When this bit is '1', it indicates 6th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', it indicates 7th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', it indicates 8th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', it indicates 9th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', it indicates 10th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', it indicates 11th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
+ UINT32_C(0x400)
+ /*
+ * When this bit is '1', it indicates 12th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
+ UINT32_C(0x800)
+ /*
+ * When this bit is '1', it indicates 13th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
+ UINT32_C(0x1000)
+ /*
+ * When this bit is '1', it indicates 14th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
+ UINT32_C(0x2000)
+ /*
+ * When this bit is '1', it indicates 15th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
+ UINT32_C(0x4000)
+ /*
+ * When this bit is '1', it indicates 16th PF belongs to one of the
+ * hosts defined in the input request.
+ */
+ #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
+ UINT32_C(0x8000)
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/*********************
* hwrm_port_phy_cfg *
*********************/
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
/*
* The HW will be configured with external loopback such that
- * host data is sent on the trasmitter and based on the external
+ * host data is sent on the transmitter and based on the external
* loopback connection the data will be received without modification.
*/
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
UINT32_C(0x40)
uint8_t unused_2[2];
/*
- * Reuested setting of TX LPI timer in microseconds.
+ * Requested setting of TX LPI timer in microseconds.
* This field is valid only when EEE is enabled and TX LPI is
* enabled.
*/
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
/*
* The HW will be configured with external loopback such that
- * host data is sent on the trasmitter and based on the external
+ * host data is sent on the transmitter and based on the external
* loopback connection the data will be received without modification.
*/
#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
UINT32_C(0x100)
/*
- * When this bit is '1', the the Out-Of-Box WoL is requested to
+ * When this bit is '1', the Out-Of-Box WoL is requested to
* be disabled on this port.
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
* This field shall be ignored if the ptp_tx_ts_capture_enable
* flag is not set in this command.
* Otherwise, if bit 'i' is set, then the HWRM is being
- * requested to configure the transmit sied of the port to
+ * requested to configure the transmit side of the port to
* capture the time stamp of every transmitted PTP message
* with messageType field value set to i.
*/
*/
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
UINT32_C(0x2)
+ /*
+ * If set to 1, then this field indicates that the
+ * PHY is capable of supporting loopback in autoneg mode.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Indicates if the configuration of shared PHY settings is supported.
+ * In cases where a physical port is shared by multiple functions
+ * (e.g. NPAR, multihost, etc), the configuration of PHY
+ * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
+ * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
+ UINT32_C(0x8)
/*
* Reserved field. The HWRM shall set this field to 0.
* An HWRM client shall ignore this field.
*/
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
- UINT32_C(0xfc)
- #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
+ UINT32_C(0xf0)
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
/* Number of front panel ports for this device. */
uint8_t port_cnt;
/* Not supported or unknown */
uint8_t valid;
} __attribute__((packed));
+/**********************
+ * hwrm_port_dsc_dump *
+ **********************/
+
+
+/* hwrm_port_dsc_dump_input (size:320b/40B) */
+struct hwrm_port_dsc_dump_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address where response diagnostic data is returned. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware
+ * may use this entire buffer or less than the entire buffer, but
+ * never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where dsc dump to be collected. */
+ uint16_t port_id;
+ /* Diag level specified by the user */
+ uint16_t diag_level;
+ /* SRDS_DIAG_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
+ UINT32_C(0x0)
+ /* SRDS_DIAG_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
+ UINT32_C(0x1)
+ /* SRDS_DIAG_EVENT */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
+ UINT32_C(0x2)
+ /* SRDS_DIAG_EYE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
+ UINT32_C(0x3)
+ /* SRDS_DIAG_REG_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
+ UINT32_C(0x4)
+ /* SRDS_DIAG_REG_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
+ UINT32_C(0x5)
+ /* SRDS_DIAG_UC_CORE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
+ UINT32_C(0x6)
+ /* SRDS_DIAG_UC_LANE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
+ UINT32_C(0x7)
+ /* SRDS_DIAG_LANE_DEBUG */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
+ UINT32_C(0x8)
+ /* SRDS_DIAG_BER_VERT */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
+ UINT32_C(0x9)
+ /* SRDS_DIAG_BER_HORZ */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
+ UINT32_C(0xa)
+ /* SRDS_DIAG_EVENT_SAFE */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
+ UINT32_C(0xb)
+ /* SRDS_DIAG_TIMESTAMP */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
+ UINT32_C(0xc)
+ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
+ HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
+ /*
+ * This field is a lane number
+ * on which to collect the dsc dump
+ */
+ uint16_t lane_number;
+ /*
+ * Configuration bits.
+ * Use enable bit to start dsc dump or retrieve dump
+ */
+ uint16_t dsc_dump_config;
+ /*
+ * Set 0 to retrieve the dsc dump
+ * Set 1 to start the dsc dump
+ */
+ #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/* hwrm_port_dsc_dump_output (size:128b/16B) */
+struct hwrm_port_dsc_dump_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_port_sfp_sideband_cfg *
+ ******************************/
+
+
+/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
+struct hwrm_port_sfp_sideband_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+ /*
+ * This bitfield is used to specify which bits from the 'flags'
+ * fields are being configured by the caller.
+ */
+ uint32_t enables;
+ /* This bit must be '1' for rs0 to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
+ UINT32_C(0x1)
+ /* This bit must be '1' for rs1 to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
+ UINT32_C(0x2)
+ /* This bit must be '1' for tx_disable to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for mod_sel to be configured.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for reset_l to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
+ UINT32_C(0x10)
+ /* This bit must be '1' for lp_mode to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
+ UINT32_C(0x20)
+ /* This bit must be '1' for pwr_disable to be configured. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
+ UINT32_C(0x40)
+ /*
+ * Only bits that have corresponding bits in the 'enables'
+ * bitfield are processed by the firmware, all other bits
+ * of 'flags' are ignored.
+ */
+ uint32_t flags;
+ /*
+ * This bit along with rs1 configures the current speed of the dual
+ * rate module. If these pins are GNDed then the speed can be changed
+ * by driectly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
+ UINT32_C(0x1)
+ /*
+ * This bit along with rs0 configures the current speed of the dual
+ * rate module. If these pins are GNDed then the speed can be changed
+ * by driectly writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
+ UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', tx_disable is set.
+ * On a 1G BASE-T module, if this bit is set,
+ * module PHY registers will not be accessible.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
+ UINT32_C(0x4)
+ /*
+ * When this bit is set to '1', this module is selected.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
+ UINT32_C(0x8)
+ /*
+ * If reset_l is set to 0, Module will be taken out of reset
+ * and other signals will be set to their requested state once
+ * the module is out of reset.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
+ UINT32_C(0x10)
+ /*
+ * When this bit is set to '1', the module will be configured
+ * in low power mode.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
+ UINT32_C(0x20)
+ /* When this bit is set to '1', the module will be powered down. */
+ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
+ UINT32_C(0x40)
+} __attribute__((packed));
+
+/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
+struct hwrm_port_sfp_sideband_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_port_sfp_sideband_qcfg *
+ *******************************/
+
+
+/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
+struct hwrm_port_sfp_sideband_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
+struct hwrm_port_sfp_sideband_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Bitmask indicating which sideband signals are valid.
+ * This is based on the board and nvm cfg that is present on the board.
+ */
+ uint32_t supported_mask;
+ uint32_t sideband_signals;
+ /* When this bit is set to '1', the Module is absent. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
+ UINT32_C(0x1)
+ /*
+ * When this bit is set to '1', there is no valid signal on RX.
+ * This signal is a filtered version of Signal Detect.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
+ UINT32_C(0x2)
+ /*
+ * This bit along with rs1 indiactes the current speed of the dual
+ * rate module.If these pins are grounded then the speed can be
+ * changed by driectky writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
+ UINT32_C(0x4)
+ /*
+ * This bit along with rs0 indiactes the current speed of the dual
+ * rate module.If these pins are grounded then the speed can be
+ * changed by driectky writing to EEPROM.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
+ UINT32_C(0x8)
+ /*
+ * When this bit is set to '1', tx_disable is set.
+ * On a 1G BASE-T module, if this bit is set, module PHY
+ * registers will not be accessible.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
+ UINT32_C(0x10)
+ /* When this bit is set to '1', tx_fault is set. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
+ UINT32_C(0x20)
+ /*
+ * When this bit is set to '1', module is selected.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
+ UINT32_C(0x40)
+ /*
+ * When this bit is set to '0', the module is held in reset.
+ * if reset_l is set to 1,first module is taken out of reset
+ * and other signals will be set to their requested state.
+ * Valid only on QSFP modules.
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
+ UINT32_C(0x80)
+ /*
+ * When this bit is set to '1', the module is in low power mode.
+ * Valid only on QSFP modules
+ */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
+ UINT32_C(0x100)
+ /* When this bit is set to '1', module is in power down state. */
+ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
+ UINT32_C(0x200)
+ uint8_t unused[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************************
+ * hwrm_port_phy_mdio_bus_acquire *
+ **********************************/
+
+
+/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
+struct hwrm_port_phy_mdio_bus_acquire_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of the port. */
+ uint16_t port_id;
+ /*
+ * client_id of the client requesting BUS access.
+ * Any value from 0x10 to 0xFFFF can be used.
+ * Client should make sure that the returned client_id
+ * in response matches the client_id in request.
+ * 0-0xF are reserved for internal use.
+ */
+ uint16_t client_id;
+ /*
+ * Timeout in milli seconds, MDIO BUS will be released automatically
+ * after this time, if another mdio acquire command is not received
+ * within the timeout window from the same client.
+ * A 0xFFFF will hold the bus until this bus is released.
+ */
+ uint16_t mdio_bus_timeout;
+ uint8_t unused_0[2];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_bus_acquire_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t unused_0;
+ /*
+ * client_id of the module holding the BUS.
+ * 0-0xF are reserved for internal use.
+ */
+ uint16_t client_id;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************************
+ * hwrm_port_phy_mdio_bus_release *
+ **********************************/
+
+
+/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
+struct hwrm_port_phy_mdio_bus_release_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of the port. */
+ uint16_t port_id;
+ /*
+ * client_id of the client requesting BUS release.
+ * A client should not release any other clients BUS.
+ */
+ uint16_t client_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_bus_release_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t unused_0;
+ /* The BUS is released if client_id matches the client_id in request. */
+ uint16_t clients_id;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
/*
* Port ID of port for which the queue configuration is being
- * queried. This field is only required when sent by IPC.
+ * queried. This field is only required when sent by IPC.
*/
uint16_t port_id;
/*
HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * This value is a the estimate packet length used in the
+ * This value is the estimate packet length used in the
* TX arbiter.
*/
uint32_t queue_len;
uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* If set to 1, then PFC is requested to be enabled on PRI 1. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
UINT32_C(0x2)
- /* If set to 1, then PFC is requested to be enabled on PRI 2. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 2. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
UINT32_C(0x4)
- /* If set to 1, then PFC is requested to be enabled on PRI 3. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 3. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
UINT32_C(0x8)
- /* If set to 1, then PFC is requested to be enabled on PRI 4. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 4. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
UINT32_C(0x10)
- /* If set to 1, then PFC is requested to be enabled on PRI 5. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 5. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
UINT32_C(0x20)
- /* If set to 1, then PFC is requested to be enabled on PRI 6. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 6. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
UINT32_C(0x40)
- /* If set to 1, then PFC is requested to be enabled on PRI 7. */
+ /* If set to 1, then PFC is requested to be enabled on PRI 7. */
#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
UINT32_C(0x80)
/*
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
/*
* When this bit is set to '0', the query is
- * for VLAN PRI field in tunnel headers.
+ * for PRI from tunnel headers.
* When this bit is set to '1', the query is
- * for VLAN PRI field in inner packet headers.
+ * for PRI from inner packet headers.
*/
#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
/*
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * CoS Queue assigned to priority 0. This value can only
+ * CoS Queue assigned to priority 0. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri0_cos_queue_id;
/*
- * CoS Queue assigned to priority 1. This value can only
+ * CoS Queue assigned to priority 1. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri1_cos_queue_id;
/*
- * CoS Queue assigned to priority 2 This value can only
+ * CoS Queue assigned to priority 2. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri2_cos_queue_id;
/*
- * CoS Queue assigned to priority 3. This value can only
+ * CoS Queue assigned to priority 3. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri3_cos_queue_id;
/*
- * CoS Queue assigned to priority 4. This value can only
+ * CoS Queue assigned to priority 4. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri4_cos_queue_id;
/*
- * CoS Queue assigned to priority 5. This value can only
+ * CoS Queue assigned to priority 5. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri5_cos_queue_id;
/*
- * CoS Queue assigned to priority 6. This value can only
+ * CoS Queue assigned to priority 6. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
*/
uint8_t pri6_cos_queue_id;
/*
- * CoS Queue assigned to priority 7. This value can only
+ * CoS Queue assigned to priority 7. This value can only
* be changed before traffic has started.
* A value of 0xff indicates that no CoS queue is assigned to the
* specified priority.
uint8_t unused_0[6];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
/*
* When this bit is set to '0', the mapping is requested
- * for VLAN PRI field in tunnel headers.
+ * for PRI from tunnel headers.
* When this bit is set to '1', the mapping is requested
- * for VLAN PRI field in inner packet headers.
+ * for PRI from inner packet headers.
*/
#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
uint32_t enables;
*/
uint8_t port_id;
/*
- * CoS Queue assigned to priority 0. This value can only
+ * CoS Queue assigned to priority 0. This value can only
* be changed before traffic has started.
*/
uint8_t pri0_cos_queue_id;
/*
- * CoS Queue assigned to priority 1. This value can only
+ * CoS Queue assigned to priority 1. This value can only
* be changed before traffic has started.
*/
uint8_t pri1_cos_queue_id;
*/
uint8_t pri2_cos_queue_id;
/*
- * CoS Queue assigned to priority 3. This value can only
+ * CoS Queue assigned to priority 3. This value can only
* be changed before traffic has started.
*/
uint8_t pri3_cos_queue_id;
/*
- * CoS Queue assigned to priority 4. This value can only
+ * CoS Queue assigned to priority 4. This value can only
* be changed before traffic has started.
*/
uint8_t pri4_cos_queue_id;
/*
- * CoS Queue assigned to priority 5. This value can only
+ * CoS Queue assigned to priority 5. This value can only
* be changed before traffic has started.
*/
uint8_t pri5_cos_queue_id;
/*
- * CoS Queue assigned to priority 6. This value can only
+ * CoS Queue assigned to priority 6. This value can only
* be changed before traffic has started.
*/
uint8_t pri6_cos_queue_id;
/*
- * CoS Queue assigned to priority 7. This value can only
+ * CoS Queue assigned to priority 7. This value can only
* be changed before traffic has started.
*/
uint8_t pri7_cos_queue_id;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_2[4];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_queue_dscp_qcaps *
+ *************************/
+
+
+/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
+struct hwrm_queue_dscp_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
+/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
+struct hwrm_queue_dscp_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of bits provided by the hardware for the DSCP value. */
+ uint8_t num_dscp_bits;
+ uint8_t unused_0;
+ /* Max number of DSCP-MASK-PRI entries supported. */
+ uint16_t max_entries;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/****************************
+ * hwrm_queue_dscp2pri_qcfg *
+ ****************************/
+
+
+/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
+struct hwrm_queue_dscp2pri_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * This is the host address where the 24-bits DSCP-MASK-PRI
+ * tuple(s) will be copied to.
+ */
+ uint64_t dest_data_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0;
+ /* Size of the buffer pointed to by dest_data_addr. */
+ uint16_t dest_data_buffer_size;
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
+struct hwrm_queue_dscp2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
+ * by the dest_data_addr.
+ */
+ uint16_t entry_cnt;
+ /*
+ * This is the default PRI which un-initialized DSCP values are
+ * mapped to.
+ */
+ uint8_t default_pri;
+ uint8_t unused_0[4];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_queue_dscp2pri_cfg *
+ ***************************/
+
+
+/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
+struct hwrm_queue_dscp2pri_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * This is the host address where the 24-bits DSCP-MASK-PRI tuple
+ * will be copied from.
+ */
+ uint64_t src_data_addr;
+ uint32_t flags;
+ /* use_hw_default_pri is 1 b */
+ #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the default_pri field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
+ UINT32_C(0x1)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure pri2cos mapping on this port.
+ */
+ uint8_t port_id;
+ /*
+ * This is the default PRI which un-initialized DSCP values will be
+ * mapped to.
+ */
+ uint8_t default_pri;
+ /*
+ * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
+ * to by src_data_addr.
+ */
+ uint16_t entry_cnt;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_dscp2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_queue_mpls_qcaps *
+ *************************/
+
+
+/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
+struct hwrm_queue_mpls_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP) to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
+/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
+struct hwrm_queue_mpls_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Bitmask indicating which queues can be configured by the
+ * hwrm_queue_mplstc2pri_cfg command.
+ *
+ * Each bit represents a specific pri where bit 0 represents
+ * pri 0 and bit 7 represents pri 7.
+ * # A value of 0 indicates that the pri is not configurable
+ * by the hwrm_queue_mplstc2pri_cfg command.
+ * # A value of 1 indicates that the pri is configurable.
+ * # A hwrm_queue_mplstc2pri_cfg command shall return error when
+ * trying to configure a pri that is not configurable.
+ */
+ uint8_t queue_mplstc2pri_cfg_allowed;
+ /*
+ * This is the default PRI which un-initialized MPLS values will be
+ * mapped to.
+ */
+ uint8_t hw_default_pri;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_queue_mplstc2pri_qcfg *
+ ******************************/
+
+
+/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
+struct hwrm_queue_mplstc2pri_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP) to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
+/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
+struct hwrm_queue_mplstc2pri_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * pri assigned to MPLS TC(EXP) 0. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 0.
+ */
+ uint8_t tc0_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 1. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 1.
+ */
+ uint8_t tc1_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 2. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 2.
+ */
+ uint8_t tc2_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 3. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 3.
+ */
+ uint8_t tc3_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 4. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 4.
+ */
+ uint8_t tc4_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 5. This value can only be changed
+ * before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 5.
+ */
+ uint8_t tc5_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 6. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 6.
+ */
+ uint8_t tc6_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 7. This value can only
+ * be changed before traffic has started.
+ * A value of 0xff indicates that no pri is assigned to the
+ * MPLS TC(EXP) 7.
+ */
+ uint8_t tc7_pri_queue_id;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*****************************
+ * hwrm_queue_mplstc2pri_cfg *
+ *****************************/
+
+
+/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
+struct hwrm_queue_mplstc2pri_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the mplstc0_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the mplstc1_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the mplstc2_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the mplstc3_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the mplstc4_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the mplstc5_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the mplstc6_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the mplstc7_pri_queue_id field to be
+ * configured.
+ */
+ #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
+ UINT32_C(0x80)
+ /*
+ * Port ID of port for which the table is being configured.
+ * The HWRM needs to check whether this function is allowed
+ * to configure MPLS TC(EXP)to pri mapping on this port.
+ */
+ uint8_t port_id;
+ uint8_t unused_0[3];
+ /*
+ * pri assigned to MPLS TC(EXP) 0. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc0_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 1. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc1_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 2 This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc2_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 3. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc3_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 4. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc4_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 5. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc5_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 6. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc6_pri_queue_id;
+ /*
+ * pri assigned to MPLS TC(EXP) 7. This value can only
+ * be changed before traffic has started.
+ */
+ uint8_t tc7_pri_queue_id;
+} __attribute__((packed));
+
+/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
+struct hwrm_queue_mplstc2pri_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*****************/
-/* hwrm_vnic_cfg_input (size:320b/40B) */
+/* hwrm_vnic_cfg_input (size:384b/48B) */
struct hwrm_vnic_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
*/
#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
UINT32_C(0x40)
+ /* This bit must be '1' for the queue_id field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
+ UINT32_C(0x80)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* be chosen if packet does not match any RSS rules.
*/
uint16_t default_cmpl_ring_id;
+ /*
+ * When specified, only incoming packets classified to the specified CoS
+ * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
+ * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
+ * ntuple filters with VNIC destination specified are invalid since they
+ * conflict with the the CoS to VNIC steering rules in this mode.
+ *
+ * If this field is not specified, packet to VNIC steering will be
+ * subject to the standard L2 filter rules and any additional ntuple
+ * filter rules with destination VNIC specified.
+ */
+ uint16_t queue_id;
+ uint8_t unused0[6];
} __attribute__((packed));
/* hwrm_vnic_cfg_output (size:128b/16B) */
*/
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
UINT32_C(0x40)
- uint8_t unused_1[7];
+ /*
+ * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
+ * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
+ * queue association.
+ */
+ uint16_t queue_id;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
+ /*
+ * When this bit is '1', it indicates that firmware supports the
+ * ability to steer incoming packets from one CoS queue to one
+ * VNIC. This optional feature can then be enabled
+ * using HWRM_VNIC_CFG on any VNIC. This feature is only
+ * available when NVM option “enable_cos_classfication” is set
+ * to 1. If set to '0', firmware does not support this feature.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
+ UINT32_C(0x100)
/*
* This field advertises the maximum concurrent TPA aggregations
* supported by the VNIC on new devices that support TPA v2.
uint8_t valid;
} __attribute__((packed));
+/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
+struct hwrm_vnic_rss_cfg_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
+ UINT32_C(0x0)
+ /*
+ * Unable to change global RSS mode to outer due to all active
+ * interfaces are not ready to support outer RSS hashing.
+ */
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
+ UINT32_C(0x1)
+ #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
+ HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_vnic_rss_qcfg *
**********************/
/*
* This value is used to determine the offset into
* packet buffer where the split data (payload) will be
- * placed according to one of of HDS placement algorithm.
+ * placed according to one of HDS placement algorithm.
*
* The lengths of packet buffers provided for split data
* shall be larger than this value.
/*
* This value is used to determine the offset into
* packet buffer where the split data (payload) will be
- * placed according to one of of HDS placement algorithm.
+ * placed according to one of HDS placement algorithm.
*
* The lengths of packet buffers provided for split data
* shall be larger than this value.
UINT32_C(0x40)
/*
* Setting this flag to 1 indicate the L2 fields in this command
- * pertain to source fields. Setting this flag to 0 indicate the
+ * pertain to source fields. Setting this flag to 0 indicate the
* L2 fields in this command pertain to the destination fields
* and this is the default/legacy behavior.
*/
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
UINT32_C(0x6)
/* VLAN */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
/*
- * Setting of this flag indicates that the dest_id field contains function ID.
+ * Setting of this flag indicates that the dst_id field contains function ID.
* If this is not set it indicates dest_id is VNIC or VPORT.
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
UINT32_C(0x8)
+ /*
+ * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
+ * If this is not set it indicates no specific arp opcode matching.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
+ UINT32_C(0x10)
+ /*
+ * Setting of this flag indicates that the dst_id field contains RFS ring
+ * table index. If this is not set it indicates dst_id is VNIC or VPORT
+ * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
+ * the same time.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
- /*
- * This bit must be '1' for the rfs_ring_tbl_idx field to be
- * configured.
- */
+ /* This flag is deprecated. */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
UINT32_C(0x80000)
/*
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
- /*
- * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
- * This index is used in lieu of the RSS hash when selecting the
- * index into the RSS table to determine the rx ring.
- */
- uint16_t rfs_ring_tbl_idx;
- uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates that the new_dst_id field contains
+ * RFS ring table index. If this is not set it indicates new_dst_id is
+ * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
+ * can’t be set at the same time.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
+ UINT32_C(0x2)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
UINT32_C(0x800)
/*
* If set to 1 an attempt will be made to try to offload this flow to the
- * most optimal flow table resource. If set to 0, the flow will be
+ * most optimal flow table resource. If set to 0, the flow will be
* placed to the default flow table resource.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
* If set to 1 there will be no attempt to allocate an on-chip try to
* offload this flow. If set to 0, which will keep compatibility with the
* older drivers, will cause the FW to attempt to allocate an on-chip flow
- * counter for the newly created flow. This will keep the existing behavior
+ * counter for the newly created flow. This will keep the existing behavior
* with EM flows which always had an associated flow counter.
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x80)
- /* Setting of this flag indicates encap action.. */
+ /* Setting of this flag indicates encap action. */
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
UINT32_C(0x100)
- /* Setting of this flag indicates decap action.. */
+ /* Setting of this flag indicates decap action. */
#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
UINT32_C(0x200)
/* Meter id. */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
/* VLAN */
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
UINT32_C(0x1)
/*
* Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
- * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
* setting this flag has no effect.
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
+ * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
+ UINT32_C(0x4)
/* Set to 1 to indicate the flow counter IDs are included in the flow table. */
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
UINT32_C(0x8000000)
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* Generic Network Virtualization Encapsulation (Geneve) */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
+ /* Multi-Protocol Label Switching (MPLS) */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
UINT32_C(0x40)
/* Stateless Transport Tunnel (STT) */
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
- * Id/Handle to the recently register context memory. This handle is passed
+ * Id/Handle to the recently register context memory. This handle is passed
* to the CFA feature.
*/
uint16_t ctx_id;
uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
uint64_t resp_addr;
/*
- * Id/Handle to the recently register context memory. This handle is passed
+ * Id/Handle to the recently register context memory. This handle is passed
* to the CFA feature.
*/
uint16_t ctx_id;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
uint64_t resp_addr;
/*
- * Id/Handle to the recently register context memory. This handle is passed
+ * Id/Handle to the recently register context memory. This handle is passed
* to the CFA feature.
*/
uint16_t ctx_id;
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint16_t resp_len;
/* Indicates the maximum number of context memory which can be registered. */
uint16_t max_entries;
- uint8_t unused_0[6];
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
/**********************
uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
struct hwrm_cfa_eem_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
UINT32_C(0x2)
/*
* When set to 1, indicates the the FW supports the Centralized
- * Memory Model. The concept designates one entity for the
+ * Memory Model. The concept designates one entity for the
* memory allocation while all others ‘subscribe’ to it.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
UINT32_C(0x4)
/*
* When set to 1, indicates the the FW supports the Detached
- * Centralized Memory Model. The memory is allocated and managed
- * as a separate entity. All PFs and VFs will be granted direct
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
* or semi-direct access to the allocated memory while none of
* which can interfere with the management of the memory.
*/
uint32_t supported;
/*
* If set to 1, then EEM KEY0 table is supported using crc32 hash.
- * If set to 0 EEM KEY0 table is not supported.
+ * If set to 0, EEM KEY0 table is not supported.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
UINT32_C(0x1)
/*
* If set to 1, then EEM KEY1 table is supported using lookup3 hash.
- * If set to 0 EEM KEY1 table is not supported.
+ * If set to 0, EEM KEY1 table is not supported.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
UINT32_C(0x2)
/*
* If set to 1, then EEM External Record table is supported.
- * If set to 0 EEM External Record table is not supported.
+ * If set to 0, EEM External Record table is not supported.
* (This table includes action record, EFC pointers, encap pointers)
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
UINT32_C(0x4)
/*
* If set to 1, then EEM External Flow Counters table is supported.
- * If set to 0 EEM External Flow Counters table is not supported.
+ * If set to 0, EEM External Flow Counters table is not supported.
*/
#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
UINT32_C(0x8)
/*
- * The maximum number of entries supported by EEM. When configuring the host memory
+ * If set to 1, then FID table used for implicit flow flush is supported.
+ * If set to 0, then FID table used for implicit flow flush is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
+ UINT32_C(0x10)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
* the number of numbers of entries that can supported are -
* 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
* Any value that are not these values, the FW will round down to the closest support
* number of entries.
*/
uint32_t max_entries_supported;
- /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
uint16_t key_entry_size;
- /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ /* The entry size in bytes of each entry in the EEM RECORD tables. */
uint16_t record_entry_size;
- /* The entry size in bytes of each entry in the EFC EEM tables. */
+ /* The entry size in bytes of each entry in the EEM EFC tables. */
uint16_t efc_entry_size;
- uint8_t unused_1;
+ /* The FID size in bytes of each entry in the EEM FID tables. */
+ uint16_t fid_entry_size;
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
********************/
-/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+/* hwrm_cfa_eem_cfg_input (size:384b/48B) */
struct hwrm_cfa_eem_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
uint16_t group_id;
uint16_t unused_0;
/*
- * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
- * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
*/
uint32_t num_entries;
uint32_t unused_1;
uint16_t record_ctx_id;
/* Configured EEM with the given context if for EFC table. */
uint16_t efc_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t fid_ctx_id;
+ uint16_t unused_2;
+ uint32_t unused_3;
} __attribute__((packed));
/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
UINT32_C(0x4)
/* The number of entries the FW has configured for EEM. */
uint32_t num_entries;
- uint8_t unused_0[7];
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t fid_ctx_id;
+ uint8_t unused_2[5];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
/*
* To properly stop EEM and ensure there are no DMA's, the caller
- * must disable EEM for the given PF, using this call. This will
+ * must disable EEM for the given PF, using this call. This will
* safely disable EEM and ensure that all DMA'ed to the
* keys/records/efc have been completed.
*/
/*
* Once the EEM host memory has been configured, EEM options have
* been configured. Then the caller should enable EEM for the given
- * PF. Note once this call has been made, then the EEM mechanism
+ * PF. Note once this call has been made, then the EEM mechanism
* will be active and DMA's will occur as packets are processed.
*/
#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
UINT32_C(0x800)
+ /*
+ * If set to 1, firmware is capable of supporting ARP ethertype as
+ * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
+ * RX direction. By default, this flag should be 0 for older version
+ * of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
+ UINT32_C(0x1000)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
+ * command. Value of 0 indicates firmware does not support
+ * rfs_ring_tbl_idx in dst_id field.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ UINT32_C(0x2000)
+ /*
+ * If set to 1, firmware is capable of supporting IPv4/IPv6 as
+ * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
+ * direction. By default, this flag should be 0 for older version
+ * of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
+ UINT32_C(0x4000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint8_t unused1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
* When writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic statistics context DMA to host. */
+/* ctx_hw_stats_ext (size:1344b/168B) */
+struct ctx_hw_stats_ext {
+ /* Number of received unicast packets */
+ uint64_t rx_ucast_pkts;
+ /* Number of received multicast packets */
+ uint64_t rx_mcast_pkts;
+ /* Number of received broadcast packets */
+ uint64_t rx_bcast_pkts;
+ /* Number of discarded packets on received path */
+ uint64_t rx_discard_pkts;
+ /* Number of dropped packets on received path */
+ uint64_t rx_drop_pkts;
+ /* Number of received bytes for unicast traffic */
+ uint64_t rx_ucast_bytes;
+ /* Number of received bytes for multicast traffic */
+ uint64_t rx_mcast_bytes;
+ /* Number of received bytes for broadcast traffic */
+ uint64_t rx_bcast_bytes;
+ /* Number of transmitted unicast packets */
+ uint64_t tx_ucast_pkts;
+ /* Number of transmitted multicast packets */
+ uint64_t tx_mcast_pkts;
+ /* Number of transmitted broadcast packets */
+ uint64_t tx_bcast_pkts;
+ /* Number of discarded packets on transmit path */
+ uint64_t tx_discard_pkts;
+ /* Number of dropped packets on transmit path */
+ uint64_t tx_drop_pkts;
+ /* Number of transmitted bytes for unicast traffic */
+ uint64_t tx_ucast_bytes;
+ /* Number of transmitted bytes for multicast traffic */
+ uint64_t tx_mcast_bytes;
+ /* Number of transmitted bytes for broadcast traffic */
+ uint64_t tx_bcast_bytes;
+ /* Number of TPA eligible packets */
+ uint64_t rx_tpa_eligible_pkt;
+ /* Number of TPA eligible bytes */
+ uint64_t rx_tpa_eligible_bytes;
+ /* Number of TPA packets */
+ uint64_t rx_tpa_pkt;
+ /* Number of TPA bytes */
+ uint64_t rx_tpa_bytes;
+ /* Number of TPA errors */
+ uint64_t rx_tpa_errors;
+} __attribute__((packed));
+
/* Periodic Engine statistics context DMA to host. */
/* ctx_eng_stats (size:512b/64B) */
struct ctx_eng_stats {
* shall be never done and the DMA address shall not be used.
* In this case, the stat block can only be read by
* hwrm_stat_ctx_query command.
+ * On Ethernet/L2 based devices:
+ * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
+ * ctx_hw_stats_ext is used for DMA,
+ * else
+ * ctx_hw_stats is used for DMA.
*/
uint32_t update_period_ms;
/*
* used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
- uint8_t unused_0[3];
+ uint8_t unused_0;
+ /*
+ * This is the size of the structure (ctx_hw_stats or
+ * ctx_hw_stats_ext) that the driver has allocated to be used
+ * for the periodic DMA updates.
+ */
+ uint16_t stats_dma_length;
} __attribute__((packed));
/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
uint64_t pcie_tl_signal_integrity;
/* Number of times LTSSM entered Recovery state */
uint64_t pcie_link_integrity;
- /* Number of TLP bytes that have been trasmitted */
+ /* Number of TLP bytes that have been transmitted */
uint64_t pcie_tx_traffic_rate;
/* Number of TLP bytes that have been received */
uint64_t pcie_rx_traffic_rate;
- /* Number of DLLP bytes that have been trasmitted */
+ /* Number of DLLP bytes that have been transmitted */
uint64_t pcie_tx_dllp_statistics;
/* Number of DLLP bytes that have been received */
uint64_t pcie_rx_dllp_statistics;
uint64_t resp_addr;
/*
* 64-bit Host Source Address.
- * This is the loation of the source data to be written.
+ * This is the location of the source data to be written.
*/
uint64_t host_src_addr;
/*
* The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
* If this value is less than the specified data length, it will be ignored.
* The response will contain the actual allocated item length, which may be greater than the requested item length.
- * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
+ * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
* the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
*/
uint32_t dir_item_length;
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
UINT32_C(0x1)
/*
- * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
+ * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
* When combined with erase_unused_space then unspecified images will be securely erased.
*/
#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
(UINT32_C(0x3) << 1)
#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
+ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
+ UINT32_C(0x70)
+ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
+ /* When this bit is 1, update the factory default region */
+ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
+ UINT32_C(0x80)
uint8_t unused_0;
} __attribute__((packed));
uint8_t unused_0[7];
} __attribute__((packed));
+/*****************
+ * hwrm_fw_reset *
+ ******************/
+
+
+/* hwrm_fw_reset_input (size:192b/24B) */
+struct hwrm_fw_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Type of embedded processor. */
+ uint8_t embedded_proc_type;
+ /* Boot Processor */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
+ UINT32_C(0x0)
+ /* Management Processor */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
+ UINT32_C(0x1)
+ /* Network control processor */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
+ UINT32_C(0x2)
+ /* RoCE control processor */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
+ UINT32_C(0x3)
+ /*
+ * Host (in multi-host environment): This is only valid if requester is IPC.
+ * Reinit host hardware resources and PCIe.
+ */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
+ UINT32_C(0x4)
+ /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
+ UINT32_C(0x5)
+ /* Reset all blocks of the chip (including all processors) */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
+ UINT32_C(0x6)
+ /*
+ * Host (in multi-host environment): This is only valid if requester is IPC.
+ * Reinit host hardware resources.
+ */
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
+ UINT32_C(0x7)
+ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
+ HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
+ /* Type of self reset. */
+ uint8_t selfrst_status;
+ /* No Self Reset */
+ #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
+ UINT32_C(0x0)
+ /* Self Reset as soon as possible to do so safely */
+ #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
+ UINT32_C(0x1)
+ /* Self Reset on PCIe Reset */
+ #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
+ UINT32_C(0x2)
+ /* Self Reset immediately after notification to all clients. */
+ #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
+ UINT32_C(0x3)
+ #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
+ HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
+ /*
+ * Indicate which host is being reset. 0 means first host.
+ * Only valid when embedded_proc_type is host in multihost
+ * environment
+ */
+ uint8_t host_idx;
+ uint8_t flags;
+ /*
+ * When this bit is '1', then the core firmware initiates
+ * the reset only after graceful shut down of all registered instances.
+ * If not, the device will continue with the existing firmware.
+ */
+ #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_fw_reset_output (size:128b/16B) */
+struct hwrm_fw_reset_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Type of self reset. */
+ uint8_t selfrst_status;
+ /* No Self Reset */
+ #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
+ UINT32_C(0x0)
+ /* Self Reset as soon as possible to do so safely */
+ #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
+ UINT32_C(0x1)
+ /* Self Reset on PCIe Reset */
+ #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
+ UINT32_C(0x2)
+ /* Self Reset immediately after notification to all clients. */
+ #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
+ UINT32_C(0x3)
+ #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
+ HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
+ uint8_t unused_0[6];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_port_ts_query *
+ ***********************/
+
+
+/* hwrm_port_ts_query_input (size:192b/24B) */
+struct hwrm_port_ts_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
+ /* tx path */
+ #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
+ /* rx path */
+ #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
+ #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
+ HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
+ /*
+ * If set, the response includes the current value of the free
+ * running timer.
+ */
+ #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
+ /* Port ID of port that is being queried. */
+ uint16_t port_id;
+ uint8_t unused_0[2];
+} __attribute__((packed));
+
+/* hwrm_port_ts_query_output (size:192b/24B) */
+struct hwrm_port_ts_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Timestamp value of PTP message captured, or current value of
+ * free running timer.
+ */
+ uint32_t ptp_msg_ts[2];
+ /* Sequence ID of the PTP message captured. */
+ uint16_t ptp_msg_seqid;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
#endif /* _HSI_STRUCT_DEF_DPDK_H_ */