#define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
#define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
#define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
+#define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
#define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
#define HWRM_VNIC_ALLOC (UINT32_C(0x40))
#define HWRM_VNIC_FREE (UINT32_C(0x41))
+#define HWRM_VNIC_CFG (UINT32_C(0x42))
+#define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
+#define HWRM_RING_ALLOC (UINT32_C(0x50))
+#define HWRM_RING_FREE (UINT32_C(0x51))
+#define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
+#define HWRM_RING_GRP_FREE (UINT32_C(0x61))
+#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
+#define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
#define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
#define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
#define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
#define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
+#define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
+#define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
#define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
#define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_l2_set_rx_mask */
+/* Description: This command will set rx mask of the function. */
+
+/* Input (40 bytes) */
+struct hwrm_cfa_l2_set_rx_mask_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /* VNIC ID */
+ uint32_t vnic_id;
+
+ /* Reserved for future use. */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_RESERVED UINT32_C(0x1)
+ /*
+ * When this bit is '1', the function is requested to accept multi-cast
+ * packets specified by the multicast addr table.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
+ /*
+ * When this bit is '1', the function is requested to accept all multi-
+ * cast packets.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
+ /*
+ * When this bit is '1', the function is requested to accept broadcast
+ * packets.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is requested to be put in the
+ * promiscuous mode. The HWRM should accept any function to set up
+ * promiscuous mode. The HWRM shall follow the semantics below for the
+ * promiscuous mode support. # When partitioning is not enabled on a
+ * port (i.e. single PF on the port), then the PF shall be allowed to be
+ * in the promiscuous mode. When the PF is in the promiscuous mode, then
+ * it shall receive all host bound traffic on that port. # When
+ * partitioning is enabled on a port (i.e. multiple PFs per port) and a
+ * PF on that port is in the promiscuous mode, then the PF receives all
+ * traffic within that partition as identified by a unique identifier
+ * for the PF (e.g. S-Tag). If a unique outer VLAN for the PF is
+ * specified, then the setting of promiscuous mode on that PF shall
+ * result in the PF receiving all host bound traffic with matching outer
+ * VLAN. # A VF shall can be set in the promiscuous mode. In the
+ * promiscuous mode, the VF does not receive any traffic unless a unique
+ * outer VLAN for the VF is specified. If a unique outer VLAN for the VF
+ * is specified, then the setting of promiscuous mode on that VF shall
+ * result in the VF receiving all host bound traffic with the matching
+ * outer VLAN. # The HWRM shall allow the setting of promiscuous mode on
+ * a function independently from the promiscuous mode settings on other
+ * functions.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
+ /*
+ * If this flag is set, the corresponding RX filters shall be set up to
+ * cover multicast/broadcast filters for the outermost Layer 2
+ * destination MAC address field.
+ */
+ #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
+ uint32_t mask;
+
+ /* This is the address for mcast address tbl. */
+ uint64_t mc_tbl_addr;
+
+ /*
+ * This value indicates how many entries in mc_tbl are valid. Each entry
+ * is 6 bytes.
+ */
+ uint32_t num_mc_entries;
+
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_cfa_l2_set_rx_mask_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/* hwrm_exec_fwd_resp */
/*
* Description: This command is used to send an encapsulated request to the
uint8_t valid;
} __attribute__((packed));
-/* hwrm_ver_get */
-/*
- * Description: This function is called by a driver to determine the HWRM
- * interface version supported by the HWRM firmware, the version of HWRM
- * firmware implementation, the name of HWRM firmware, the versions of other
- * embedded firmwares, and the names of other embedded firmwares, etc. Any
- * interface or firmware version with major = 0, minor = 0, and update = 0 shall
- * be considered an invalid version.
- */
-
+/* hwrm_port_phy_qcfg */
+/* Description: This command queries the PHY configuration for the port. */
/* Input (24 bytes) */
-struct hwrm_ver_get_input {
+
+struct hwrm_port_phy_qcfg_input {
/*
* This value indicates what type of request this is. The format for the
* rest of the command is determined by this field.
*/
uint64_t resp_addr;
- /*
- * This field represents the major version of HWRM interface
- * specification supported by the driver HWRM implementation. The
- * interface major version is intended to change only when non backward
- * compatible changes are made to the HWRM interface specification.
- */
- uint8_t hwrm_intf_maj;
-
- /*
- * This field represents the minor version of HWRM interface
- * specification supported by the driver HWRM implementation. A change
- * in interface minor version is used to reflect significant backward
- * compatible modification to HWRM interface specification. This can be
- * due to addition or removal of functionality. HWRM interface
- * specifications with the same major version but different minor
- * versions are compatible.
- */
- uint8_t hwrm_intf_min;
-
- /*
- * This field represents the update version of HWRM interface
- * specification supported by the driver HWRM implementation. The
- * interface update version is used to reflect minor changes or bug
- * fixes to a released HWRM interface specification.
- */
- uint8_t hwrm_intf_upd;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
- uint8_t unused_0[5];
+ uint16_t unused_0[3];
} __attribute__((packed));
-/* Output (128 bytes) */
-struct hwrm_ver_get_output {
+/* Output (96 bytes) */
+struct hwrm_port_phy_qcfg_output {
/*
* Pass/Fail or error type Note: receiver to verify the in parameters,
* and fail the call with an error when appropriate
*/
uint16_t resp_len;
- /*
- * This field represents the major version of HWRM interface
- * specification supported by the HWRM implementation. The interface
- * major version is intended to change only when non backward compatible
- * changes are made to the HWRM interface specification. A HWRM
- * implementation that is compliant with this specification shall
- * provide value of 1 in this field.
- */
- uint8_t hwrm_intf_maj;
+ /* This value indicates the current link status. */
+ /* There is no link or cable detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK (UINT32_C(0x0) << 0)
+ /* There is no link, but a cable has been detected. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL (UINT32_C(0x1) << 0)
+ /* There is a link. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK (UINT32_C(0x2) << 0)
+ uint8_t link;
- /*
- * This field represents the minor version of HWRM interface
- * specification supported by the HWRM implementation. A change in
- * interface minor version is used to reflect significant backward
- * compatible modification to HWRM interface specification. This can be
- * due to addition or removal of functionality. HWRM interface
- * specifications with the same major version but different minor
- * versions are compatible. A HWRM implementation that is compliant with
- * this specification shall provide value of 0 in this field.
- */
- uint8_t hwrm_intf_min;
+ uint8_t unused_0;
- /*
- * This field represents the update version of HWRM interface
- * specification supported by the HWRM implementation. The interface
- * update version is used to reflect minor changes or bug fixes to a
- * released HWRM interface specification. A HWRM implementation that is
- * compliant with this specification shall provide value of 1 in this
- * field.
- */
- uint8_t hwrm_intf_upd;
+ /* This value indicates the current link speed of the connection. */
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB \
+ (UINT32_C(0x1) << 0)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB \
+ (UINT32_C(0xa) << 0)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB \
+ (UINT32_C(0x14) << 0)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB \
+ (UINT32_C(0x19) << 0)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB \
+ (UINT32_C(0x64) << 0)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB \
+ (UINT32_C(0xc8) << 0)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB \
+ (UINT32_C(0xfa) << 0)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB \
+ (UINT32_C(0x190) << 0)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB \
+ (UINT32_C(0x1f4) << 0)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB \
+ (UINT32_C(0x3e8) << 0)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB \
+ (UINT32_C(0xffff) << 0)
+ uint16_t link_speed;
- uint8_t hwrm_intf_rsvd;
+ /* This value is indicates the duplex of the current connection. */
+ /* Half Duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_HALF (UINT32_C(0x0) << 0)
+ /* Full duplex connection. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL (UINT32_C(0x1) << 0)
+ uint8_t duplex;
/*
- * This field represents the major version of HWRM firmware. A change in
- * firmware major version represents a major firmware release.
+ * This value is used to indicate the current pause configuration. When
+ * autoneg is enabled, this value represents the autoneg results of
+ * pause configuration.
*/
- uint8_t hwrm_fw_maj;
-
/*
- * This field represents the minor version of HWRM firmware. A change in
- * firmware minor version represents significant firmware functionality
- * changes.
+ * When this bit is '1', Generation of tx pause messages is supported.
+ * Disabled otherwise.
*/
- uint8_t hwrm_fw_min;
-
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
/*
- * This field represents the build version of HWRM firmware. A change in
- * firmware build version represents bug fixes to a released firmware.
+ * When this bit is '1', Reception of rx pause messages is supported.
+ * Disabled otherwise.
*/
- uint8_t hwrm_fw_bld;
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
+ uint8_t pause;
/*
- * This field is a reserved field. This field can be used to represent
- * firmware branches or customer specific releases tied to a specific
- * (major,minor,update) version of the HWRM firmware.
+ * The supported speeds for the port. This is a bit mask. For each speed
+ * that is supported, the corrresponding bit will be set to '1'.
*/
- uint8_t hwrm_fw_rsvd;
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
+ UINT32_C(0x10)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
+ UINT32_C(0x2000)
+ uint16_t support_speeds;
/*
- * This field represents the major version of mgmt firmware. A change in
- * major version represents a major release.
+ * Current setting of forced link speed. When the link speed is not
+ * being forced, this value shall be set to 0.
*/
- uint8_t mgmt_fw_maj;
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB \
+ (UINT32_C(0x1) << 0)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB \
+ (UINT32_C(0xa) << 0)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB \
+ (UINT32_C(0x14) << 0)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB \
+ (UINT32_C(0x19) << 0)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB \
+ (UINT32_C(0x64) << 0)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB \
+ (UINT32_C(0xc8) << 0)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB \
+ (UINT32_C(0xfa) << 0)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
+ (UINT32_C(0x190) << 0)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
+ (UINT32_C(0x1f4) << 0)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
+ (UINT32_C(0x3e8) << 0)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
+ (UINT32_C(0xffff) << 0)
+ uint16_t force_link_speed;
+ /* Current setting of auto negotiation mode. */
+ /*
+ * Disable autoneg or autoneg disabled. No speeds are selected.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE \
+ (UINT32_C(0x0) << 0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS \
+ (UINT32_C(0x1) << 0)
+ /*
+ * Select only the auto_link_speed speed for autoneg mode. This
+ * mode has been DEPRECATED. An HWRM client should not use this
+ * mode.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED \
+ (UINT32_C(0x2) << 0)
+ /*
+ * Select the auto_link_speed or any speed below that speed for
+ * autoneg. This mode has been DEPRECATED. An HWRM client should
+ * not use this mode.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW \
+ (UINT32_C(0x3) << 0)
+ /*
+ * Select the speeds based on the corresponding link speed mask
+ * value that is provided.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK \
+ (UINT32_C(0x4) << 0)
+ uint8_t auto_mode;
+
+ /*
+ * Current setting of pause autonegotiation. Move autoneg_pause flag
+ * here.
+ */
+ /*
+ * When this bit is '1', Generation of tx pause messages has been
+ * requested. Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
+ /*
+ * When this bit is '1', Reception of rx pause messages has been
+ * requested. Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
+ /*
+ * When set to 1, the advertisement of pause is enabled. # When the
+ * auto_mode is not set to none and this flag is set to 1, then the
+ * auto_pause bits on this port are being advertised and autoneg pause
+ * results are being interpreted. # When the auto_mode is not set to
+ * none and this flag is set to 0, the pause is forced as indicated in
+ * force_pause, and also advertised as auto_pause bits, but the autoneg
+ * results are not interpreted since the pause configuration is being
+ * forced. # When the auto_mode is set to none and this flag is set to
+ * 1, auto_pause bits should be ignored and should be set to 0.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
+ UINT32_C(0x4)
+ uint8_t auto_pause;
+
+ /*
+ * Current setting for auto_link_speed. This field is only valid when
+ * auto_mode is set to "one_speed" or "one_or_below".
+ */
+ /* 100Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB \
+ (UINT32_C(0x1) << 0)
+ /* 1Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB \
+ (UINT32_C(0xa) << 0)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB \
+ (UINT32_C(0x14) << 0)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB \
+ (UINT32_C(0x19) << 0)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB \
+ (UINT32_C(0x64) << 0)
+ /* 20Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB \
+ (UINT32_C(0xc8) << 0)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB \
+ (UINT32_C(0xfa) << 0)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB \
+ (UINT32_C(0x190) << 0)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB \
+ (UINT32_C(0x1f4) << 0)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB \
+ (UINT32_C(0x3e8) << 0)
+ /* 10Mb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
+ (UINT32_C(0xffff) << 0)
+ uint16_t auto_link_speed;
+
+ /*
+ * Current setting for auto_link_speed_mask that is used to advertise
+ * speeds during autonegotiation. This field is only valid when
+ * auto_mode is set to "mask". The speeds specified in this field shall
+ * be a subset of supported speeds on this port.
+ */
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
+ UINT32_C(0x10)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
+ UINT32_C(0x2000)
+ uint16_t auto_link_speed_mask;
+
+ /* Current setting for wirespeed. */
+ /* Wirespeed feature is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
+ /* Wirespeed feature is enabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
+ uint8_t wirespeed;
+
+ /* Current setting for loopback. */
+ /* No loopback is selected. Normal operation. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE (UINT32_C(0x0) << 0)
+ /*
+ * The HW will be configured with local loopback such that host
+ * data is sent back to the host without modification.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
+ /*
+ * The HW will be configured with remote loopback such that port
+ * logic will send packets back out the transmitter that are
+ * received.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
+ uint8_t lpbk;
+
+ /*
+ * Current setting of forced pause. When the pause configuration is not
+ * being forced, then this value shall be set to 0.
+ */
+ /*
+ * When this bit is '1', Generation of tx pause messages is supported.
+ * Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', Reception of rx pause messages is supported.
+ * Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX \
+ UINT32_C(0x2)
+ uint8_t force_pause;
+
+ /*
+ * This value indicates the current status of the optics module on this
+ * port.
+ */
+ /* Module is inserted and accepted */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
+ (UINT32_C(0x0) << 0)
+ /* Module is rejected and transmit side Laser is disabled. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
+ (UINT32_C(0x1) << 0)
+ /* Module mismatch warning. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
+ (UINT32_C(0x2) << 0)
+ /* Module is rejected and powered down. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
+ (UINT32_C(0x3) << 0)
+ /* Module is not inserted. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
+ (UINT32_C(0x4) << 0)
+ /* Module status is not applicable. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
+ (UINT32_C(0xff) << 0)
+ uint8_t module_status;
+
+ /* Current setting for preemphasis. */
+ uint32_t preemphasis;
+
+ /* This field represents the major version of the PHY. */
+ uint8_t phy_maj;
+
+ /* This field represents the minor version of the PHY. */
+ uint8_t phy_min;
+
+ /* This field represents the build version of the PHY. */
+ uint8_t phy_bld;
+
+ /* This value represents a PHY type. */
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
+ (UINT32_C(0x0) << 0)
+ /* BASE-CR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
+ (UINT32_C(0x1) << 0)
+ /* BASE-KR4 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
+ (UINT32_C(0x2) << 0)
+ /* BASE-LR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
+ (UINT32_C(0x3) << 0)
+ /* BASE-SR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
+ (UINT32_C(0x4) << 0)
+ /* BASE-KR2 (Deprecated) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
+ (UINT32_C(0x5) << 0)
+ /* BASE-KX */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
+ (UINT32_C(0x6) << 0)
+ /* BASE-KR */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
+ (UINT32_C(0x7) << 0)
+ /* BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
+ (UINT32_C(0x8) << 0)
+ /* EEE capable BASE-T */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
+ (UINT32_C(0x9) << 0)
+ /* SGMII connected external PHY */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
+ (UINT32_C(0xa) << 0)
+ uint8_t phy_type;
+
+ /* This value represents a media type. */
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN \
+ (UINT32_C(0x0) << 0)
+ /* Twisted Pair */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP (UINT32_C(0x1) << 0)
+ /* Direct Attached Copper */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC \
+ (UINT32_C(0x2) << 0)
+ /* Fiber */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE \
+ (UINT32_C(0x3) << 0)
+ uint8_t media_type;
+
+ /* This value represents a transceiver type. */
+ /* PHY and MAC are in the same package */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
+ (UINT32_C(0x1) << 0)
+ /* PHY and MAC are in different packages */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
+ (UINT32_C(0x2) << 0)
+ uint8_t xcvr_pkg_type;
+
+ /*
+ * This field represents flags related to EEE configuration. These EEE
+ * configuration flags are valid only when the auto_mode is not set to
+ * none (in other words autonegotiation is enabled).
+ */
+ /* This field represents PHY address. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
+ /*
+ * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
+ * Speeds for autoneg with EEE mode enabled are based on
+ * eee_link_speed_mask.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
+ UINT32_C(0x20)
+ /*
+ * This flag is valid only when eee_enabled is set to 1. # If
+ * eee_enabled is set to 0, then EEE mode is disabled and this flag
+ * shall be ignored. # If eee_enabled is set to 1 and this flag is set
+ * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and in
+ * use. # If eee_enabled is set to 1 and this flag is set to 0, then
+ * Energy Efficient Ethernet (EEE) mode is enabled but is currently not
+ * in use.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
+ UINT32_C(0x40)
+ /*
+ * This flag is valid only when eee_enabled is set to 1. # If
+ * eee_enabled is set to 0, then EEE mode is disabled and this flag
+ * shall be ignored. # If eee_enabled is set to 1 and this flag is set
+ * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and TX LPI
+ * is enabled. # If eee_enabled is set to 1 and this flag is set to 0,
+ * then Energy Efficient Ethernet (EEE) mode is enabled but TX LPI is
+ * disabled.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
+ UINT32_C(0x80)
+ /*
+ * This field represents flags related to EEE configuration. These EEE
+ * configuration flags are valid only when the auto_mode is not set to
+ * none (in other words autonegotiation is enabled).
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
+ UINT32_C(0xe0)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
+ uint8_t eee_config_phy_addr;
+
+ /* Reserved field, set to 0 */
+ /*
+ * When set to 1, the parallel detection is used to determine the speed
+ * of the link partner. Parallel detection is used when a
+ * autonegotiation capable device is connected to a link parter that is
+ * not capable of autonegotiation.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT \
+ UINT32_C(0x1)
+ /* Reserved field, set to 0 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_MASK UINT32_C(0xfe)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_SFT 1
+ uint8_t parallel_detect;
+
+ /*
+ * The advertised speeds for the port by the link partner. Each
+ * advertised speed will be set to '1'.
+ */
+ /* 100Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
+ UINT32_C(0x2)
+ /* 1Gb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
+ UINT32_C(0x8)
+ /* 2Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
+ UINT32_C(0x10)
+ /* 2.5Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
+ UINT32_C(0x40)
+ /* 20Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
+ UINT32_C(0x80)
+ /* 25Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
+ UINT32_C(0x100)
+ /* 40Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
+ UINT32_C(0x200)
+ /* 50Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
+ UINT32_C(0x400)
+ /* 100Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
+ UINT32_C(0x800)
+ /* 10Mb link speed (Half-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
+ UINT32_C(0x1000)
+ /* 10Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
+ UINT32_C(0x2000)
+ uint16_t link_partner_adv_speeds;
+
+ /*
+ * The advertised autoneg for the port by the link partner. This field
+ * is deprecated and should be set to 0.
+ */
+ /*
+ * Disable autoneg or autoneg disabled. No speeds are selected.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
+ (UINT32_C(0x0) << 0)
+ /* Select all possible speeds for autoneg mode. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS\
+ (UINT32_C(0x1) << 0)
+ /*
+ * Select only the auto_link_speed speed for autoneg mode. This
+ * mode has been DEPRECATED. An HWRM client should not use this
+ * mode.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
+ (UINT32_C(0x2) << 0)
+ /*
+ * Select the auto_link_speed or any speed below that speed for
+ * autoneg. This mode has been DEPRECATED. An HWRM client should
+ * not use this mode.
+ */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
+ (UINT32_C(0x3) << 0)
+ /*
+ * Select the speeds based on the corresponding link speed mask
+ * value that is provided.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK\
+ (UINT32_C(0x4) << 0)
+ uint8_t link_partner_adv_auto_mode;
+
+ /* The advertised pause settings on the port by the link partner. */
+ /*
+ * When this bit is '1', Generation of tx pause messages is supported.
+ * Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', Reception of rx pause messages is supported.
+ * Disabled otherwise.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
+ UINT32_C(0x2)
+ uint8_t link_partner_adv_pause;
+
+ /*
+ * Current setting for link speed mask that is used to advertise speeds
+ * during autonegotiation when EEE is enabled. This field is valid only
+ * when eee_enabled flags is set to 1. The speeds specified in this
+ * field shall be a subset of speeds specified in auto_link_speed_mask.
+ */
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ uint16_t adv_eee_link_speed_mask;
+
+ /*
+ * Current setting for link speed mask that is advertised by the link
+ * partner when EEE is enabled. This field is valid only when
+ * eee_enabled flags is set to 1.
+ */
+ /* Reserved */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
+ UINT32_C(0x1)
+ /* 100Mb link speed (Full-duplex) */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
+ UINT32_C(0x2)
+ /* Reserved */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
+ UINT32_C(0x4)
+ /* 1Gb link speed (Full-duplex) */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
+ UINT32_C(0x8)
+ /* Reserved */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
+ UINT32_C(0x10)
+ /* Reserved */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
+ UINT32_C(0x20)
+ /* 10Gb link speed */
+ #define \
+ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
+ UINT32_C(0x40)
+ uint16_t link_partner_adv_eee_link_speed_mask;
+
+ /* This value represents transceiver identifier type. */
+ /*
+ * Current setting of TX LPI timer in microseconds. This field is valid
+ * only when_eee_enabled flag is set to 1 and tx_lpi_enabled is set to
+ * 1.
+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
+ /* This value represents transceiver identifier type. */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT \
+ 24
+ /* Unknown */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
+ (UINT32_C(0x0) << 24)
+ /* SFP/SFP+/SFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
+ (UINT32_C(0x3) << 24)
+ /* QSFP */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
+ (UINT32_C(0xc) << 24)
+ /* QSFP+ */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
+ (UINT32_C(0xd) << 24)
+ /* QSFP28 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
+ (UINT32_C(0x11) << 24)
+ uint32_t xcvr_identifier_type_tx_lpi_timer;
+
+ uint32_t unused_1;
+
+ /*
+ * Up to 16 bytes of null padded ASCII string representing PHY vendor.
+ * If the string is set to null, then the vendor name is not available.
+ */
+ char phy_vendor_name[16];
+
+ /*
+ * Up to 16 bytes of null padded ASCII string that identifies vendor
+ * specific part number of the PHY. If the string is set to null, then
+ * the vendor specific part number is not available.
+ */
+ char phy_vendor_partnumber[16];
+
+ uint32_t unused_2;
+ uint8_t unused_3;
+ uint8_t unused_4;
+ uint8_t unused_5;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_ver_get */
+/*
+ * Description: This function is called by a driver to determine the HWRM
+ * interface version supported by the HWRM firmware, the version of HWRM
+ * firmware implementation, the name of HWRM firmware, the versions of other
+ * embedded firmwares, and the names of other embedded firmwares, etc. Any
+ * interface or firmware version with major = 0, minor = 0, and update = 0 shall
+ * be considered an invalid version.
+ */
+
+/* Input (24 bytes) */
+struct hwrm_ver_get_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /*
+ * This field represents the major version of HWRM interface
+ * specification supported by the driver HWRM implementation. The
+ * interface major version is intended to change only when non backward
+ * compatible changes are made to the HWRM interface specification.
+ */
+ uint8_t hwrm_intf_maj;
+
+ /*
+ * This field represents the minor version of HWRM interface
+ * specification supported by the driver HWRM implementation. A change
+ * in interface minor version is used to reflect significant backward
+ * compatible modification to HWRM interface specification. This can be
+ * due to addition or removal of functionality. HWRM interface
+ * specifications with the same major version but different minor
+ * versions are compatible.
+ */
+ uint8_t hwrm_intf_min;
+
+ /*
+ * This field represents the update version of HWRM interface
+ * specification supported by the driver HWRM implementation. The
+ * interface update version is used to reflect minor changes or bug
+ * fixes to a released HWRM interface specification.
+ */
+ uint8_t hwrm_intf_upd;
+
+ uint8_t unused_0[5];
+} __attribute__((packed));
+
+/* Output (128 bytes) */
+struct hwrm_ver_get_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ /*
+ * This field represents the major version of HWRM interface
+ * specification supported by the HWRM implementation. The interface
+ * major version is intended to change only when non backward compatible
+ * changes are made to the HWRM interface specification. A HWRM
+ * implementation that is compliant with this specification shall
+ * provide value of 1 in this field.
+ */
+ uint8_t hwrm_intf_maj;
+
+ /*
+ * This field represents the minor version of HWRM interface
+ * specification supported by the HWRM implementation. A change in
+ * interface minor version is used to reflect significant backward
+ * compatible modification to HWRM interface specification. This can be
+ * due to addition or removal of functionality. HWRM interface
+ * specifications with the same major version but different minor
+ * versions are compatible. A HWRM implementation that is compliant with
+ * this specification shall provide value of 0 in this field.
+ */
+ uint8_t hwrm_intf_min;
+
+ /*
+ * This field represents the update version of HWRM interface
+ * specification supported by the HWRM implementation. The interface
+ * update version is used to reflect minor changes or bug fixes to a
+ * released HWRM interface specification. A HWRM implementation that is
+ * compliant with this specification shall provide value of 1 in this
+ * field.
+ */
+ uint8_t hwrm_intf_upd;
+
+ uint8_t hwrm_intf_rsvd;
+
+ /*
+ * This field represents the major version of HWRM firmware. A change in
+ * firmware major version represents a major firmware release.
+ */
+ uint8_t hwrm_fw_maj;
+
+ /*
+ * This field represents the minor version of HWRM firmware. A change in
+ * firmware minor version represents significant firmware functionality
+ * changes.
+ */
+ uint8_t hwrm_fw_min;
+
+ /*
+ * This field represents the build version of HWRM firmware. A change in
+ * firmware build version represents bug fixes to a released firmware.
+ */
+ uint8_t hwrm_fw_bld;
+
+ /*
+ * This field is a reserved field. This field can be used to represent
+ * firmware branches or customer specific releases tied to a specific
+ * (major,minor,update) version of the HWRM firmware.
+ */
+ uint8_t hwrm_fw_rsvd;
+
+ /*
+ * This field represents the major version of mgmt firmware. A change in
+ * major version represents a major release.
+ */
+ uint8_t mgmt_fw_maj;
+
+ /*
+ * This field represents the minor version of mgmt firmware. A change in
+ * minor version represents significant functionality changes.
+ */
+ uint8_t mgmt_fw_min;
+
+ /*
+ * This field represents the build version of mgmt firmware. A change in
+ * update version represents bug fixes.
+ */
+ uint8_t mgmt_fw_bld;
+
+ /*
+ * This field is a reserved field. This field can be used to represent
+ * firmware branches or customer specific releases tied to a specific
+ * (major,minor,update) version
+ */
+ uint8_t mgmt_fw_rsvd;
+
+ /*
+ * This field represents the major version of network control firmware.
+ * A change in major version represents a major release.
+ */
+ uint8_t netctrl_fw_maj;
+
+ /*
+ * This field represents the minor version of network control firmware.
+ * A change in minor version represents significant functionality
+ * changes.
+ */
+ uint8_t netctrl_fw_min;
+
+ /*
+ * This field represents the build version of network control firmware.
+ * A change in update version represents bug fixes.
+ */
+ uint8_t netctrl_fw_bld;
+
+ /*
+ * This field is a reserved field. This field can be used to represent
+ * firmware branches or customer specific releases tied to a specific
+ * (major,minor,update) version
+ */
+ uint8_t netctrl_fw_rsvd;
+
+ /*
+ * This field is reserved for future use. The responder should set it to
+ * 0. The requester should ignore this field.
+ */
+ uint32_t reserved1;
+
+ /*
+ * This field represents the major version of RoCE firmware. A change in
+ * major version represents a major release.
+ */
+ uint8_t roce_fw_maj;
+
+ /*
+ * This field represents the minor version of RoCE firmware. A change in
+ * minor version represents significant functionality changes.
+ */
+ uint8_t roce_fw_min;
+
+ /*
+ * This field represents the build version of RoCE firmware. A change in
+ * update version represents bug fixes.
+ */
+ uint8_t roce_fw_bld;
+
+ /*
+ * This field is a reserved field. This field can be used to represent
+ * firmware branches or customer specific releases tied to a specific
+ * (major,minor,update) version
+ */
+ uint8_t roce_fw_rsvd;
+
+ /*
+ * This field represents the name of HWRM FW (ASCII chars without NULL
+ * at the end).
+ */
+ char hwrm_fw_name[16];
+
+ /*
+ * This field represents the name of mgmt FW (ASCII chars without NULL
+ * at the end).
+ */
+ char mgmt_fw_name[16];
+
+ /*
+ * This field represents the name of network control firmware (ASCII
+ * chars without NULL at the end).
+ */
+ char netctrl_fw_name[16];
+
+ /*
+ * This field is reserved for future use. The responder should set it to
+ * 0. The requester should ignore this field.
+ */
+ uint32_t reserved2[4];
+
+ /*
+ * This field represents the name of RoCE FW (ASCII chars without NULL
+ * at the end).
+ */
+ char roce_fw_name[16];
+
+ /* This field returns the chip number. */
+ uint16_t chip_num;
+
+ /* This field returns the revision of chip. */
+ uint8_t chip_rev;
+
+ /* This field returns the chip metal number. */
+ uint8_t chip_metal;
+
+ /* This field returns the bond id of the chip. */
+ uint8_t chip_bond_id;
+
+ /*
+ * This value indicates the type of platform used for chip
+ * implementation.
+ */
+ /* ASIC */
+ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
+ (UINT32_C(0x0) << 0)
+ /* FPGA platform of the chip. */
+ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
+ (UINT32_C(0x1) << 0)
+ /* Palladium platform of the chip. */
+ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
+ (UINT32_C(0x2) << 0)
+ uint8_t chip_platform_type;
+
+ /*
+ * This field returns the maximum value of request window that is
+ * supported by the HWRM. The request window is mapped into device
+ * address space using MMIO.
+ */
+ uint16_t max_req_win_len;
+
+ /*
+ * This field returns the maximum value of response buffer in bytes. If
+ * a request specifies the response buffer length that is greater than
+ * this value, then the HWRM should fail it. The value of this field
+ * shall be 4KB or more.
+ */
+ uint16_t max_resp_len;
+
+ /*
+ * This field returns the default request timeout value in milliseconds.
+ */
+ uint16_t def_req_timeout;
+
+ uint8_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_queue_qportcfg */
+/*
+ * Description: This function is called by a driver to query queue configuration
+ * of a port. # The HWRM shall at least advertise one queue with lossy service
+ * profile. # The driver shall use this command to query queue ids before
+ * configuring or using any queues. # If a service profile is not set for a
+ * queue, then the driver shall not use that queue without configuring a service
+ * profile for it. # If the driver is not allowed to configure service profiles,
+ * then the driver shall only use queues for which service profiles are pre-
+ * configured.
+ */
+
+/* Input (24 bytes) */
+struct hwrm_queue_qportcfg_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /*
+ * Enumeration denoting the RX, TX type of the resource. This
+ * enumeration is used for resources that are similar for both TX and RX
+ * paths of the chip.
+ */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
+ (UINT32_C(0x0) << 0)
+ /* rx path */
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
+ (UINT32_C(0x1) << 0)
+ #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
+ uint32_t flags;
+
+ /*
+ * Port ID of port for which the queue configuration is being queried.
+ * This field is only required when sent by IPC.
+ */
+ uint16_t port_id;
+
+ uint16_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_ring_alloc */
+/*
+ * Description: This command allocates and does basic preparation for a ring.
+ */
+
+/* Input (80 bytes) */
+struct hwrm_ring_alloc_input {
/*
- * This field represents the minor version of mgmt firmware. A change in
- * minor version represents significant functionality changes.
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
*/
- uint8_t mgmt_fw_min;
+ uint16_t req_type;
/*
- * This field represents the build version of mgmt firmware. A change in
- * update version represents bug fixes.
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
*/
- uint8_t mgmt_fw_bld;
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
/*
- * This field is a reserved field. This field can be used to represent
- * firmware branches or customer specific releases tied to a specific
- * (major,minor,update) version
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
*/
- uint8_t mgmt_fw_rsvd;
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /* This bit must be '1' for the Reserved1 field to be configured. */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)
+ /* This bit must be '1' for the Reserved2 field to be configured. */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2 UINT32_C(0x2)
+ /* This bit must be '1' for the Reserved3 field to be configured. */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the stat_ctx_id_valid field to be
+ * configured.
+ */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
+ /* This bit must be '1' for the Reserved4 field to be configured. */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4 UINT32_C(0x10)
+ /* This bit must be '1' for the max_bw_valid field to be configured. */
+ #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
+ uint32_t enables;
+
+ /* Ring Type. */
+ /* Completion Ring (CR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
+ /* RX Ring (RR) */
+ #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
+ uint8_t ring_type;
+
+ uint8_t unused_0;
+ uint16_t unused_1;
+
+ /* This value is a pointer to the page table for the Ring. */
+ uint64_t page_tbl_addr;
+
+ /* First Byte Offset of the first entry in the first page. */
+ uint32_t fbo;
+
+ /*
+ * Actual page size in 2^page_size. The supported range is increments in
+ * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12
+ * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB
+ * Page size is 64 KB. - 22 = 2 MB Page size is 2 MB. - 23 = 4 MB Page
+ * size is 4 MB. - 31 = 1 GB Page size is 1 GB.
+ */
+ uint8_t page_size;
+
+ /*
+ * This value indicates the depth of page table. For this version of the
+ * specification, value other than 0 or 1 shall be considered as an
+ * invalid value. When the page_tbl_depth = 0, then it is treated as a
+ * special case with the following. 1. FBO and page size fields are not
+ * valid. 2. page_tbl_addr is the physical address of the first element
+ * of the ring.
+ */
+ uint8_t page_tbl_depth;
+
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * Number of 16B units in the ring. Minimum size for a ring is 16 16B
+ * entries.
+ */
+ uint32_t length;
+
+ /*
+ * Logical ring number for the ring to be allocated. This value
+ * determines the position in the doorbell area where the update to the
+ * ring will be made. For completion rings, this value is also the MSI-X
+ * vector number for the function the completion ring is associated
+ * with.
+ */
+ uint16_t logical_id;
+
+ /*
+ * This field is used only when ring_type is a TX ring. This value
+ * indicates what completion ring the TX ring is associated with.
+ */
+ uint16_t cmpl_ring_id;
+
+ /*
+ * This field is used only when ring_type is a TX ring. This value
+ * indicates what CoS queue the TX ring is associated with.
+ */
+ uint16_t queue_id;
+
+ uint8_t unused_4;
+ uint8_t unused_5;
+
+ /* This field is reserved for the future use. It shall be set to 0. */
+ uint32_t reserved1;
+ /* This field is reserved for the future use. It shall be set to 0. */
+ uint16_t reserved2;
+
+ uint8_t unused_6;
+ uint8_t unused_7;
+ /* This field is reserved for the future use. It shall be set to 0. */
+ uint32_t reserved3;
+
+ /*
+ * This field is used only when ring_type is a TX ring. This input
+ * indicates what statistics context this ring should be associated
+ * with.
+ */
+ uint32_t stat_ctx_id;
+
+ /* This field is reserved for the future use. It shall be set to 0. */
+ uint32_t reserved4;
+
+ /*
+ * This field is used only when ring_type is a TX ring. Maximum BW
+ * allocated to this TX ring in Mbps. The HWRM will translate this value
+ * into byte counter and time interval used for this ring inside the
+ * device.
+ */
+ uint32_t max_bw;
+
+ /*
+ * This field is used only when ring_type is a Completion ring. This
+ * value indicates what interrupt mode should be used on this completion
+ * ring. Note: In the legacy interrupt mode, no more than 16 completion
+ * rings are allowed.
+ */
+ /* Legacy INTA */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY (UINT32_C(0x0) << 0)
+ /* Reserved */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD (UINT32_C(0x1) << 0)
+ /* MSI-X */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX (UINT32_C(0x2) << 0)
+ /* No Interrupt - Polled mode */
+ #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL (UINT32_C(0x3) << 0)
+ uint8_t int_mode;
+
+ uint8_t unused_8[3];
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+
+struct hwrm_ring_alloc_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ /* Physical number of ring allocated. */
+ uint16_t ring_id;
+
+ /* Logical number of ring allocated. */
+ uint16_t logical_ring_id;
+
+ uint8_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_ring_free */
+/*
+ * Description: This command is used to free a ring and associated resources.
+ */
+/* Input (24 bytes) */
+
+struct hwrm_ring_free_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /* Ring Type. */
+ /* Completion Ring (CR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
+ /* TX Ring (TR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
+ /* RX Ring (RR) */
+ #define HWRM_RING_FREE_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
+ uint8_t ring_type;
+
+ uint8_t unused_0;
+
+ /* Physical number of ring allocated. */
+ uint16_t ring_id;
+
+ uint32_t unused_1;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_ring_free_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_ring_grp_alloc */
+/*
+ * Description: This API allocates and does basic preparation for a ring group.
+ */
+
+/* Input (24 bytes) */
+struct hwrm_ring_grp_alloc_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /* This value identifies the CR associated with the ring group. */
+ uint16_t cr;
+
+ /* This value identifies the main RR associated with the ring group. */
+ uint16_t rr;
+
+ /*
+ * This value identifies the aggregation RR associated with the ring
+ * group. If this value is 0xFF... (All Fs), then no Aggregation ring
+ * will be set.
+ */
+ uint16_t ar;
+
+ /*
+ * This value identifies the statistics context associated with the ring
+ * group.
+ */
+ uint16_t sc;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_ring_grp_alloc_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
/*
- * This field represents the major version of network control firmware.
- * A change in major version represents a major release.
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
*/
- uint8_t netctrl_fw_maj;
+ uint16_t resp_len;
/*
- * This field represents the minor version of network control firmware.
- * A change in minor version represents significant functionality
- * changes.
+ * This is the ring group ID value. Use this value to program the
+ * default ring group for the VNIC or as table entries in an RSS/COS
+ * context.
*/
- uint8_t netctrl_fw_min;
+ uint32_t ring_group_id;
+
+ uint8_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
/*
- * This field represents the build version of network control firmware.
- * A change in update version represents bug fixes.
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
*/
- uint8_t netctrl_fw_bld;
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_ring_grp_free */
+/*
+ * Description: This API frees a ring group and associated resources. # If a
+ * ring in the ring group is reset or free, then the associated rings in the
+ * ring group shall also be reset/free using hwrm_ring_free. # A function driver
+ * shall always use hwrm_ring_grp_free after freeing all rings in a group. # As
+ * a part of executing this command, the HWRM shall reset all associated ring
+ * group resources.
+ */
+/* Input (24 bytes) */
+struct hwrm_ring_grp_free_input {
/*
- * This field is a reserved field. This field can be used to represent
- * firmware branches or customer specific releases tied to a specific
- * (major,minor,update) version
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
*/
- uint8_t netctrl_fw_rsvd;
+ uint16_t req_type;
/*
- * This field is reserved for future use. The responder should set it to
- * 0. The requester should ignore this field.
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
*/
- uint32_t reserved1;
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
/*
- * This field represents the major version of RoCE firmware. A change in
- * major version represents a major release.
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
*/
- uint8_t roce_fw_maj;
+ uint16_t target_id;
/*
- * This field represents the minor version of RoCE firmware. A change in
- * minor version represents significant functionality changes.
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
*/
- uint8_t roce_fw_min;
+ uint64_t resp_addr;
+
+ /* This is the ring group ID value. */
+ uint32_t ring_group_id;
+
+ uint32_t unused_0;
+} __attribute__((packed));
+/* Output (16 bytes) */
+struct hwrm_ring_grp_free_output {
/*
- * This field represents the build version of RoCE firmware. A change in
- * update version represents bug fixes.
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
*/
- uint8_t roce_fw_bld;
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
/*
- * This field is a reserved field. This field can be used to represent
- * firmware branches or customer specific releases tied to a specific
- * (major,minor,update) version
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
*/
- uint8_t roce_fw_rsvd;
+ uint16_t resp_len;
+
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
/*
- * This field represents the name of HWRM FW (ASCII chars without NULL
- * at the end).
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
*/
- char hwrm_fw_name[16];
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_alloc */
+/*
+ * Description: This command allocates and does basic preparation for a stat
+ * context.
+ */
+/* Input (32 bytes) */
+struct hwrm_stat_ctx_alloc_input {
/*
- * This field represents the name of mgmt FW (ASCII chars without NULL
- * at the end).
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
*/
- char mgmt_fw_name[16];
+ uint16_t req_type;
/*
- * This field represents the name of network control firmware (ASCII
- * chars without NULL at the end).
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
*/
- char netctrl_fw_name[16];
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
/*
- * This field is reserved for future use. The responder should set it to
- * 0. The requester should ignore this field.
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
*/
- uint32_t reserved2[4];
+ uint16_t target_id;
/*
- * This field represents the name of RoCE FW (ASCII chars without NULL
- * at the end).
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
*/
- char roce_fw_name[16];
-
- /* This field returns the chip number. */
- uint16_t chip_num;
-
- /* This field returns the revision of chip. */
- uint8_t chip_rev;
-
- /* This field returns the chip metal number. */
- uint8_t chip_metal;
+ uint64_t resp_addr;
- /* This field returns the bond id of the chip. */
- uint8_t chip_bond_id;
+ /* This is the address for statistic block. */
+ uint64_t stats_dma_addr;
/*
- * This value indicates the type of platform used for chip
- * implementation.
+ * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,
+ * 1000ms.
*/
- /* ASIC */
- #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
- (UINT32_C(0x0) << 0)
- /* FPGA platform of the chip. */
- #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
- (UINT32_C(0x1) << 0)
- /* Palladium platform of the chip. */
- #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
- (UINT32_C(0x2) << 0)
- uint8_t chip_platform_type;
+ uint32_t update_period_ms;
- /*
- * This field returns the maximum value of request window that is
- * supported by the HWRM. The request window is mapped into device
- * address space using MMIO.
- */
- uint16_t max_req_win_len;
+ uint32_t unused_0;
+} __attribute__((packed));
+/* Output (16 bytes) */
+struct hwrm_stat_ctx_alloc_output {
/*
- * This field returns the maximum value of response buffer in bytes. If
- * a request specifies the response buffer length that is greater than
- * this value, then the HWRM should fail it. The value of this field
- * shall be 4KB or more.
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
*/
- uint16_t max_resp_len;
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
/*
- * This field returns the default request timeout value in milliseconds.
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
*/
- uint16_t def_req_timeout;
+ uint16_t resp_len;
+
+ /* This is the statistics context ID value. */
+ uint32_t stat_ctx_id;
uint8_t unused_0;
uint8_t unused_1;
uint8_t valid;
} __attribute__((packed));
-/* hwrm_queue_qportcfg */
-/*
- * Description: This function is called by a driver to query queue configuration
- * of a port. # The HWRM shall at least advertise one queue with lossy service
- * profile. # The driver shall use this command to query queue ids before
- * configuring or using any queues. # If a service profile is not set for a
- * queue, then the driver shall not use that queue without configuring a service
- * profile for it. # If the driver is not allowed to configure service profiles,
- * then the driver shall only use queues for which service profiles are pre-
- * configured.
- */
+/* hwrm_stat_ctx_clr_stats */
+/* Description: This command clears statistics of a context. */
/* Input (24 bytes) */
-struct hwrm_queue_qportcfg_input {
+struct hwrm_stat_ctx_clr_stats_input {
/*
* This value indicates what type of request this is. The format for the
* rest of the command is determined by this field.
*/
uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_stat_ctx_clr_stats_output {
/*
- * Enumeration denoting the RX, TX type of the resource. This
- * enumeration is used for resources that are similar for both TX and RX
- * paths of the chip.
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
*/
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
- UINT32_C(0x1)
- /* tx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
- (UINT32_C(0x0) << 0)
- /* rx path */
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
- (UINT32_C(0x1) << 0)
- #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
- HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
- uint32_t flags;
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
/*
- * Port ID of port for which the queue configuration is being queried.
- * This field is only required when sent by IPC.
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
*/
- uint16_t port_id;
+ uint16_t resp_len;
- uint16_t unused_0;
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
} __attribute__((packed));
-/* hwrm_stat_ctx_clr_stats */
-/* Description: This command clears statistics of a context. */
-
+/* hwrm_stat_ctx_free */
+/* Description: This command is used to free a stat context. */
/* Input (24 bytes) */
-struct hwrm_stat_ctx_clr_stats_input {
+
+struct hwrm_stat_ctx_free_input {
/*
* This value indicates what type of request this is. The format for the
* rest of the command is determined by this field.
} __attribute__((packed));
/* Output (16 bytes) */
-struct hwrm_stat_ctx_clr_stats_output {
+
+struct hwrm_stat_ctx_free_output {
/*
* Pass/Fail or error type Note: receiver to verify the in parameters,
* and fail the call with an error when appropriate
*/
uint16_t resp_len;
- uint32_t unused_0;
+ /* This is the statistics context ID value. */
+ uint32_t stat_ctx_id;
+
+ uint8_t unused_0;
uint8_t unused_1;
uint8_t unused_2;
- uint8_t unused_3;
/*
* This field is used in Output records to indicate that the output is
uint8_t valid;
} __attribute__((packed));
+/* hwrm_vnic_cfg */
+/* Description: Configure the RX VNIC structure. */
+
+/* Input (40 bytes) */
+struct hwrm_vnic_cfg_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /*
+ * When this bit is '1', the VNIC is requested to be the default VNIC
+ * for the function.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
+ /*
+ * When this bit is '1', the VNIC is being configured to strip VLAN in
+ * the RX path. If set to '0', then VLAN stripping is disabled on this
+ * VNIC.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
+ /*
+ * When this bit is '1', the VNIC is being configured to buffer receive
+ * packets in the hardware until the host posts new receive buffers. If
+ * set to '0', then bd_stall is being configured to be disabled on this
+ * VNIC.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
+ /*
+ * When this bit is '1', the VNIC is being configured to receive both
+ * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not
+ * configured to be operating in dual VNIC mode.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
+ /*
+ * When this flag is set to '1', the VNIC is requested to be configured
+ * to receive only RoCE traffic. If this flag is set to '0', then this
+ * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set
+ * to '1', then the HWRM client shall not set this flag to '1'.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
+ uint32_t flags;
+
+ /* This bit must be '1' for the dflt_ring_grp field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
+ /* This bit must be '1' for the rss_rule field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
+ /* This bit must be '1' for the cos_rule field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
+ /* This bit must be '1' for the lb_rule field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
+ /* This bit must be '1' for the mru field to be configured. */
+ #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
+ uint32_t enables;
+
+ /* Logical vnic ID */
+ uint16_t vnic_id;
+
+ /*
+ * Default Completion ring for the VNIC. This ring will be chosen if
+ * packet does not match any RSS rules and if there is no COS rule.
+ */
+ uint16_t dflt_ring_grp;
+
+ /*
+ * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
+ * RSS rule.
+ */
+ uint16_t rss_rule;
+
+ /*
+ * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
+ * COS rule.
+ */
+ uint16_t cos_rule;
+
+ /*
+ * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
+ * there is no LB rule.
+ */
+ uint16_t lb_rule;
+
+ /*
+ * The maximum receive unit of the vnic. Each vnic is associated with a
+ * function. The vnic mru value overwrites the mru setting of the
+ * associated function. The HWRM shall make sure that vnic mru does not
+ * exceed the mru of the port the function is associated with.
+ */
+ uint16_t mru;
+
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_vnic_cfg_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/* hwrm_vnic_free */
/*
* Description: Free a VNIC resource. Idle any resources associated with the
uint8_t valid;
} __attribute__((packed));
+/* Input (16 bytes) */
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+
+struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+
+ uint8_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+ uint8_t unused_4;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/* hwrm_vnic_rss_cos_lb_ctx_free */
+/* Description: This function can be used to free COS/Load Balance context. */
+/* Input (24 bytes) */
+
+struct hwrm_vnic_rss_cos_lb_ctx_free_input {
+ /*
+ * This value indicates what type of request this is. The format for the
+ * rest of the command is determined by this field.
+ */
+ uint16_t req_type;
+
+ /*
+ * This value indicates the what completion ring the request will be
+ * optionally completed on. If the value is -1, then no CR completion
+ * will be generated. Any other value must be a valid CR ring_id value
+ * for this function.
+ */
+ uint16_t cmpl_ring;
+
+ /* This value indicates the command sequence number. */
+ uint16_t seq_id;
+
+ /*
+ * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
+ * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+
+ /*
+ * This is the host address where the response will be written when the
+ * request is complete. This area must be 16B aligned and must be
+ * cleared to zero before the request is made.
+ */
+ uint64_t resp_addr;
+
+ /* rss_cos_lb_ctx_id is 16 b */
+ uint16_t rss_cos_lb_ctx_id;
+
+ uint16_t unused_0[3];
+} __attribute__((packed));
+
+/* Output (16 bytes) */
+struct hwrm_vnic_rss_cos_lb_ctx_free_output {
+ /*
+ * Pass/Fail or error type Note: receiver to verify the in parameters,
+ * and fail the call with an error when appropriate
+ */
+ uint16_t error_code;
+
+ /* This field returns the type of original request. */
+ uint16_t req_type;
+
+ /* This field provides original sequence number of the command. */
+ uint16_t seq_id;
+
+ /*
+ * This field is the length of the response in bytes. The last byte of
+ * the response is a valid flag that will read as '1' when the command
+ * has been completely written to memory.
+ */
+ uint16_t resp_len;
+
+ uint32_t unused_0;
+ uint8_t unused_1;
+ uint8_t unused_2;
+ uint8_t unused_3;
+
+ /*
+ * This field is used in Output records to indicate that the output is
+ * completely written to RAM. This field should be read as '1' to
+ * indicate that the output has been completely written. When writing a
+ * command completion or response to an internal processor, the order of
+ * writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/* Output (32 bytes) */
struct hwrm_queue_qportcfg_output {
/*
git.droids-corp.org / dpdk.git / blobdiff