BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
- BNXT_ULP_CF_IDX_VFR_FLAG = 28,
- BNXT_ULP_CF_IDX_LAST = 29
+ BNXT_ULP_CF_IDX_LAST = 28
};
enum bnxt_ulp_critical_resource {
BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
};
+enum bnxt_ulp_vfr_flag {
+ BNXT_ULP_VFR_FLAG_NO = 0,
+ BNXT_ULP_VFR_FLAG_YES = 1,
+ BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
enum bnxt_ulp_fdb_resource_flags {
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00