net/bnxt: add locks in flow database

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 8acf76e..24b71b3 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -12,14 +12,14 @@
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
-#define BNXT_ULP_CLASS_HID_SHFTR 0
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
+#define BNXT_ULP_CLASS_HID_SHFTR 16
 #define BNXT_ULP_CLASS_HID_SHFTL 23
 #define BNXT_ULP_CLASS_HID_MASK 255
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
 #define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
 #define BNXT_ULP_ACT_HID_SHFTR 0
@@ -117,8 +117,7 @@ enum bnxt_ulp_cf_idx {
        BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
        BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
        BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
-       BNXT_ULP_CF_IDX_VFR_FLAG = 28,
-       BNXT_ULP_CF_IDX_LAST = 29
+       BNXT_ULP_CF_IDX_LAST = 28
 };
 
 enum bnxt_ulp_critical_resource {
@@ -233,6 +232,12 @@ enum bnxt_ulp_spec_opc {
        BNXT_ULP_SPEC_OPC_LAST = 6
 };
 
+enum bnxt_ulp_vfr_flag {
+       BNXT_ULP_VFR_FLAG_NO = 0,
+       BNXT_ULP_VFR_FLAG_YES = 1,
+       BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
 enum bnxt_ulp_encap_vtag_encoding {
        BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4,
        BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5,
@@ -252,6 +257,12 @@ enum bnxt_ulp_encap_vtag_encoding {
        BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
 };
 
+enum bnxt_ulp_vfr_flag {
+       BNXT_ULP_VFR_FLAG_NO = 0,
+       BNXT_ULP_VFR_FLAG_YES = 1,
+       BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
 enum bnxt_ulp_fdb_resource_flags {
        BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
        BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
@@ -296,6 +307,9 @@ enum bnxt_ulp_resource_sub_type {
 };
 
 enum bnxt_ulp_sym {
+       BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+       BNXT_ULP_SYM_AGG_ERROR_YES = 1,
        BNXT_ULP_SYM_BIG_ENDIAN = 0,
        BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
        BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
@@ -327,42 +341,160 @@ enum bnxt_ulp_sym {
        BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
        BNXT_ULP_SYM_ECV_VALID_NO = 0,
        BNXT_ULP_SYM_ECV_VALID_YES = 1,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+       BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+       BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+       BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+       BNXT_ULP_SYM_HREC_NEXT_YES = 1,
+       BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+       BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+       BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+       BNXT_ULP_SYM_IP_PROTO_TCP = 6,
        BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+       BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
        BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+       BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
        BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+       BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+       BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+       BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+       BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+       BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+       BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+       BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+       BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+       BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+       BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+       BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+       BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+       BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+       BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+       BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
        BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
        BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
        BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+       BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
        BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
        BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
        BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
        BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
        BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+       BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+       BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+       BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+       BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+       BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+       BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+       BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+       BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+       BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+       BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+       BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
        BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
        BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+       BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
        BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
        BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
        BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+       BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
        BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
        BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
        BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
        BNXT_ULP_SYM_NO = 0,
+       BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
        BNXT_ULP_SYM_POP_VLAN_NO = 0,
        BNXT_ULP_SYM_POP_VLAN_YES = 1,
+       BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+       BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
+       BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+       BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
+       BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+       BNXT_ULP_SYM_RESERVED_IGNORE = 0,
        BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
        BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
        BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
        BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+       BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+       BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
+       BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+       BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+       BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+       BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+       BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+       BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+       BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+       BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+       BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
+       BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+       BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
+       BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+       BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+       BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
+       BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
        BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+       BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+       BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+       BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
+       BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+       BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+       BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+       BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
        BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+       BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+       BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+       BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
+       BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
+       BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
        BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
        BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
        BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
        BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
@@ -372,6 +504,9 @@ enum bnxt_ulp_sym {
        BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
        BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
        BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+       BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+       BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+       BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
        BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
        BNXT_ULP_SYM_YES = 1
 };
@@ -465,10 +600,14 @@ enum bnxt_ulp_act_prop_idx {
 };
 
 enum bnxt_ulp_class_hid {
-       BNXT_ULP_CLASS_HID_0013 = 0x0013
+       BNXT_ULP_CLASS_HID_0080 = 0x0080,
+       BNXT_ULP_CLASS_HID_0000 = 0x0000,
+       BNXT_ULP_CLASS_HID_0087 = 0x0087
 };
 
 enum bnxt_ulp_act_hid {
+       BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+       BNXT_ULP_ACT_HID_0040 = 0x0040,
        BNXT_ULP_ACT_HID_0029 = 0x0029
 };