net/bnxt: match flow API items with flow template patterns

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 957b21a..319500a 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -13,6 +13,8 @@
 
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2
+#define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1
 
 enum bnxt_ulp_action_bit {
        BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
@@ -45,6 +47,31 @@ enum bnxt_ulp_action_bit {
        BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
 };
 
+enum bnxt_ulp_hdr_bit {
+       BNXT_ULP_HDR_BIT_SVIF                = 0x0000000000000001,
+       BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000002,
+       BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000004,
+       BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000008,
+       BNXT_ULP_HDR_BIT_O_L3                = 0x0000000000000010,
+       BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000020,
+       BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000040,
+       BNXT_ULP_HDR_BIT_O_L4                = 0x0000000000000080,
+       BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000100,
+       BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000200,
+       BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000400,
+       BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000800,
+       BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000001000,
+       BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000002000,
+       BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000004000,
+       BNXT_ULP_HDR_BIT_I_L3                = 0x0000000000008000,
+       BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000010000,
+       BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000020000,
+       BNXT_ULP_HDR_BIT_I_L4                = 0x0000000000040000,
+       BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000080000,
+       BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000100000,
+       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000200000
+};
+
 enum bnxt_ulp_byte_order {
        BNXT_ULP_BYTE_ORDER_BE,
        BNXT_ULP_BYTE_ORDER_LE,
@@ -67,12 +94,25 @@ enum bnxt_ulp_fmf_mask {
        BNXT_ULP_FMF_MASK_LAST
 };
 
+enum bnxt_ulp_fmf_spec {
+       BNXT_ULP_FMF_SPEC_IGNORE = 0,
+       BNXT_ULP_FMF_SPEC_LAST = 1
+};
+
 enum bnxt_ulp_mark_enable {
        BNXT_ULP_MARK_ENABLE_NO = 0,
        BNXT_ULP_MARK_ENABLE_YES = 1,
        BNXT_ULP_MARK_ENABLE_LAST = 2
 };
 
+enum bnxt_ulp_hdr_field {
+       BNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,
+       BNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,
+       BNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,
+       BNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,
+       BNXT_ULP_HDR_FIELD_LAST = 4
+};
+
 enum bnxt_ulp_mask_opc {
        BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
        BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,