net/bnxt: add computed header field in result opcode

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 94d4253..6591d78 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -3,17 +3,14 @@
  * All rights reserved.
  */
 
-/*
- * date: Mon Mar  9 02:37:53 2020
- * version: 0.0
- */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
 
-#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_REGFILE_MAX_SZ 16
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
@@ -28,6 +25,8 @@
 #define BNXT_ULP_ACT_HID_SHFTR 0
 #define BNXT_ULP_ACT_HID_SHFTL 23
 #define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
+#define BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ 1
 
 enum bnxt_ulp_action_bit {
        BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
@@ -61,24 +60,19 @@ enum bnxt_ulp_action_bit {
 };
 
 enum bnxt_ulp_hdr_bit {
-       BNXT_ULP_HDR_BIT_SVIF                = 0x0000000000000001,
-       BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000002,
-       BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000004,
-       BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000008,
-       BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000010,
-       BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000020,
-       BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000040,
-       BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000080,
-       BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000100,
-       BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000200,
-       BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000400,
-       BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000000800,
-       BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000001000,
-       BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000002000,
-       BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000004000,
-       BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000008000,
-       BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000010000,
-       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
+       BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000001,
+       BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000002,
+       BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000004,
+       BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000008,
+       BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000010,
+       BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000020,
+       BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000040,
+       BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000000080,
+       BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000000100,
+       BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000000200,
+       BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000000400,
+       BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000000800,
+       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000001000
 };
 
 enum bnxt_ulp_act_type {
@@ -94,6 +88,14 @@ enum bnxt_ulp_byte_order {
        BNXT_ULP_BYTE_ORDER_LAST = 2
 };
 
+enum bnxt_ulp_cache_tbl_id {
+       BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_INGRESS = 0,
+       BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_EGRESS = 1,
+       BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_INGRESS = 2,
+       BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_EGRESS = 3,
+       BNXT_ULP_CACHE_TBL_ID_LAST = 4
+};
+
 enum bnxt_ulp_chf_idx {
        BNXT_ULP_CHF_IDX_MPLS_TAG_NUM = 0,
        BNXT_ULP_CHF_IDX_O_VTAG_NUM = 1,
@@ -112,6 +114,11 @@ enum bnxt_ulp_chf_idx {
        BNXT_ULP_CHF_IDX_LAST = 14
 };
 
+enum bnxt_ulp_def_regfile_index {
+       BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID = 0,
+       BNXT_ULP_DEF_REGFILE_INDEX_LAST = 1
+};
+
 enum bnxt_ulp_device_id {
        BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
        BNXT_ULP_DEVICE_ID_THOR = 1,
@@ -120,6 +127,12 @@ enum bnxt_ulp_device_id {
        BNXT_ULP_DEVICE_ID_LAST = 4
 };
 
+enum bnxt_ulp_direction {
+       BNXT_ULP_DIRECTION_INGRESS = 0,
+       BNXT_ULP_DIRECTION_EGRESS = 1,
+       BNXT_ULP_DIRECTION_LAST = 2
+};
+
 enum bnxt_ulp_hdr_type {
        BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
        BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
@@ -137,8 +150,9 @@ enum bnxt_ulp_mask_opc {
        BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
        BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
        BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
-       BNXT_ULP_MASK_OPC_ADD_PAD = 3,
-       BNXT_ULP_MASK_OPC_LAST = 4
+       BNXT_ULP_MASK_OPC_SET_TO_DEF_REGFILE = 3,
+       BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+       BNXT_ULP_MASK_OPC_LAST = 5
 };
 
 enum bnxt_ulp_match_type {
@@ -175,17 +189,22 @@ enum bnxt_ulp_regfile_index {
        BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
        BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
        BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
-       BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
-       BNXT_ULP_REGFILE_INDEX_LAST = 15
+       BNXT_ULP_REGFILE_INDEX_CACHE_ENTRY_PTR = 14,
+       BNXT_ULP_REGFILE_INDEX_NOT_USED = 15,
+       BNXT_ULP_REGFILE_INDEX_LAST = 16
 };
 
 enum bnxt_ulp_resource_func {
-       BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0,
-       BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 1,
-       BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 2,
-       BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 3,
-       BNXT_ULP_RESOURCE_FUNC_HW_FID = 4,
-       BNXT_ULP_RESOURCE_FUNC_LAST = 5
+       BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+       BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+       BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+       BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+       BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+       BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+       BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+       BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+       BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+       BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
 };
 
 enum bnxt_ulp_result_opc {
@@ -193,7 +212,9 @@ enum bnxt_ulp_result_opc {
        BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
        BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
        BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
-       BNXT_ULP_RESULT_OPC_LAST = 4
+       BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
+       BNXT_ULP_RESULT_OPC_SET_TO_COMP_HDR_FIELD = 5,
+       BNXT_ULP_RESULT_OPC_LAST = 6
 };
 
 enum bnxt_ulp_search_before_alloc {
@@ -205,9 +226,11 @@ enum bnxt_ulp_search_before_alloc {
 enum bnxt_ulp_spec_opc {
        BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
        BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
-       BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
-       BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
-       BNXT_ULP_SPEC_OPC_LAST = 4
+       BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD = 2,
+       BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
+       BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 4,
+       BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
+       BNXT_ULP_SPEC_OPC_LAST = 6
 };
 
 enum bnxt_ulp_encap_vtag_encoding {
@@ -417,12 +440,13 @@ enum bnxt_ulp_act_prop_idx {
        BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
        BNXT_ULP_ACT_PROP_IDX_LAST = 268
 };
+
 enum bnxt_ulp_class_hid {
-       BNXT_ULP_CLASS_HID_0092 = 0x0092
+       BNXT_ULP_CLASS_HID_0013 = 0x0013
 };
 
 enum bnxt_ulp_act_hid {
        BNXT_ULP_ACT_HID_0029 = 0x0029
 };
 
-#endif /* _ULP_TEMPLATE_DB_H_ */
+#endif