net/ixgbe: check driver type in MACsec API

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 94d4253..e6065d2 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -11,9 +11,10 @@
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
 
-#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_REGFILE_MAX_SZ 16
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
@@ -28,6 +29,8 @@
 #define BNXT_ULP_ACT_HID_SHFTR 0
 #define BNXT_ULP_ACT_HID_SHFTL 23
 #define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
+#define BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ 1
 
 enum bnxt_ulp_action_bit {
        BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
@@ -94,6 +97,14 @@ enum bnxt_ulp_byte_order {
        BNXT_ULP_BYTE_ORDER_LAST = 2
 };
 
+enum bnxt_ulp_cache_tbl_id {
+       BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_INGRESS = 0,
+       BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_EGRESS = 1,
+       BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_INGRESS = 2,
+       BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_EGRESS = 3,
+       BNXT_ULP_CACHE_TBL_ID_LAST = 4
+};
+
 enum bnxt_ulp_chf_idx {
        BNXT_ULP_CHF_IDX_MPLS_TAG_NUM = 0,
        BNXT_ULP_CHF_IDX_O_VTAG_NUM = 1,
@@ -112,6 +123,11 @@ enum bnxt_ulp_chf_idx {
        BNXT_ULP_CHF_IDX_LAST = 14
 };
 
+enum bnxt_ulp_def_regfile_index {
+       BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID = 0,
+       BNXT_ULP_DEF_REGFILE_INDEX_LAST = 1
+};
+
 enum bnxt_ulp_device_id {
        BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
        BNXT_ULP_DEVICE_ID_THOR = 1,
@@ -120,6 +136,12 @@ enum bnxt_ulp_device_id {
        BNXT_ULP_DEVICE_ID_LAST = 4
 };
 
+enum bnxt_ulp_direction {
+       BNXT_ULP_DIRECTION_INGRESS = 0,
+       BNXT_ULP_DIRECTION_EGRESS = 1,
+       BNXT_ULP_DIRECTION_LAST = 2
+};
+
 enum bnxt_ulp_hdr_type {
        BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
        BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
@@ -137,8 +159,9 @@ enum bnxt_ulp_mask_opc {
        BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
        BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
        BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
-       BNXT_ULP_MASK_OPC_ADD_PAD = 3,
-       BNXT_ULP_MASK_OPC_LAST = 4
+       BNXT_ULP_MASK_OPC_SET_TO_DEF_REGFILE = 3,
+       BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+       BNXT_ULP_MASK_OPC_LAST = 5
 };
 
 enum bnxt_ulp_match_type {
@@ -175,17 +198,20 @@ enum bnxt_ulp_regfile_index {
        BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
        BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
        BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
-       BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
-       BNXT_ULP_REGFILE_INDEX_LAST = 15
+       BNXT_ULP_REGFILE_INDEX_CACHE_ENTRY_PTR = 14,
+       BNXT_ULP_REGFILE_INDEX_NOT_USED = 15,
+       BNXT_ULP_REGFILE_INDEX_LAST = 16
 };
 
 enum bnxt_ulp_resource_func {
-       BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0,
-       BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 1,
-       BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 2,
-       BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 3,
-       BNXT_ULP_RESOURCE_FUNC_HW_FID = 4,
-       BNXT_ULP_RESOURCE_FUNC_LAST = 5
+       BNXT_ULP_RESOURCE_FUNC_INVALID = 0,
+       BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 1,
+       BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 2,
+       BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 3,
+       BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 4,
+       BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 5,
+       BNXT_ULP_RESOURCE_FUNC_HW_FID = 6,
+       BNXT_ULP_RESOURCE_FUNC_LAST = 7
 };
 
 enum bnxt_ulp_result_opc {
@@ -193,7 +219,8 @@ enum bnxt_ulp_result_opc {
        BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
        BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
        BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
-       BNXT_ULP_RESULT_OPC_LAST = 4
+       BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
+       BNXT_ULP_RESULT_OPC_LAST = 5
 };
 
 enum bnxt_ulp_search_before_alloc {
@@ -206,8 +233,9 @@ enum bnxt_ulp_spec_opc {
        BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
        BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
        BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
-       BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
-       BNXT_ULP_SPEC_OPC_LAST = 4
+       BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 3,
+       BNXT_ULP_SPEC_OPC_ADD_PAD = 4,
+       BNXT_ULP_SPEC_OPC_LAST = 5
 };
 
 enum bnxt_ulp_encap_vtag_encoding {