net/bnxt: fix VLAN/VXLAN encapsulation header size

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db_enum.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 81da34e..6802deb 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -11,7 +11,7 @@
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
 #define BNXT_ULP_CLASS_HID_SHFTR 32
@@ -52,7 +52,8 @@ enum bnxt_ulp_action_bit {
        BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000100000,
        BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000000200000,
        BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000000400000,
-       BNXT_ULP_ACTION_BIT_LAST             = 0x0000000000800000
+       BNXT_ULP_ACTION_BIT_JUMP             = 0x0000000000800000,
+       BNXT_ULP_ACTION_BIT_LAST             = 0x0000000001000000
 };
 
 enum bnxt_ulp_hdr_bit {
@@ -72,7 +73,8 @@ enum bnxt_ulp_hdr_bit {
        BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000002000,
        BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000004000,
        BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000008000,
-       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000010000
+       BNXT_ULP_HDR_BIT_F1                  = 0x0000000000010000,
+       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
 };
 
 enum bnxt_ulp_act_type {
@@ -133,7 +135,9 @@ enum bnxt_ulp_cf_idx {
        BNXT_ULP_CF_IDX_L4_HDR_CNT = 41,
        BNXT_ULP_CF_IDX_VFR_MODE = 42,
        BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43,
-       BNXT_ULP_CF_IDX_LAST = 44
+       BNXT_ULP_CF_IDX_L3_TUN = 44,
+       BNXT_ULP_CF_IDX_L3_TUN_DECAP = 45,
+       BNXT_ULP_CF_IDX_LAST = 46
 };
 
 enum bnxt_ulp_cond_opcode {
@@ -321,7 +325,10 @@ enum bnxt_ulp_resource_func {
        BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
        BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
        BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
-       BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
+       BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
+       BNXT_ULP_RESOURCE_FUNC_SHARED_TABLE = 0x86,
+       BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x87,
+       BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x88
 };
 
 enum bnxt_ulp_resource_sub_type {
@@ -329,7 +336,8 @@ enum bnxt_ulp_resource_sub_type {
        BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
        BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
        BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
-       BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
+       BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3,
+       BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4,
        BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
        BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
 };
@@ -337,6 +345,10 @@ enum bnxt_ulp_resource_sub_type {
 enum bnxt_ulp_sym {
        BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
        BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+       BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0,
+       BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0,
+       BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0,
+       BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0,
        BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
        BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
        BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
@@ -547,7 +559,8 @@ enum bnxt_ulp_sym {
        BNXT_ULP_SYM_IP_PROTO_UDP = 17,
        BNXT_ULP_SYM_VF_FUNC_PARIF = 15,
        BNXT_ULP_SYM_NO = 0,
-       BNXT_ULP_SYM_YES = 1
+       BNXT_ULP_SYM_YES = 1,
+       BNXT_ULP_SYM_RECYCLE_DST = 0x800
 };
 
 enum bnxt_ulp_wh_plus {
@@ -596,6 +609,7 @@ enum bnxt_ulp_act_prop_sz {
        BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
        BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
        BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+       BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
        BNXT_ULP_ACT_PROP_SZ_LAST = 4
 };
 
@@ -640,7 +654,8 @@ enum bnxt_ulp_act_prop_idx {
        BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
        BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
        BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
-       BNXT_ULP_ACT_PROP_IDX_LAST = 257
+       BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
+       BNXT_ULP_ACT_PROP_IDX_LAST = 261
 };
 
 enum bnxt_ulp_class_hid {
@@ -792,6 +807,22 @@ enum bnxt_ulp_class_hid {
        BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
        BNXT_ULP_CLASS_HID_0371 = 0x0371,
        BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
+       BNXT_ULP_CLASS_HID_0000 = 0x0000,
+       BNXT_ULP_CLASS_HID_00ce = 0x00ce,
+       BNXT_ULP_CLASS_HID_01b6 = 0x01b6,
+       BNXT_ULP_CLASS_HID_0074 = 0x0074,
+       BNXT_ULP_CLASS_HID_00fe = 0x00fe,
+       BNXT_ULP_CLASS_HID_03bc = 0x03bc,
+       BNXT_ULP_CLASS_HID_0206 = 0x0206,
+       BNXT_ULP_CLASS_HID_02c4 = 0x02c4,
+       BNXT_ULP_CLASS_HID_055a = 0x055a,
+       BNXT_ULP_CLASS_HID_045a = 0x045a,
+       BNXT_ULP_CLASS_HID_061a = 0x061a,
+       BNXT_ULP_CLASS_HID_051a = 0x051a,
+       BNXT_ULP_CLASS_HID_074a = 0x074a,
+       BNXT_ULP_CLASS_HID_004e = 0x004e,
+       BNXT_ULP_CLASS_HID_040a = 0x040a,
+       BNXT_ULP_CLASS_HID_010e = 0x010e,
        BNXT_ULP_CLASS_HID_048b = 0x048b,
        BNXT_ULP_CLASS_HID_0749 = 0x0749,
        BNXT_ULP_CLASS_HID_05f1 = 0x05f1,