net/bnxt: add context list for timers
[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db_enum.h
index ca019bb..8cbbe20 100644 (file)
@@ -3,12 +3,12 @@
  * All rights reserved.
  */
 
-/* date: Fri Jan 29 09:44:41 2021 */
+/* date: Sun Mar 21 13:04:51 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
 
-#define BNXT_ULP_REGFILE_MAX_SZ 38
+#define BNXT_ULP_REGFILE_MAX_SZ 40
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_GEN_TBL_MAX_SZ 10
 #define BNXT_ULP_ACT_HID_SHFTR 27
 #define BNXT_ULP_ACT_HID_SHFTL 26
 #define BNXT_ULP_ACT_HID_MASK 2047
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 11
-#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 10
+#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 4
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 33
+#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 26
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 205
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 6
 #define BNXT_ULP_COND_GOTO_REJECT 1023
 #define BNXT_ULP_COND_GOTO_RF 0x10000
 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4
+#define BNXT_ULP_APP_ID_SHIFT 4
 #define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595
 #define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5
 #define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 484
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495
 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 550
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 41
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43
 #define ULP_THOR_CLASS_TMPL_LIST_SIZE 5
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 26
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 90
-#define ULP_THOR_CLASS_IDENT_LIST_SIZE 3
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 138
-#define ULP_THOR_CLASS_COND_LIST_SIZE 6
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 13
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 0
+#define ULP_THOR_CLASS_IDENT_LIST_SIZE 0
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 102
+#define ULP_THOR_CLASS_COND_LIST_SIZE 1
 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
@@ -109,7 +113,8 @@ enum bnxt_ulp_hdr_bit {
        BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000010000,
        BNXT_ULP_HDR_BIT_I_ICMP              = 0x0000000000020000,
        BNXT_ULP_HDR_BIT_F1                  = 0x0000000000040000,
-       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000080000
+       BNXT_ULP_HDR_BIT_ANY                 = 0x0000000000080000,
+       BNXT_ULP_HDR_BIT_LAST                = 0x0000000000100000
 };
 
 enum bnxt_ulp_accept_opc {
@@ -146,7 +151,8 @@ enum bnxt_ulp_cc_upd_src {
        BNXT_ULP_CC_UPD_SRC_REGFILE = 0,
        BNXT_ULP_CC_UPD_SRC_GLB_REGFILE = 1,
        BNXT_ULP_CC_UPD_SRC_COMP_FIELD = 2,
-       BNXT_ULP_CC_UPD_SRC_LAST = 3
+       BNXT_ULP_CC_UPD_SRC_CONST = 3,
+       BNXT_ULP_CC_UPD_SRC_LAST = 4
 };
 
 enum bnxt_ulp_cf_idx {
@@ -212,7 +218,8 @@ enum bnxt_ulp_cf_idx {
        BNXT_ULP_CF_IDX_HDR_SIG_ID = 59,
        BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60,
        BNXT_ULP_CF_IDX_WC_MATCH = 61,
-       BNXT_ULP_CF_IDX_LAST = 62
+       BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62,
+       BNXT_ULP_CF_IDX_LAST = 63
 };
 
 enum bnxt_ulp_cond_list_opc {
@@ -281,26 +288,19 @@ enum bnxt_ulp_fdb_type {
        BNXT_ULP_FDB_TYPE_LAST = 3
 };
 
-enum bnxt_ulp_field_cond_src {
-       BNXT_ULP_FIELD_COND_SRC_TRUE = 0,
-       BNXT_ULP_FIELD_COND_SRC_CF = 1,
-       BNXT_ULP_FIELD_COND_SRC_RF = 2,
-       BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,
-       BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,
-       BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,
-       BNXT_ULP_FIELD_COND_SRC_FLOW_PAT_MATCH = 6,
-       BNXT_ULP_FIELD_COND_SRC_ACT_PAT_MATCH = 7,
-       BNXT_ULP_FIELD_COND_SRC_LAST = 8
-};
-
 enum bnxt_ulp_field_opc {
-       BNXT_ULP_FIELD_OPC_COND_OP = 0,
-       BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST = 1,
-       BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST = 2,
-       BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST = 3,
-       BNXT_ULP_FIELD_OPC_SRC1_MINUS_CONST_POST = 4,
-       BNXT_ULP_FIELD_OPC_PORT_TABLE = 5,
-       BNXT_ULP_FIELD_OPC_LAST = 6
+       BNXT_ULP_FIELD_OPC_SRC1 = 0,
+       BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3 = 1,
+       BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2 = 2,
+       BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2 = 3,
+       BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST = 4,
+       BNXT_ULP_FIELD_OPC_SRC1_MINUS_SRC2_POST = 5,
+       BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2 = 6,
+       BNXT_ULP_FIELD_OPC_SRC1_OR_SRC2_OR_SRC3 = 7,
+       BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2 = 8,
+       BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3 = 9,
+       BNXT_ULP_FIELD_OPC_SKIP = 10,
+       BNXT_ULP_FIELD_OPC_LAST = 11
 };
 
 enum bnxt_ulp_field_src {
@@ -319,7 +319,8 @@ enum bnxt_ulp_field_src {
        BNXT_ULP_FIELD_SRC_FIELD_BIT = 12,
        BNXT_ULP_FIELD_SRC_SKIP = 13,
        BNXT_ULP_FIELD_SRC_REJECT = 14,
-       BNXT_ULP_FIELD_SRC_LAST = 15
+       BNXT_ULP_FIELD_SRC_PORT_TABLE = 15,
+       BNXT_ULP_FIELD_SRC_LAST = 16
 };
 
 enum bnxt_ulp_generic_tbl_lkup_type {
@@ -344,11 +345,16 @@ enum bnxt_ulp_glb_rf_idx {
        BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
        BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 6,
        BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 7,
-       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 8,
-       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 9,
-       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 10,
-       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 11,
-       BNXT_ULP_GLB_RF_IDX_LAST = 12
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 8,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 9,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 10,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 11,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 12,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 13,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 14,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 15,
+       BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 16,
+       BNXT_ULP_GLB_RF_IDX_LAST = 17
 };
 
 enum bnxt_ulp_hdr_type {
@@ -458,7 +464,15 @@ enum bnxt_ulp_rf_idx {
        BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC = 35,
        BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 36,
        BNXT_ULP_RF_IDX_CC = 37,
-       BNXT_ULP_RF_IDX_LAST = 38
+       BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 38,
+       BNXT_ULP_RF_IDX_PHY_PORT_VPORT = 39,
+       BNXT_ULP_RF_IDX_LAST = 40
+};
+
+enum bnxt_ulp_shared_session {
+       BNXT_ULP_SHARED_SESSION_NO = 0,
+       BNXT_ULP_SHARED_SESSION_YES = 1,
+       BNXT_ULP_SHARED_SESSION_LAST = 2
 };
 
 enum bnxt_ulp_tcam_tbl_opc {
@@ -476,6 +490,11 @@ enum bnxt_ulp_template_type {
        BNXT_ULP_TEMPLATE_TYPE_LAST = 2
 };
 
+enum bnxt_ulp_app_cap {
+       BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001,
+       BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002
+};
+
 enum bnxt_ulp_fdb_resource_flags {
        BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00,
        BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01
@@ -559,6 +578,7 @@ enum bnxt_ulp_act_prop_sz {
        BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
        BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
        BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8,
+       BNXT_ULP_ACT_PROP_SZ_RSS = 64,
        BNXT_ULP_ACT_PROP_SZ_LAST = 4
 };
 
@@ -605,7 +625,8 @@ enum bnxt_ulp_act_prop_idx {
        BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
        BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
        BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261,
-       BNXT_ULP_ACT_PROP_IDX_LAST = 269
+       BNXT_ULP_ACT_PROP_IDX_RSS = 269,
+       BNXT_ULP_ACT_PROP_IDX_LAST = 333
 };
 
 enum ulp_wp_sym {