/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2020 Broadcom
+ * Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
#define BNXT_ULP_REGFILE_MAX_SZ 19
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
+#define BNXT_ULP_GEN_TBL_MAX_SZ 4
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217
#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
#define BNXT_ULP_CLASS_HID_SHFTR 32
#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8
#define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
+#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000100000,
BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000000200000,
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000000400000,
- BNXT_ULP_ACTION_BIT_LAST = 0x0000000000800000
+ BNXT_ULP_ACTION_BIT_JUMP = 0x0000000000800000,
+ BNXT_ULP_ACTION_BIT_SHARED = 0x0000000001000000,
+ BNXT_ULP_ACTION_BIT_SAMPLE = 0x0000000002000000,
+ BNXT_ULP_ACTION_BIT_SHARED_SAMPLE = 0x0000000004000000,
+ BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
};
enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000002000,
BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000004000,
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000008000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000010000
+ BNXT_ULP_HDR_BIT_F1 = 0x0000000000010000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000020000
};
enum bnxt_ulp_act_type {
BNXT_ULP_CF_IDX_L4_HDR_CNT = 41,
BNXT_ULP_CF_IDX_VFR_MODE = 42,
BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43,
- BNXT_ULP_CF_IDX_LAST = 44
+ BNXT_ULP_CF_IDX_L3_TUN = 44,
+ BNXT_ULP_CF_IDX_L3_TUN_DECAP = 45,
+ BNXT_ULP_CF_IDX_LAST = 46
};
-enum bnxt_ulp_cond_opcode {
- BNXT_ULP_COND_OPCODE_NOP = 0,
- BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET = 1,
- BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET = 2,
- BNXT_ULP_COND_OPCODE_HDR_BIT_IS_SET = 3,
- BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET = 4,
- BNXT_ULP_COND_OPCODE_ACTION_BIT_NOT_SET = 5,
- BNXT_ULP_COND_OPCODE_HDR_BIT_NOT_SET = 6,
- BNXT_ULP_COND_OPCODE_LAST = 7
+enum bnxt_ulp_cond_list_opc {
+ BNXT_ULP_COND_LIST_OPC_TRUE = 0,
+ BNXT_ULP_COND_LIST_OPC_FALSE = 1,
+ BNXT_ULP_COND_LIST_OPC_OR = 2,
+ BNXT_ULP_COND_LIST_OPC_AND = 3,
+ BNXT_ULP_COND_LIST_OPC_LAST = 4
+};
+
+enum bnxt_ulp_cond_opc {
+ BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET = 0,
+ BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET = 1,
+ BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET = 2,
+ BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET = 3,
+ BNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4,
+ BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5,
+ BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6,
+ BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,
+ BNXT_ULP_COND_OPC_REGFILE_IS_SET = 8,
+ BNXT_ULP_COND_OPC_REGFILE_NOT_SET = 9,
+ BNXT_ULP_COND_OPC_LAST = 10
};
enum bnxt_ulp_critical_resource {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_fdb_opc {
+ BNXT_ULP_FDB_OPC_PUSH = 0,
+ BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1,
+ BNXT_ULP_FDB_OPC_PUSH_REGFILE = 2,
+ BNXT_ULP_FDB_OPC_NOP = 3,
+ BNXT_ULP_FDB_OPC_LAST = 4
+};
+
enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
BNXT_ULP_FLOW_MEM_TYPE_EXT = 1,
BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
};
+enum bnxt_ulp_generic_tbl_opc {
+ BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_GENERIC_TBL_OPC_READ = 1,
+ BNXT_ULP_GENERIC_TBL_OPC_WRITE = 2,
+ BNXT_ULP_GENERIC_TBL_OPC_LAST = 3
+};
+
enum bnxt_ulp_glb_regfile_index {
BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1,
enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_NOT_USED = 0,
- BNXT_ULP_REGFILE_INDEX_CLASS_TID = 1,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 2,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 3,
- BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 4,
- BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 5,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 6,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 7,
- BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 8,
- BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 9,
- BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 10,
- BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 11,
- BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 12,
- BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 13,
- BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 14,
- BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 15,
- BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 16,
- BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 17,
- BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 18,
- BNXT_ULP_REGFILE_INDEX_LAST = 19
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
+ BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
+ BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
+ BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 14,
+ BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 15,
+ BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 = 16,
+ BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 = 17,
+ BNXT_ULP_REGFILE_INDEX_ACTION_REC_SIZE = 18,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_0 = 19,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_TCAM_INDEX_1 = 20,
+ BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_0 = 21,
+ BNXT_ULP_REGFILE_INDEX_PROFILE_TCAM_INDEX_1 = 22,
+ BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_0 = 23,
+ BNXT_ULP_REGFILE_INDEX_WC_TCAM_INDEX_1 = 24,
+ BNXT_ULP_REGFILE_INDEX_SRC_PROPERTY_PTR = 25,
+ BNXT_ULP_REGFILE_INDEX_GENERIC_TBL_HIT = 26,
+ BNXT_ULP_REGFILE_INDEX_MIRROR_PTR_0 = 27,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID = 28,
+ BNXT_ULP_REGFILE_INDEX_FID = 29,
+ BNXT_ULP_REGFILE_INDEX_LAST = 30
+};
+
+enum bnxt_ulp_tcam_tbl_opc {
+ BNXT_ULP_TCAM_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE = 1,
+ BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2,
+ BNXT_ULP_TCAM_TBL_OPC_LAST = 3
};
enum bnxt_ulp_search_before_alloc {
BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
- BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE = 0x82,
BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4,
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
};
enum bnxt_ulp_sym {
BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+ BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0,
+ BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0,
+ BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0,
+ BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0,
BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
BNXT_ULP_SYM_IP_PROTO_UDP = 17,
BNXT_ULP_SYM_VF_FUNC_PARIF = 15,
BNXT_ULP_SYM_NO = 0,
- BNXT_ULP_SYM_YES = 1
+ BNXT_ULP_SYM_YES = 1,
+ BNXT_ULP_SYM_RECYCLE_DST = 0x800
};
enum bnxt_ulp_wh_plus {
BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+ BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
BNXT_ULP_ACT_PROP_SZ_LAST = 4
};
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
- BNXT_ULP_ACT_PROP_IDX_LAST = 257
+ BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 261
};
enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
BNXT_ULP_CLASS_HID_0371 = 0x0371,
BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000,
+ BNXT_ULP_CLASS_HID_00ce = 0x00ce,
+ BNXT_ULP_CLASS_HID_01b6 = 0x01b6,
+ BNXT_ULP_CLASS_HID_0074 = 0x0074,
+ BNXT_ULP_CLASS_HID_00fe = 0x00fe,
+ BNXT_ULP_CLASS_HID_03bc = 0x03bc,
+ BNXT_ULP_CLASS_HID_0206 = 0x0206,
+ BNXT_ULP_CLASS_HID_02c4 = 0x02c4,
+ BNXT_ULP_CLASS_HID_055a = 0x055a,
+ BNXT_ULP_CLASS_HID_045a = 0x045a,
+ BNXT_ULP_CLASS_HID_061a = 0x061a,
+ BNXT_ULP_CLASS_HID_051a = 0x051a,
+ BNXT_ULP_CLASS_HID_074a = 0x074a,
+ BNXT_ULP_CLASS_HID_004e = 0x004e,
+ BNXT_ULP_CLASS_HID_040a = 0x040a,
+ BNXT_ULP_CLASS_HID_010e = 0x010e,
BNXT_ULP_CLASS_HID_048b = 0x048b,
BNXT_ULP_CLASS_HID_0749 = 0x0749,
BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
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