if (roc_nix_is_vf_or_sdp(&dev->nix) ||
dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
- capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
+ capa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;
return capa;
}
uint32_t speed_capa;
/* Auto negotiation disabled */
- speed_capa = ETH_LINK_SPEED_FIXED;
+ speed_capa = RTE_ETH_LINK_SPEED_FIXED;
if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
- speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
- ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
- ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
+ speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
+ RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
+ RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
}
return speed_capa;
struct roc_nix *nix = &dev->nix;
int i, rc = 0;
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
/* Setup Inline Inbound */
rc = roc_nix_inl_inb_init(nix);
if (rc) {
cnxk_nix_inb_mode_set(dev, true);
}
- if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
- dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+ dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
struct plt_bitmap *bmap;
size_t bmap_sz;
void *mem;
dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix);
- /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */
- if (!(dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY))
+ /* Skip the rest if RTE_ETH_TX_OFFLOAD_SECURITY is not enabled */
+ if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY))
goto done;
rc = -ENOMEM;
done:
return 0;
cleanup:
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
rc |= roc_nix_inl_inb_fini(nix);
return rc;
}
+static int
+nix_meter_fini(struct cnxk_eth_dev *dev)
+{
+ struct cnxk_meter_node *next_mtr = NULL;
+ struct roc_nix_bpf_objs profs = {0};
+ struct cnxk_meter_node *mtr = NULL;
+ struct cnxk_mtr *fms = &dev->mtr;
+ struct roc_nix *nix = &dev->nix;
+ struct roc_nix_rq *rq;
+ uint32_t i;
+ int rc;
+
+ RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
+ for (i = 0; i < mtr->rq_num; i++) {
+ rq = &dev->rqs[mtr->rq_id[i]];
+ rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false);
+ }
+
+ profs.level = mtr->level;
+ profs.count = 1;
+ profs.ids[0] = mtr->bpf_id;
+ rc = roc_nix_bpf_free(nix, &profs, 1);
+
+ if (rc)
+ return rc;
+
+ TAILQ_REMOVE(fms, mtr, next);
+ plt_free(mtr);
+ }
+ return 0;
+}
+
static int
nix_security_release(struct cnxk_eth_dev *dev)
{
int rc, ret = 0;
/* Cleanup Inline inbound */
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
/* Destroy inbound sessions */
tvar = NULL;
RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar)
}
/* Cleanup Inline outbound */
- if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY ||
- dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+ dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
/* Destroy outbound sessions */
tvar = NULL;
RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar)
mbp_priv = rte_mempool_get_priv(rxq->qconf.mp);
buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
- if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {
- dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
- dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
+ if (eth_dev->data->mtu + (uint32_t)CNXK_NIX_L2_OVERHEAD > buffsz) {
+ dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
+ dev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
}
}
{
struct rte_eth_dev_data *data = eth_dev->data;
struct cnxk_eth_rxq_sp *rxq;
- uint16_t mtu;
int rc;
rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[0]) - 1;
/* Setup scatter mode if needed by jumbo */
nix_enable_mseg_on_jumbo(rxq);
- /* Setup MTU based on max_rx_pkt_len */
- mtu = data->dev_conf.rxmode.max_rx_pkt_len - CNXK_NIX_L2_OVERHEAD +
- CNXK_NIX_MAX_VTAG_ACT_SIZE;
-
- rc = cnxk_nix_mtu_set(eth_dev, mtu);
+ rc = cnxk_nix_mtu_set(eth_dev, data->mtu);
if (rc)
plt_err("Failed to set default MTU size, rc=%d", rc);
struct rte_eth_fc_conf fc_conf = {0};
int rc;
- /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW
+ /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
* by AF driver, update those info in PMD structure.
*/
rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
goto exit;
fc->mode = fc_conf.mode;
- fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) ||
- (fc_conf.mode == RTE_FC_RX_PAUSE);
- fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) ||
- (fc_conf.mode == RTE_FC_TX_PAUSE);
+ fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
+ (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
+ fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
+ (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
exit:
return rc;
/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
if (roc_model_is_cn96_ax() &&
dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
- (fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
+ (fc_cfg.mode == RTE_ETH_FC_FULL || fc_cfg.mode == RTE_ETH_FC_RX_PAUSE)) {
fc_cfg.mode =
- (fc_cfg.mode == RTE_FC_FULL ||
- fc_cfg.mode == RTE_FC_TX_PAUSE) ?
- RTE_FC_TX_PAUSE : RTE_FC_NONE;
+ (fc_cfg.mode == RTE_ETH_FC_FULL ||
+ fc_cfg.mode == RTE_ETH_FC_TX_PAUSE) ?
+ RTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;
}
return cnxk_nix_flow_ctrl_set(eth_dev, &fc_cfg);
* Maximum three segments can be supported with W8, Choose
* NIX_MAXSQESZ_W16 for multi segment offload.
*/
- if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
return NIX_MAXSQESZ_W16;
else
return NIX_MAXSQESZ_W8;
/* Free memory prior to re-allocation if needed. */
if (eth_dev->data->tx_queues[qid] != NULL) {
plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
- dev_ops->tx_queue_release(eth_dev->data->tx_queues[qid]);
+ dev_ops->tx_queue_release(eth_dev, qid);
eth_dev->data->tx_queues[qid] = NULL;
}
/* When Tx Security offload is enabled, increase tx desc count by
* max possible outbound desc count.
*/
- if (dev->tx_offloads & DEV_TX_OFFLOAD_SECURITY)
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
nb_desc += dev->outb.nb_desc;
/* Setup ROC SQ */
txq_sp->dev = dev;
txq_sp->qid = qid;
txq_sp->qconf.conf.tx = *tx_conf;
+ /* Queue config should reflect global offloads */
+ txq_sp->qconf.conf.tx.offloads = dev->tx_offloads;
txq_sp->qconf.nb_desc = nb_desc;
plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p"
}
static void
-cnxk_nix_tx_queue_release(void *txq)
+cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
{
+ void *txq = eth_dev->data->tx_queues[qid];
struct cnxk_eth_txq_sp *txq_sp;
struct cnxk_eth_dev *dev;
struct roc_nix_sq *sq;
- uint16_t qid;
int rc;
if (!txq)
return;
txq_sp = cnxk_eth_txq_to_sp(txq);
+
dev = txq_sp->dev;
- qid = txq_sp->qid;
plt_nix_dbg("Releasing txq %u", qid);
const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
plt_nix_dbg("Freeing memory prior to re-allocation %d", qid);
- dev_ops->rx_queue_release(eth_dev->data->rx_queues[qid]);
+ dev_ops->rx_queue_release(eth_dev, qid);
eth_dev->data->rx_queues[qid] = NULL;
}
* to avoid meta packet drop as LBK does not currently support
* backpressure.
*/
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {
uint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();
/* Use current RQ's aura limit if inl rq is not available */
rxq_sp->dev = dev;
rxq_sp->qid = qid;
rxq_sp->qconf.conf.rx = *rx_conf;
+ /* Queue config should reflect global offloads */
+ rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
rxq_sp->qconf.nb_desc = nb_desc;
rxq_sp->qconf.mp = mp;
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
/* Setup rq reference for inline dev if present */
rc = roc_nix_inl_dev_rq_get(rq);
if (rc)
* These are needed in deriving raw clock value from tsc counter.
* read_clock eth op returns raw clock value.
*/
- if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
+ if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) {
rc = cnxk_nix_tsc_convert(dev);
if (rc) {
plt_err("Failed to calculate delta and freq mult");
}
static void
-cnxk_nix_rx_queue_release(void *rxq)
+cnxk_nix_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
{
+ void *rxq = eth_dev->data->rx_queues[qid];
struct cnxk_eth_rxq_sp *rxq_sp;
struct cnxk_eth_dev *dev;
struct roc_nix_rq *rq;
struct roc_nix_cq *cq;
- uint16_t qid;
int rc;
if (!rxq)
rxq_sp = cnxk_eth_rxq_to_sp(rxq);
dev = rxq_sp->dev;
- qid = rxq_sp->qid;
rq = &dev->rqs[qid];
plt_nix_dbg("Releasing rxq %u", qid);
/* Release rq reference for inline dev if present */
- if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
roc_nix_inl_dev_rq_put(rq);
/* Cleanup ROC RQ */
dev->ethdev_rss_hf = ethdev_rss;
- if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
+ if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&
dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
}
- if (ethdev_rss & ETH_RSS_C_VLAN)
+ if (ethdev_rss & RTE_ETH_RSS_C_VLAN)
flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
- if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
+ if (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)
flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
- if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
+ if (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)
flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
- if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
+ if (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)
flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
- if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
+ if (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)
flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
if (ethdev_rss & RSS_IPV4_ENABLE)
if (ethdev_rss & RSS_IPV6_ENABLE)
flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
- if (ethdev_rss & ETH_RSS_TCP)
+ if (ethdev_rss & RTE_ETH_RSS_TCP)
flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
- if (ethdev_rss & ETH_RSS_UDP)
+ if (ethdev_rss & RTE_ETH_RSS_UDP)
flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
- if (ethdev_rss & ETH_RSS_SCTP)
+ if (ethdev_rss & RTE_ETH_RSS_SCTP)
flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
- if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
+ if (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)
flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
if (ethdev_rss & RSS_IPV6_EX_ENABLE)
flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
- if (ethdev_rss & ETH_RSS_PORT)
+ if (ethdev_rss & RTE_ETH_RSS_PORT)
flowkey_cfg |= FLOW_KEY_TYPE_PORT;
- if (ethdev_rss & ETH_RSS_NVGRE)
+ if (ethdev_rss & RTE_ETH_RSS_NVGRE)
flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
- if (ethdev_rss & ETH_RSS_VXLAN)
+ if (ethdev_rss & RTE_ETH_RSS_VXLAN)
flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
- if (ethdev_rss & ETH_RSS_GENEVE)
+ if (ethdev_rss & RTE_ETH_RSS_GENEVE)
flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
- if (ethdev_rss & ETH_RSS_GTPU)
+ if (ethdev_rss & RTE_ETH_RSS_GTPU)
flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
return flowkey_cfg;
dev->sqs = NULL;
}
+static int
+nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
+{
+ TAILQ_INIT(&dev->mtr_profiles);
+ TAILQ_INIT(&dev->mtr_policy);
+ TAILQ_INIT(&dev->mtr);
+
+ return 0;
+}
+
static int
nix_rss_default_setup(struct cnxk_eth_dev *dev)
{
uint64_t rss_hf;
rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
- rss_hash_level = ETH_RSS_LEVEL(rss_hf);
+ rss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);
if (rss_hash_level)
rss_hash_level -= 1;
txq_sp = cnxk_eth_txq_to_sp(txq[i]);
memcpy(&tx_qconf[i], &txq_sp->qconf, sizeof(*tx_qconf));
tx_qconf[i].valid = true;
- dev_ops->tx_queue_release(txq[i]);
+ dev_ops->tx_queue_release(eth_dev, i);
eth_dev->data->tx_queues[i] = NULL;
}
rxq_sp = cnxk_eth_rxq_to_sp(rxq[i]);
memcpy(&rx_qconf[i], &rxq_sp->qconf, sizeof(*rx_qconf));
rx_qconf[i].valid = true;
- dev_ops->rx_queue_release(rxq[i]);
+ dev_ops->rx_queue_release(eth_dev, i);
eth_dev->data->rx_queues[i] = NULL;
}
struct cnxk_eth_qconf *tx_qconf = dev->tx_qconf;
struct cnxk_eth_qconf *rx_qconf = dev->rx_qconf;
int rc, i, nb_rxq, nb_txq;
- void **txq, **rxq;
nb_rxq = RTE_MIN(dev->nb_rxq, eth_dev->data->nb_rx_queues);
nb_txq = RTE_MIN(dev->nb_txq, eth_dev->data->nb_tx_queues);
&tx_qconf[i].conf.tx);
if (rc) {
plt_err("Failed to setup tx queue rc=%d", rc);
- txq = eth_dev->data->tx_queues;
for (i -= 1; i >= 0; i--)
- dev_ops->tx_queue_release(txq[i]);
+ dev_ops->tx_queue_release(eth_dev, i);
goto fail;
}
}
rx_qconf[i].mp);
if (rc) {
plt_err("Failed to setup rx queue rc=%d", rc);
- rxq = eth_dev->data->rx_queues;
for (i -= 1; i >= 0; i--)
- dev_ops->rx_queue_release(rxq[i]);
+ dev_ops->rx_queue_release(eth_dev, i);
goto tx_queue_release;
}
}
return 0;
tx_queue_release:
- txq = eth_dev->data->tx_queues;
for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
- dev_ops->tx_queue_release(txq[i]);
+ dev_ops->tx_queue_release(eth_dev, i);
fail:
if (tx_qconf)
free(tx_qconf);
/* Nothing much to do if offload is not enabled */
if (!(dev->tx_offloads &
- (DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
- DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)))
+ (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
+ RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO)))
return 0;
/* Setup LSO formats in AF. Its a no-op if other ethdev has
goto fail_configure;
}
- if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
- rxmode->mq_mode != ETH_MQ_RX_RSS) {
+ if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&
+ rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {
plt_err("Unsupported mq rx mode %d", rxmode->mq_mode);
goto fail_configure;
}
- if (txmode->mq_mode != ETH_MQ_TX_NONE) {
+ if (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {
plt_err("Unsupported mq tx mode %d", txmode->mq_mode);
goto fail_configure;
}
if (rc)
goto fail_configure;
+ /* Disable and free rte_meter entries */
+ rc = nix_meter_fini(dev);
+ if (rc)
+ goto fail_configure;
+
/* Cleanup security support */
rc = nix_security_release(dev);
if (rc)
/* Prepare rx cfg */
rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD;
if (dev->rx_offloads &
- (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) {
+ (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {
rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_OL4;
rx_cfg |= ROC_NIX_LF_RX_CFG_CSUM_IL4;
}
ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 |
ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3);
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+ rx_cfg |= ROC_NIX_LF_RX_CFG_IP6_UDP_OPT;
+ /* Disable drop re if rx offload security is enabled and
+ * platform does not support it.
+ */
+ if (dev->ipsecd_drop_re_dis)
+ rx_cfg &= ~(ROC_NIX_LF_RX_CFG_DROP_RE);
+ }
+
nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
nb_txq = RTE_MAX(data->nb_tx_queues, 1);
goto free_nix_lf;
}
+ rc = nix_ingress_policer_setup(dev);
+ if (rc) {
+ plt_err("Failed to setup ingress policer rc=%d", rc);
+ goto free_nix_lf;
+ }
+
rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false);
if (rc) {
plt_err("Failed to enable default tm hierarchy, rc=%d", rc);
* enabled on PF owning this VF
*/
memset(&dev->tstamp, 0, sizeof(struct cnxk_timesync_info));
- if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
+ if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en)
cnxk_eth_dev_ops.timesync_enable(eth_dev);
else
cnxk_eth_dev_ops.timesync_disable(eth_dev);
- if (dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
rc = rte_mbuf_dyn_rx_timestamp_register
(&dev->tstamp.tstamp_dynfield_offset,
&dev->tstamp.rx_tstamp_dynflag);
.set_mc_addr_list = cnxk_nix_mc_addr_list_configure,
.set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit,
.tm_ops_get = cnxk_nix_tm_ops_get,
+ .mtr_ops_get = cnxk_nix_mtr_ops_get,
};
static int
roc_nix_npc_rx_ena_dis(nix, false);
+ /* Disable and free rte_meter entries */
+ nix_meter_fini(dev);
+
/* Disable and free rte_flow entries */
roc_npc_fini(&dev->npc);
/* Free up SQs */
for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
- dev_ops->tx_queue_release(eth_dev->data->tx_queues[i]);
+ dev_ops->tx_queue_release(eth_dev, i);
eth_dev->data->tx_queues[i] = NULL;
}
eth_dev->data->nb_tx_queues = 0;
/* Free up RQ's and CQ's */
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
- dev_ops->rx_queue_release(eth_dev->data->rx_queues[i]);
+ dev_ops->rx_queue_release(eth_dev, i);
eth_dev->data->rx_queues[i] = NULL;
}
eth_dev->data->nb_rx_queues = 0;
git.droids-corp.org / dpdk.git / blobdiff