common/mlx5: fix default devargs initialization

[dpdk.git] / drivers / net / cnxk / cnxk_ethdev.c

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 0558bc3..deb95ae 100644 (file)
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -3,6 +3,8 @@
  */
 #include <cnxk_ethdev.h>
 
+#include <rte_eventdev.h>
+
 static inline uint64_t
 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
@@ -304,24 +306,22 @@ static int
 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 {
        struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+       enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL;
        struct cnxk_fc_cfg *fc = &dev->fc_cfg;
-       struct rte_eth_fc_conf fc_conf = {0};
        int rc;
 
-       /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
-        * by AF driver, update those info in PMD structure.
-        */
-       rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
-       if (rc)
-               goto exit;
+       /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+       if (roc_model_is_cn96_ax() &&
+           dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG)
+               fc_mode = ROC_NIX_FC_TX;
 
-       fc->mode = fc_conf.mode;
-       fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-                       (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
-       fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-                       (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
+       /* By default enable flow control */
+       rc = roc_nix_fc_mode_set(&dev->nix, fc_mode);
+       if (rc)
+               return rc;
 
-exit:
+       fc->mode = (fc_mode == ROC_NIX_FC_FULL) ? RTE_ETH_FC_FULL :
+                                                 RTE_ETH_FC_TX_PAUSE;
        return rc;
 }
 
@@ -543,6 +543,11 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
                nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
        }
 
+       /* Its a no-op when inline device is not used */
+       if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
+           dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
+               roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+
        /* Setup ROC CQ */
        cq = &dev->cqs[qid];
        cq->qid = qid;
@@ -567,6 +572,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
        rq->first_skip = first_skip;
        rq->later_skip = sizeof(struct rte_mbuf);
        rq->lpb_size = mp->elt_size;
+       rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
 
        /* Enable Inline IPSec on RQ, will not be used for Poll mode */
        if (roc_nix_inl_inb_is_enabled(nix))
@@ -597,6 +603,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
        rxq_sp->qconf.mp = mp;
 
        if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+               /* Pass a tagmask used to handle error packets in inline device.
+                * Ethdev rq's tag_mask field will be overwritten later
+                * when sso is setup.
+                */
+               rq->tag_mask =
+                       0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28);
+
                /* Setup rq reference for inline dev if present */
                rc = roc_nix_inl_dev_rq_get(rq);
                if (rc)
@@ -1409,6 +1422,8 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev)
        /* Disable Rx via NPC */
        roc_nix_npc_rx_ena_dis(&dev->nix, false);
 
+       roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, false);
+
        /* Stop rx queues and free up pkts pending */
        for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
                rc = dev_ops->rx_queue_stop(eth_dev, i);
@@ -1513,6 +1528,8 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev)
 
        cnxk_nix_toggle_flag_link_cfg(dev, false);
 
+       roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, true);
+
        return 0;
 
 rx_disable: