*/
#include <cnxk_ethdev.h>
+#include <rte_eventdev.h>
+
static inline uint64_t
nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
{
struct roc_nix *nix = &dev->nix;
struct roc_nix_rq *rq;
uint32_t i;
- int rc;
+ int rc = 0;
RTE_TAILQ_FOREACH_SAFE(mtr, fms, next, next_mtr) {
for (i = 0; i < mtr->rq_num; i++) {
nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL;
struct cnxk_fc_cfg *fc = &dev->fc_cfg;
- struct rte_eth_fc_conf fc_conf = {0};
int rc;
- /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
- * by AF driver, update those info in PMD structure.
- */
- rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
- if (rc)
- goto exit;
+ /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+ if (roc_model_is_cn96_ax() &&
+ dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG)
+ fc_mode = ROC_NIX_FC_TX;
- fc->mode = fc_conf.mode;
- fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
- (fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
- fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
- (fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
+ /* By default enable flow control */
+ rc = roc_nix_fc_mode_set(&dev->nix, fc_mode);
+ if (rc)
+ return rc;
-exit:
+ fc->mode = (fc_mode == ROC_NIX_FC_FULL) ? RTE_ETH_FC_FULL :
+ RTE_ETH_FC_TX_PAUSE;
return rc;
}
struct cnxk_fc_cfg *fc = &dev->fc_cfg;
struct rte_eth_fc_conf fc_cfg = {0};
- if (roc_nix_is_vf_or_sdp(&dev->nix))
+ if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix))
return 0;
fc_cfg.mode = fc->mode;
nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
}
+ /* Its a no-op when inline device is not used */
+ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
+ dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
+ roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+
/* Setup ROC CQ */
cq = &dev->cqs[qid];
cq->qid = qid;
rq->first_skip = first_skip;
rq->later_skip = sizeof(struct rte_mbuf);
rq->lpb_size = mp->elt_size;
+ rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
/* Enable Inline IPSec on RQ, will not be used for Poll mode */
if (roc_nix_inl_inb_is_enabled(nix))
rxq_sp->qconf.mp = mp;
if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+ /* Pass a tagmask used to handle error packets in inline device.
+ * Ethdev rq's tag_mask field will be overwritten later
+ * when sso is setup.
+ */
+ rq->tag_mask =
+ 0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28);
+
/* Setup rq reference for inline dev if present */
rc = roc_nix_inl_dev_rq_get(rq);
if (rc)
static int
nix_ingress_policer_setup(struct cnxk_eth_dev *dev)
{
+ struct rte_eth_dev *eth_dev = dev->eth_dev;
+ int rc = 0;
+
TAILQ_INIT(&dev->mtr_profiles);
TAILQ_INIT(&dev->mtr_policy);
TAILQ_INIT(&dev->mtr);
- return 0;
+ if (eth_dev->dev_ops->mtr_ops_get == NULL)
+ return rc;
+
+ return nix_mtr_capabilities_init(eth_dev);
}
static int
for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
dev_ops->tx_queue_release(eth_dev, i);
fail:
- if (tx_qconf)
- free(tx_qconf);
- if (rx_qconf)
- free(rx_qconf);
+ free(tx_qconf);
+ free(rx_qconf);
return rc;
}
-static uint16_t
-nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
-{
- RTE_SET_USED(queue);
- RTE_SET_USED(mbufs);
- RTE_SET_USED(pkts);
-
- return 0;
-}
-
static void
nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
{
* which caused app crash since rx/tx burst is still
* on different lcores
*/
- eth_dev->tx_pkt_burst = nix_eth_nop_burst;
- eth_dev->rx_pkt_burst = nix_eth_nop_burst;
+ eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
+ eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
rte_mb();
}
goto free_nix_lf;
}
- rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
+ rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
+ dev->npc.pre_l2_size_offset,
+ dev->npc.pre_l2_size_offset_mask,
+ dev->npc.pre_l2_size_shift_dir);
if (rc) {
plt_err("Failed to enable switch type nix_lf rc=%d", rc);
goto free_nix_lf;
goto cq_fini;
}
+ /* Setup Inline security support */
+ rc = nix_security_setup(dev);
+ if (rc)
+ goto cq_fini;
+
/* Init flow control configuration */
fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG;
fc_cfg.rxchan_cfg.enable = true;
goto cq_fini;
}
- /* Setup Inline security support */
- rc = nix_security_setup(dev);
- if (rc)
- goto cq_fini;
-
+ /* Initialize TC to SQ mapping as invalid */
+ memset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map));
/*
* Restore queue config when reconfigure followed by
* reconfigure and no queue configure invoked from application case.
int count, i, j, rc;
void *rxq;
- /* Disable switch hdr pkind */
- roc_nix_switch_hdr_set(&dev->nix, 0);
+ /* Disable all the NPC entries */
+ rc = roc_npc_mcam_enable_all_entries(&dev->npc, 0);
+ if (rc)
+ return rc;
/* Stop link change events */
if (!roc_nix_is_vf_or_sdp(&dev->nix))
/* Disable Rx via NPC */
roc_nix_npc_rx_ena_dis(&dev->nix, false);
+ roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, false);
+
/* Stop rx queues and free up pkts pending */
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
rc = dev_ops->rx_queue_stop(eth_dev, i);
return rc;
}
+ rc = roc_npc_mcam_enable_all_entries(&dev->npc, 1);
+ if (rc) {
+ plt_err("Failed to enable NPC entries %d", rc);
+ return rc;
+ }
+
cnxk_nix_toggle_flag_link_cfg(dev, true);
/* Start link change events */
cnxk_nix_toggle_flag_link_cfg(dev, false);
+ roc_nix_inl_outb_soft_exp_poll_switch(&dev->nix, true);
+
return 0;
rx_disable:
.tx_burst_mode_get = cnxk_nix_tx_burst_mode_get,
.flow_ctrl_get = cnxk_nix_flow_ctrl_get,
.flow_ctrl_set = cnxk_nix_flow_ctrl_set,
+ .priority_flow_ctrl_queue_config =
+ cnxk_nix_priority_flow_ctrl_queue_config,
+ .priority_flow_ctrl_queue_info_get =
+ cnxk_nix_priority_flow_ctrl_queue_info_get,
.dev_set_link_up = cnxk_nix_set_link_up,
.dev_set_link_down = cnxk_nix_set_link_down,
.get_module_info = cnxk_nix_get_module_info,
int rc, max_entries;
eth_dev->dev_ops = &cnxk_eth_dev_ops;
+ eth_dev->rx_queue_count = cnxk_nix_rx_queue_count;
+ eth_dev->rx_descriptor_status = cnxk_nix_rx_descriptor_status;
+ eth_dev->tx_descriptor_status = cnxk_nix_tx_descriptor_status;
/* Alloc security context */
sec_ctx = plt_zmalloc(sizeof(struct rte_security_ctx), 0);
sec_ctx->flags =
(RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);
eth_dev->security_ctx = sec_ctx;
- TAILQ_INIT(&dev->inb.list);
- TAILQ_INIT(&dev->outb.list);
/* For secondary processes, the primary has done all the work */
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
dev->configured = 0;
dev->ptype_disable = 0;
+ TAILQ_INIT(&dev->inb.list);
+ TAILQ_INIT(&dev->outb.list);
+ rte_spinlock_init(&dev->inb.lock);
+ rte_spinlock_init(&dev->outb.lock);
+
/* For vfs, returned max_entries will be 0. but to keep default mac
* address, one entry must be allocated. so setting up to 1.
*/
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
const struct eth_dev_ops *dev_ops = eth_dev->dev_ops;
+ struct rte_eth_pfc_queue_conf pfc_conf;
struct roc_nix *nix = &dev->nix;
+ struct rte_eth_fc_conf fc_conf;
int rc, i;
+ /* Disable switch hdr pkind */
+ roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
+
plt_free(eth_dev->security_ctx);
eth_dev->security_ctx = NULL;
roc_nix_npc_rx_ena_dis(nix, false);
+ /* Restore 802.3 Flow control configuration */
+ memset(&pfc_conf, 0, sizeof(struct rte_eth_pfc_queue_conf));
+ memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
+ fc_conf.mode = RTE_ETH_FC_NONE;
+ rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
+
+ pfc_conf.mode = RTE_ETH_FC_NONE;
+ for (i = 0; i < CNXK_NIX_PFC_CHAN_COUNT; i++) {
+ if (dev->pfc_tc_sq_map[i] != 0xFFFF) {
+ pfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i];
+ pfc_conf.rx_pause.tc = i;
+ pfc_conf.tx_pause.rx_qid = i;
+ pfc_conf.tx_pause.tc = i;
+ rc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,
+ &pfc_conf);
+ if (rc)
+ plt_err("Failed to reset PFC. error code(%d)",
+ rc);
+ }
+ }
+
+ fc_conf.mode = RTE_ETH_FC_FULL;
+ rc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);
+
/* Disable and free rte_meter entries */
nix_meter_fini(dev);
git.droids-corp.org / dpdk.git / blobdiff