#include <rte_mbuf.h>
#include <rte_mbuf_pool_ops.h>
#include <rte_mempool.h>
+#include <rte_mtr_driver.h>
#include <rte_security.h>
#include <rte_security_driver.h>
#include <rte_tailq.h>
#include <rte_time.h>
+#include <rte_tm_driver.h>
#include "roc_api.h"
CNXK_NIX_TX_NB_SEG_MAX)
#define CNXK_NIX_RSS_L3_L4_SRC_DST \
- (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
- ETH_RSS_L4_DST_ONLY)
+ (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
+ RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
#define CNXK_NIX_RSS_OFFLOAD \
- (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
- ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
- CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
+ (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | \
+ RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL | \
+ RTE_ETH_RSS_L2_PAYLOAD | CNXK_NIX_RSS_L3_L4_SRC_DST | \
+ RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN)
#define CNXK_NIX_TX_OFFLOAD_CAPA \
- (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
- DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
- DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
- DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
- DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
- DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
- DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
- DEV_TX_OFFLOAD_IPV4_CKSUM | DEV_TX_OFFLOAD_SECURITY)
+ (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
+ RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
+ RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | \
+ RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \
+ RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
+ RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_SECURITY)
#define CNXK_NIX_RX_OFFLOAD_CAPA \
- (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
- DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
- DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
- DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP | \
- DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_SECURITY)
+ (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \
+ RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \
+ RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
+ RTE_ETH_RX_OFFLOAD_SECURITY)
#define RSS_IPV4_ENABLE \
- (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
- ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
+ (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
+ RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_SCTP)
#define RSS_IPV6_ENABLE \
- (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
- ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
+ (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | \
+ RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
#define RSS_IPV6_EX_ENABLE \
- (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
+ (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX)
#define RSS_MAX_LEVELS 3
#define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
#define CNXK_NIX_UDP_TUN_BITMASK \
- ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
- (1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
+ ((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) | \
+ (1ull << (RTE_MBUF_F_TX_TUNNEL_GENEVE >> 45)))
/* Subtype from inline outbound error event */
#define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
/* SPI will be in 20 bits of tag */
#define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
+#define CNXK_NIX_PFC_CHAN_COUNT 16
+
+#define CNXK_TM_MARK_VLAN_DEI BIT_ULL(0)
+#define CNXK_TM_MARK_IP_DSCP BIT_ULL(1)
+#define CNXK_TM_MARK_IP_ECN BIT_ULL(2)
+
+#define CNXK_TM_MARK_MASK \
+ (CNXK_TM_MARK_VLAN_DEI | CNXK_TM_MARK_IP_DSCP | CNXK_TM_MARK_IP_ECN)
+
+#define CNXK_TX_MARK_FMT_MASK (0xFFFFFFFFFFFFull)
+
struct cnxk_fc_cfg {
enum rte_eth_fc_mode mode;
uint8_t rx_pause;
uint8_t tx_pause;
};
+struct cnxk_pfc_cfg {
+ struct cnxk_fc_cfg fc_cfg;
+ uint16_t class_en;
+ uint16_t pause_time;
+ uint8_t rx_tc;
+ uint8_t rx_qid;
+ uint8_t tx_tc;
+ uint8_t tx_qid;
+};
+
struct cnxk_eth_qconf {
union {
struct rte_eth_txconf tx;
uint64_t *tx_tstamp;
} __plt_cache_aligned;
+struct cnxk_meter_node {
+#define MAX_PRV_MTR_NODES 10
+ TAILQ_ENTRY(cnxk_meter_node) next;
+ /**< Pointer to the next flow meter structure. */
+ uint32_t id; /**< Usr mtr id. */
+ struct cnxk_mtr_profile_node *profile;
+ struct cnxk_mtr_policy_node *policy;
+ uint32_t bpf_id; /**< Hw mtr id. */
+ uint32_t rq_num;
+ uint32_t *rq_id;
+ uint16_t level;
+ uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */
+ uint32_t prev_cnt;
+ uint32_t next_id; /**< Next mtr id for chaining */
+ bool is_prev;
+ bool is_next;
+ struct rte_mtr_params params;
+ struct roc_nix_bpf_objs profs;
+ bool is_used;
+ uint32_t ref_cnt;
+};
+
+struct action_rss {
+ enum rte_eth_hash_function func;
+ uint32_t level;
+ uint64_t types;
+ uint32_t key_len;
+ uint32_t queue_num;
+ uint8_t *key;
+ uint16_t *queue;
+};
+
+struct policy_actions {
+ uint32_t action_fate;
+ union {
+ uint16_t queue;
+ uint32_t mtr_id;
+ struct action_rss *rss_desc;
+ };
+};
+
+struct cnxk_mtr_policy_node {
+ TAILQ_ENTRY(cnxk_mtr_policy_node) next;
+ /**< Pointer to the next flow meter structure. */
+ uint32_t id; /**< Policy id */
+ uint32_t mtr_id; /** Meter id */
+ struct rte_mtr_meter_policy_params policy;
+ struct policy_actions actions[RTE_COLORS];
+ uint32_t ref_cnt;
+};
+
+struct cnxk_mtr_profile_node {
+ TAILQ_ENTRY(cnxk_mtr_profile_node) next;
+ struct rte_mtr_meter_profile profile; /**< Profile detail. */
+ uint32_t ref_cnt; /**< Use count. */
+ uint32_t id; /**< Profile id. */
+};
+
+TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node);
+TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node);
+TAILQ_HEAD(cnxk_mtr, cnxk_meter_node);
+
/* Security session private data */
struct cnxk_eth_sec_sess {
/* List entry */
/* Using inbound with inline device */
bool inl_dev;
- /* Device argument to force inline device for inb */
- bool force_inl_dev;
+ /* Device argument to disable inline device usage for inb */
+ bool no_inl_dev;
/* Active sessions */
uint16_t nb_sess;
/* List of sessions */
struct cnxk_eth_sec_sess_list list;
+
+ /* DPTR for WRITE_SA microcode op */
+ void *sa_dptr;
+
+ /* Lock to synchronize sa setup/release */
+ rte_spinlock_t lock;
};
/* Outbound security data */
/* List of sessions */
struct cnxk_eth_sec_sess_list list;
+
+ /* DPTR for WRITE_SA microcode op */
+ void *sa_dptr;
+
+ /* Lock to synchronize sa setup/release */
+ rte_spinlock_t lock;
};
struct cnxk_eth_dev {
uint16_t flags;
uint8_t ptype_disable;
bool scalar_ena;
+ bool tx_mark;
bool ptp_en;
+ bool rx_mark_update; /* Enable/Disable mark update to mbuf */
/* Pointer back to rte */
struct rte_eth_dev *eth_dev;
union {
struct {
uint64_t cq_min_4k : 1;
+ uint64_t ipsecd_drop_re_dis : 1;
+ uint64_t vec_drop_re_dis : 1;
};
uint64_t hwcap;
};
struct cnxk_eth_qconf *rx_qconf;
/* Flow control configuration */
+ uint16_t pfc_tc_sq_map[CNXK_NIX_PFC_CHAN_COUNT];
+ struct cnxk_pfc_cfg pfc_cfg;
struct cnxk_fc_cfg fc_cfg;
/* PTP Counters */
double clk_freq_mult;
uint64_t clk_delta;
+ /* Ingress policer */
+ enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX];
+ struct cnxk_mtr_profiles mtr_profiles;
+ struct cnxk_mtr_policy mtr_policy;
+ struct cnxk_mtr mtr;
+
/* Rx burst for cleanup(Only Primary) */
eth_rx_burst_t rx_pkt_burst_no_offload;
/* Security data */
struct cnxk_eth_dev_sec_inb inb;
struct cnxk_eth_dev_sec_outb outb;
+
+ /* Reassembly dynfield/flag offsets */
+ int reass_dynfield_off;
+ int reass_dynflag_bit;
};
struct cnxk_eth_rxq_sp {
/* Common security ops */
extern struct rte_security_ops cnxk_eth_sec_ops;
+/* Common tm ops */
+extern struct rte_tm_ops cnxk_tm_ops;
+
/* Ops */
int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
struct rte_pci_device *pci_dev);
struct rte_eth_fc_conf *fc_conf);
int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);
+int cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev,
+ struct rte_eth_pfc_queue_conf *pfc_conf);
+int cnxk_nix_priority_flow_ctrl_queue_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_pfc_queue_info *pfc_info);
int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev);
int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev);
int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev,
int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
uint16_t queue_idx, uint16_t tx_rate);
+int cnxk_nix_tm_mark_vlan_dei(struct rte_eth_dev *eth_dev, int mark_green,
+ int mark_yellow, int mark_red,
+ struct rte_tm_error *error);
+int cnxk_nix_tm_mark_ip_ecn(struct rte_eth_dev *eth_dev, int mark_green,
+ int mark_yellow, int mark_red,
+ struct rte_tm_error *error);
+int cnxk_nix_tm_mark_ip_dscp(struct rte_eth_dev *eth_dev, int mark_green,
+ int mark_yellow, int mark_red,
+ struct rte_tm_error *error);
+
+/* MTR */
+int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
/* RSS */
uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid,
struct rte_eth_txq_info *qinfo);
+/* Queue status */
+int cnxk_nix_rx_descriptor_status(void *rxq, uint16_t offset);
+int cnxk_nix_tx_descriptor_status(void *txq, uint16_t offset);
+uint32_t cnxk_nix_rx_queue_count(void *rxq);
+
/* Lookup configuration */
const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
void *cnxk_nix_fastpath_lookup_mem_get(void);
/* Other private functions */
int nix_recalc_mtu(struct rte_eth_dev *eth_dev);
+int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id);
+int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id,
+ struct cnxk_mtr_policy_node **policy);
+int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id,
+ uint32_t queue_num, const uint16_t *queue);
+int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id,
+ uint32_t prev_id, uint32_t next_id);
+int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id);
+struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev,
+ uint32_t cur_id);
+int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id,
+ uint32_t level);
+int nix_mtr_capabilities_init(struct rte_eth_dev *eth_dev);
+int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id);
+int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id);
+int nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t id,
+ struct rte_mtr_error *error);
+int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
+ uint32_t *prev_id, uint32_t *next_id,
+ struct cnxk_mtr_policy_node *policy,
+ int *tree_level);
+int nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,
+ struct cnxk_pfc_cfg *conf);
/* Inlines */
static __rte_always_inline uint64_t
rte_mbuf_timestamp_t *);
}
-static __rte_always_inline void
-cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,
- struct cnxk_timesync_info *tstamp,
- const uint8_t ts_enable, const uint8_t mseg_enable,
- uint64_t *tstamp_ptr)
-{
- if (ts_enable) {
- if (!mseg_enable) {
- mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
- mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET;
- }
-
- /* Reading the rx timestamp inserted by CGX, viz at
- * starting of the packet data.
- */
- *cnxk_nix_timestamp_dynfield(mbuf, tstamp) =
- rte_be_to_cpu_64(*tstamp_ptr);
- /* PKT_RX_IEEE1588_TMST flag needs to be set only in case
- * PTP packets are received.
- */
- if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {
- tstamp->rx_tstamp =
- *cnxk_nix_timestamp_dynfield(mbuf, tstamp);
- tstamp->rx_ready = 1;
- mbuf->ol_flags |= PKT_RX_IEEE1588_PTP |
- PKT_RX_IEEE1588_TMST |
- tstamp->rx_tstamp_dynflag;
- }
- }
-}
-
static __rte_always_inline uintptr_t
cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
{
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