/*-
* BSD LICENSE
*
- * Copyright(c) 2014-2016 Chelsio Communications.
+ * Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
void __iomem *bar2_addr; /* address of BAR2 Queue registers */
unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
+ struct sge_qstat *stat;
unsigned int cidx; /* consumer index */
unsigned int gts_idx; /* last gts write sent */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
+#define PCI_EXP_DEVCTL 0x0008 /* Device control */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
+#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
+#define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
{
u32 val32 = val;
- if (rte_eal_pci_write_config(adapter->pdev, &val32, sizeof(val32),
+ if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32),
addr) < 0)
dev_err(adapter, "Can't write to PCI config space\n");
}
static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr,
u32 *val)
{
- if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+ if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
addr) < 0)
dev_err(adapter, "Can't read from PCI config space\n");
}
{
u16 val16 = val;
- if (rte_eal_pci_write_config(adapter->pdev, &val16, sizeof(val16),
+ if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16),
addr) < 0)
dev_err(adapter, "Can't write to PCI config space\n");
}
static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr,
u16 *val)
{
- if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+ if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
addr) < 0)
dev_err(adapter, "Can't read from PCI config space\n");
}
static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr,
u8 *val)
{
- if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val),
+ if (rte_pci_read_config(adapter->pdev, val, sizeof(*val),
addr) < 0)
dev_err(adapter, "Can't read from PCI config space\n");
}
void t4_free_sge_resources(struct adapter *adap);
void t4_sge_tx_monitor_start(struct adapter *adap);
void t4_sge_tx_monitor_stop(struct adapter *adap);
-int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf);
+int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
+ uint16_t nb_pkts);
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
const struct pkt_gl *gl);
int t4_sge_init(struct adapter *adap);