int protocol_shift;
int ethertype_shift;
int macmatch_shift;
+ int tos_shift;
u64 hash_filter_mask;
};
bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
u8 fw_caps_support; /* 32-bit Port Capabilities */
u8 filter2_wr_support; /* FW support for FILTER2_WR */
+ u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
};
/* Firmware Port Capabilities types.
enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
- unsigned int qtype, u64 *pbar2_qoffset,
+ enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
unsigned int *pbar2_qid);
int t4_init_sge_params(struct adapter *adapter);