net/mlx5: implement vectorized MPRQ burst

[dpdk.git] / drivers / net / cxgbe / base / t4_hw.c

diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index c8514c9..9217956 100644 (file)
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -2517,6 +2517,10 @@ int t4_get_pfres(struct adapter *adapter)
 
        word = be32_to_cpu(rpl.type_to_neq);
        pfres->neq = G_FW_PFVF_CMD_NEQ(word);
+
+       word = be32_to_cpu(rpl.r_caps_to_nethctrl);
+       pfres->nethctrl = G_FW_PFVF_CMD_NETHCTRL(word);
+
        return 0;
 }
 
@@ -5040,6 +5044,10 @@ int t4_prep_adapter(struct adapter *adapter)
                adapter->params.arch.mps_rplc_size = 128;
                adapter->params.arch.nchan = NCHAN;
                adapter->params.arch.vfcount = 128;
+               /* Congestion map is for 4 channels so that
+                * MPS can have 4 priority per port.
+                */
+               adapter->params.arch.cng_ch_bits_log = 2;
                break;
        case CHELSIO_T6:
                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
@@ -5049,6 +5057,10 @@ int t4_prep_adapter(struct adapter *adapter)
                adapter->params.arch.mps_rplc_size = 256;
                adapter->params.arch.nchan = 2;
                adapter->params.arch.vfcount = 256;
+               /* Congestion map is for 2 channels so that
+                * MPS can have 8 priority per port.
+                */
+               adapter->params.arch.cng_ch_bits_log = 3;
                break;
        default:
                dev_err(adapter, "%s: Device %d is not supported\n",