net/ixgbe/base: update X550 SFP identification

[dpdk.git] / drivers / net / cxgbe / base / t4fw_interface.h

diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h
index 842aa12..e2d2ee8 100644 (file)
--- a/drivers/net/cxgbe/base/t4fw_interface.h
+++ b/drivers/net/cxgbe/base/t4fw_interface.h
@@ -55,6 +55,8 @@ enum fw_memtype {
 
 enum fw_wr_opcodes {
        FW_FILTER_WR            = 0x02,
+       FW_ULPTX_WR             = 0x04,
+       FW_TP_WR                = 0x05,
        FW_ETH_TX_PKT_WR        = 0x08,
        FW_ETH_TX_PKTS_WR       = 0x09,
        FW_ETH_TX_PKT_VM_WR     = 0x11,
@@ -77,6 +79,11 @@ struct fw_wr_hdr {
 #define V_FW_WR_OP(x)          ((x) << S_FW_WR_OP)
 #define G_FW_WR_OP(x)          (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
 
+/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
+ */
+#define S_FW_WR_ATOMIC         23
+#define V_FW_WR_ATOMIC(x)      ((x) << S_FW_WR_ATOMIC)
+
 /* work request immediate data length (hi)
  */
 #define S_FW_WR_IMMDLEN        0
@@ -93,6 +100,11 @@ struct fw_wr_hdr {
 #define G_FW_WR_EQUEQ(x)       (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
 #define F_FW_WR_EQUEQ          V_FW_WR_EQUEQ(1U)
 
+/* flow context identifier (lo)
+ */
+#define S_FW_WR_FLOWID         8
+#define V_FW_WR_FLOWID(x)      ((x) << S_FW_WR_FLOWID)
+
 /* length in units of 16-bytes (lo)
  */
 #define S_FW_WR_LEN16          0
@@ -333,6 +345,7 @@ enum fw_cmd_opcodes {
        FW_RSS_IND_TBL_CMD             = 0x20,
        FW_RSS_GLB_CONFIG_CMD          = 0x22,
        FW_RSS_VI_CONFIG_CMD           = 0x23,
+       FW_CLIP_CMD                    = 0x28,
        FW_DEBUG_CMD                   = 0x81,
 };
 
@@ -648,8 +661,12 @@ enum fw_params_param_dev {
  * physical and virtual function parameters
  */
 enum fw_params_param_pfvf {
+       FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
+       FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
        FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
        FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
+       FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
+       FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
        FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
        FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A
 };
@@ -729,6 +746,12 @@ struct fw_pfvf_cmd {
        __be32 r4;
 };
 
+#define S_FW_PFVF_CMD_PFN              8
+#define V_FW_PFVF_CMD_PFN(x)           ((x) << S_FW_PFVF_CMD_PFN)
+
+#define S_FW_PFVF_CMD_VFN              0
+#define V_FW_PFVF_CMD_VFN(x)           ((x) << S_FW_PFVF_CMD_VFN)
+
 #define S_FW_PFVF_CMD_NIQFLINT          20
 #define M_FW_PFVF_CMD_NIQFLINT          0xfff
 #define G_FW_PFVF_CMD_NIQFLINT(x)       \
@@ -788,6 +811,11 @@ enum fw_iq_type {
        FW_IQ_TYPE_FL_INT_CAP,
 };
 
+enum fw_iq_iqtype {
+       FW_IQ_IQTYPE_NIC = 1,
+       FW_IQ_IQTYPE_OFLD,
+};
+
 struct fw_iq_cmd {
        __be32 op_to_vfn;
        __be32 alloc_to_len16;
@@ -921,6 +949,9 @@ struct fw_iq_cmd {
        (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
 #define F_FW_IQ_CMD_IQFLINTCONGEN      V_FW_IQ_CMD_IQFLINTCONGEN(1U)
 
+#define S_FW_IQ_CMD_IQTYPE     24
+#define V_FW_IQ_CMD_IQTYPE(x)  ((x) << S_FW_IQ_CMD_IQTYPE)
+
 #define S_FW_IQ_CMD_FL0CNGCHMAP                20
 #define M_FW_IQ_CMD_FL0CNGCHMAP                0xf
 #define V_FW_IQ_CMD_FL0CNGCHMAP(x)     ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
@@ -1251,12 +1282,17 @@ struct fw_vi_cmd {
 /* Special VI_MAC command index ids */
 #define FW_VI_MAC_ADD_MAC              0x3FF
 #define FW_VI_MAC_ADD_PERSIST_MAC      0x3FE
+#define FW_VI_MAC_ID_BASED_FREE         0x3FC
 
 enum fw_vi_mac_smac {
        FW_VI_MAC_MPS_TCAM_ENTRY,
        FW_VI_MAC_SMT_AND_MPSTCAM
 };
 
+enum fw_vi_mac_entry_types {
+       FW_VI_MAC_TYPE_RAW = 0x2,
+};
+
 struct fw_vi_mac_cmd {
        __be32 op_to_viid;
        __be32 freemacs_to_len16;
@@ -1268,6 +1304,13 @@ struct fw_vi_mac_cmd {
                struct fw_vi_mac_hash {
                        __be64 hashvec;
                } hash;
+               struct fw_vi_mac_raw {
+                       __be32 raw_idx_pkd;
+                       __be32 data0_pkd;
+                       __be32 data1[2];
+                       __be64 data0m_pkd;
+                       __be32 data1m[2];
+               } raw;
        } u;
 };
 
@@ -1277,6 +1320,12 @@ struct fw_vi_mac_cmd {
 #define G_FW_VI_MAC_CMD_VIID(x)        \
        (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
 
+#define S_FW_VI_MAC_CMD_FREEMACS       31
+#define V_FW_VI_MAC_CMD_FREEMACS(x)    ((x) << S_FW_VI_MAC_CMD_FREEMACS)
+
+#define S_FW_VI_MAC_CMD_ENTRY_TYPE      23
+#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)   ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
+
 #define S_FW_VI_MAC_CMD_VALID          15
 #define M_FW_VI_MAC_CMD_VALID          0x1
 #define V_FW_VI_MAC_CMD_VALID(x)       ((x) << S_FW_VI_MAC_CMD_VALID)
@@ -1296,6 +1345,12 @@ struct fw_vi_mac_cmd {
 #define G_FW_VI_MAC_CMD_IDX(x) \
        (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
 
+#define S_FW_VI_MAC_CMD_RAW_IDX         16
+#define M_FW_VI_MAC_CMD_RAW_IDX         0xffff
+#define V_FW_VI_MAC_CMD_RAW_IDX(x)      ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
+#define G_FW_VI_MAC_CMD_RAW_IDX(x)      \
+       (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
+
 struct fw_vi_rxmode_cmd {
        __be32 op_to_viid;
        __be32 retval_len16;
@@ -2167,6 +2222,22 @@ struct fw_rss_vi_config_cmd {
        (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN   V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
 
+struct fw_clip_cmd {
+       __be32 op_to_write;
+       __be32 alloc_to_len16;
+       __be64 ip_hi;
+       __be64 ip_lo;
+       __be32 r4[2];
+};
+
+#define S_FW_CLIP_CMD_ALLOC            31
+#define V_FW_CLIP_CMD_ALLOC(x)         ((x) << S_FW_CLIP_CMD_ALLOC)
+#define F_FW_CLIP_CMD_ALLOC            V_FW_CLIP_CMD_ALLOC(1U)
+
+#define S_FW_CLIP_CMD_FREE             30
+#define V_FW_CLIP_CMD_FREE(x)          ((x) << S_FW_CLIP_CMD_FREE)
+#define F_FW_CLIP_CMD_FREE             V_FW_CLIP_CMD_FREE(1U)
+
 /******************************************************************************
  *   D E B U G   C O M M A N D s
  ******************************************************/