i40e/base: add PHY capabilities

[dpdk.git] / drivers / net / cxgbe / cxgbe_main.c

diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c
index dad0a98..3755444 100644 (file)
--- a/drivers/net/cxgbe/cxgbe_main.c
+++ b/drivers/net/cxgbe/cxgbe_main.c
@@ -383,7 +383,8 @@ static void print_port_info(struct adapter *adap)
                if (bufp != buf)
                        --bufp;
                sprintf(bufp, "BASE-%s",
-                       t4_get_port_type_description(pi->port_type));
+                       t4_get_port_type_description(
+                                       (enum fw_port_type)pi->port_type));
 
                dev_info(adap,
                         " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
@@ -410,7 +411,7 @@ static int adap_init0_tweaks(struct adapter *adapter)
         * Line Size, etc.  The firmware default is for a 4KB Page Size and
         * 64B Cache Line Size ...
         */
-       t4_fixup_host_params_compat(adapter, PAGE_SIZE, L1_CACHE_BYTES,
+       t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
                                    T5_LAST_REV);
 
        /*
@@ -629,7 +630,7 @@ static int adap_init0(struct adapter *adap)
                        dev_err(adap, "Failed to restart. Exit.\n");
                        goto bye;
                }
-               state &= ~DEV_STATE_INIT;
+               state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
        }
 
        t4_get_fw_version(adap, &adap->params.fw_vers);
@@ -1099,7 +1100,7 @@ int cxgbe_probe(struct adapter *adapter)
                qpp = 1 << ((t4_read_reg(adapter,
                                A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
                                & M_QUEUESPERPAGEPF0);
-               num_seg = PAGE_SIZE / UDBS_SEG_SIZE;
+               num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
                if (qpp > num_seg)
                        dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");