static inline bool is_x_1g_port(const struct link_config *lc)
{
- return ((lc->supported & FW_PORT_CAP_SPEED_1G) != 0);
+ return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
}
static inline bool is_x_10g_port(const struct link_config *lc)
}
}
+void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
+{
+ t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
+ &pi->stats_base);
+}
+
+void cxgbe_stats_reset(struct port_info *pi)
+{
+ t4_clr_port_stats(pi->adapter, pi->tx_chan);
+}
+
static void setup_memwin(struct adapter *adap)
{
u32 mem_win0_base;
if (bufp != buf)
--bufp;
sprintf(bufp, "BASE-%s",
- t4_get_port_type_description(pi->port_type));
+ t4_get_port_type_description(
+ (enum fw_port_type)pi->port_type));
dev_info(adap,
" " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
* Line Size, etc. The firmware default is for a 4KB Page Size and
* 64B Cache Line Size ...
*/
- t4_fixup_host_params_compat(adapter, PAGE_SIZE, L1_CACHE_BYTES,
+ t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
T5_LAST_REV);
/*
t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
V_PKTSHIFT(rx_dma_offset));
+ t4_set_reg_field(adapter, A_SGE_FLM_CFG,
+ V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
+ V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
+
+ t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
+ V_IDMAARBROUNDROBIN(1U));
+
/*
* Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
* adds the pseudo header itself.
dev_err(adap, "Failed to restart. Exit.\n");
goto bye;
}
- state &= ~DEV_STATE_INIT;
+ state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
}
t4_get_fw_version(adap, &adap->params.fw_vers);
{
struct adapter *adapter = pi->adapter;
int ret;
+ unsigned int mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
/*
* We do not set address filters and promiscuity here, the stack does
* that step explicitly.
*/
- ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, 1500, -1, -1,
+ ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
-1, 1, true);
if (ret == 0) {
ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
qpp = 1 << ((t4_read_reg(adapter,
A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
& M_QUEUESPERPAGEPF0);
- num_seg = PAGE_SIZE / UDBS_SEG_SIZE;
+ num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
if (qpp > num_seg)
dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");