static void tid_free(struct tid_info *t)
{
if (t->tid_tab) {
- if (t->ftid_bmap)
- rte_bitmap_free(t->ftid_bmap);
+ rte_bitmap_free(t->ftid_bmap);
if (t->ftid_bmap_array)
t4_os_free(t->ftid_bmap_array);
struct sge_eth_txq *t = &s->ethtxq[i];
init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
- r->usembufs = 1;
- r->fl.size = (r->usembufs ? 1024 : 72);
+ r->fl.size = 1024;
t->q.size = 1024;
}
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
adap->params.vi_enable_rx = (ret == 0 && val[0] != 0);
+ /* Read the RAW MPS entries. In T6, the last 2 TCAM entries
+ * are reserved for RAW MAC addresses (rawf = 2, one per port).
+ */
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
+ params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START);
+ params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END);
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
+ params, val);
+ if (ret == 0) {
+ adap->params.rawf_start = val[0];
+ adap->params.rawf_size = val[1] - val[0] + 1;
+ }
+ }
+
/*
* The MTU/MSS Table is initialized by now, so load their values. If
* we're initializing the adapter, then we'll make any modifications
unsigned int mtu;
int ret;
- mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
- (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
+ mtu = pi->eth_dev->data->mtu;
conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
* that step explicitly.
*/
ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
- !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
+ !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP),
true);
if (ret == 0) {
ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
}
if (ret == 0 && cxgbe_force_linkup(adapter))
- pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
+ pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
return ret;
}
if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
- if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
+ if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
- if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
+ if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
F_FW_RSS_VI_CONFIG_CMD_UDPEN;
{
#define SET_SPEED(__speed_name) \
do { \
- *speed_caps |= ETH_LINK_ ## __speed_name; \
+ *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \
} while (0)
#define FW_CAPS_TO_SPEED(__fw_name) \
speed_caps);
if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
- *speed_caps |= ETH_LINK_SPEED_FIXED;
+ *speed_caps |= RTE_ETH_LINK_SPEED_FIXED;
}
/**