(w)->wr.wr_lo = cpu_to_be64(0); \
} while (0)
+#define INIT_TP_WR_MIT_CPL(w, cpl, tid) do { \
+ INIT_TP_WR(w, tid); \
+ OPCODE_TID(w) = cpu_to_be32(MK_OPCODE_TID(cpl, tid)); \
+} while (0)
+
+#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
+ (w)->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) | \
+ V_FW_WR_ATOMIC(atomic)); \
+ (w)->wr.wr_mid = cpu_to_be32(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
+ V_FW_WR_FLOWID(tid)); \
+ (w)->wr.wr_lo = cpu_to_be64(0); \
+} while (0)
+
/*
* Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
*/
unsigned int atids_in_use;
/* TIDs in the TCAM */
- rte_atomic32_t tids_in_use;
+ u32 tids_in_use;
/* TIDs in the HASH */
- rte_atomic32_t hash_tids_in_use;
- rte_atomic32_t conns_in_use;
+ u32 hash_tids_in_use;
+ u32 conns_in_use;
rte_spinlock_t atid_lock __rte_cache_aligned;
rte_spinlock_t ftid_lock;
int cxgbe_alloc_atid(struct tid_info *t, void *data);
void cxgbe_free_atid(struct tid_info *t, unsigned int atid);
+void cxgbe_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid,
+ unsigned short family);
void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
unsigned short family);