/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
*
*/
#ifndef __DPAA_ETHDEV_H__
#include <fsl_usd.h>
#include <fsl_qman.h>
#include <fsl_bman.h>
-#include <of.h>
+#include <dpaa_of.h>
#include <netcfg.h>
+#define MAX_DPAA_CORES 4
#define DPAA_MBUF_HW_ANNOTATION 64
#define DPAA_FD_PTA_SIZE 64
-#if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
-#error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
-#endif
-
/* mbuf->seqn will be used to store event entry index for
* driver specific usage. For parallel mode queues, invalid
* index will be set and for atomic mode queues, valid value
/* Alignment to use for cpu-local structs to avoid coherency problems. */
#define MAX_CACHELINE 64
-#define DPAA_MIN_RX_BUF_SIZE 512
#define DPAA_MAX_RX_PKT_LEN 10240
+#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
+
/* RX queue tail drop threshold (CGR Based) in frame count */
#define CGR_RX_PERFQ_THRESH 256
#define DPAA_PCD_FQID_START 0x400
#define DPAA_PCD_FQID_MULTIPLIER 0x100
#define DPAA_DEFAULT_NUM_PCD_QUEUES 1
-#define DPAA_MAX_NUM_PCD_QUEUES 32
+#define DPAA_MAX_NUM_PCD_QUEUES 4
#define DPAA_IF_TX_PRIORITY 3
#define DPAA_IF_RX_PRIORITY 0
#define DPAA_DEBUG_FQ_TX_ERROR 1
#define DPAA_RSS_OFFLOAD_ALL ( \
+ ETH_RSS_L2_PAYLOAD | \
ETH_RSS_IP | \
ETH_RSS_UDP | \
ETH_RSS_TCP | \