net/dpaa: add frame count based tail drop with CGR

[dpdk.git] / drivers / net / dpaa / dpaa_ethdev.h

diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h
index bd63ee0..f00a77a 100644 (file)
--- a/drivers/net/dpaa/dpaa_ethdev.h
+++ b/drivers/net/dpaa/dpaa_ethdev.h
@@ -17,11 +17,6 @@
 #include <of.h>
 #include <netcfg.h>
 
-/* DPAA SoC identifier; If this is not available, it can be concluded
- * that board is non-DPAA. Single slot is currently supported.
- */
-#define DPAA_SOC_ID_FILE               "sys/devices/soc0/soc_id"
-
 #define DPAA_MBUF_HW_ANNOTATION                64
 #define DPAA_FD_PTA_SIZE               64
 
@@ -39,10 +34,8 @@
 #define DPAA_MIN_RX_BUF_SIZE 512
 #define DPAA_MAX_RX_PKT_LEN  10240
 
-/* RX queue tail drop threshold
- * currently considering 32 KB packets.
- */
-#define CONG_THRESHOLD_RX_Q  (32 * 1024)
+/* RX queue tail drop threshold (CGR Based) in frame count */
+#define CGR_RX_PERFQ_THRESH 256
 
 /*max mac filter for memac(8) including primary mac addr*/
 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
@@ -50,10 +43,15 @@
 /*Maximum number of slots available in TX ring*/
 #define MAX_TX_RING_SLOTS      8
 
+#ifndef VLAN_TAG_SIZE
+#define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
+#endif
+
 /* PCD frame queues */
 #define DPAA_PCD_FQID_START            0x400
 #define DPAA_PCD_FQID_MULTIPLIER       0x100
 #define DPAA_DEFAULT_NUM_PCD_QUEUES    1
+#define DPAA_MAX_NUM_PCD_QUEUES                32
 
 #define DPAA_IF_TX_PRIORITY            3
 #define DPAA_IF_RX_PRIORITY            4
@@ -103,6 +101,7 @@ struct dpaa_if {
        char *name;
        const struct fm_eth_port_cfg *cfg;
        struct qman_fq *rx_queues;
+       struct qman_cgr *cgr_rx;
        struct qman_fq *tx_queues;
        struct qman_fq debug_queues[2];
        uint16_t nb_rx_queues;