/* enable timestamp in mbuf */
bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
+uint64_t dpaa2_timestamp_rx_dynflag;
+int dpaa2_timestamp_dynfield_offset = -1;
struct rte_dpaa2_xstats_name_off {
char name[RTE_ETH_XSTATS_NAME_SIZE];
};
static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
- RTE_ETH_FILTER_ADD,
- RTE_ETH_FILTER_DELETE,
- RTE_ETH_FILTER_UPDATE,
- RTE_ETH_FILTER_FLUSH,
RTE_ETH_FILTER_GET
};
#if !defined(RTE_LIBRTE_IEEE1588)
if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
#endif
+ {
+ ret = rte_mbuf_dyn_rx_timestamp_register(
+ &dpaa2_timestamp_dynfield_offset,
+ &dpaa2_timestamp_rx_dynflag);
+ if (ret != 0) {
+ DPAA2_PMD_ERR("Error to register timestamp field/flag");
+ return -rte_errno;
+ }
dpaa2_enable_ts[dev->data->port_id] = true;
+ }
if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
tx_l3_csum_offload = true;
if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
+ eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
+
/* Invoke PMD device initialization function */
diag = dpaa2_dev_init(eth_dev);
if (diag == 0) {