/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016 NXP
+ * Copyright 2016-2019 NXP
*
*/
#define MAX_TCS DPNI_MAX_TC
#define MAX_RX_QUEUES 128
#define MAX_TX_QUEUES 16
+#define MAX_DPNI 8
/*default tc to be used for ,congestion, distribution etc configuration. */
#define DPAA2_DEF_TC 0
#define CONG_RETRY_COUNT 18000
/* RX queue tail drop threshold
- * currently considering 32 KB packets
+ * currently considering 64 KB packets
*/
-#define CONG_THRESHOLD_RX_Q (64 * 1024)
+#define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024)
#define CONG_RX_OAL 128
/* Size of the input SMMU mapped memory required by MC */
#define DPAA2_RX_TAILDROP_OFF 0x04
#define DPAA2_RSS_OFFLOAD_ALL ( \
+ ETH_RSS_L2_PAYLOAD | \
ETH_RSS_IP | \
ETH_RSS_UDP | \
ETH_RSS_TCP | \
uint32_t options;
void *rx_vq[MAX_RX_QUEUES];
void *tx_vq[MAX_TX_QUEUES];
-
struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
+ void *tx_conf_vq[MAX_TX_QUEUES];
+ uint8_t tx_conf_en;
uint8_t max_mac_filters;
uint8_t max_vlan_filters;
uint8_t num_rx_tc;
uint8_t flags; /*dpaa2 config flags */
uint8_t en_ordered;
uint8_t en_loose_ordered;
+ uint8_t max_cgs;
+ uint8_t cgid_in_use[MAX_RX_QUEUES];
struct pattern_s {
uint8_t item_count;
uint64_t qos_extract_param;
uint64_t fs_extract_param[MAX_TCS];
} extract;
+
+ uint16_t ss_offset;
+ uint64_t ss_iova;
+ uint64_t ss_param_iova;
+#if defined(RTE_LIBRTE_IEEE1588)
+ /*stores timestamp of last received packet on dev*/
+ uint64_t rx_timestamp;
+ /*stores timestamp of last received tx confirmation packet on dev*/
+ uint64_t tx_timestamp;
+ /* stores pointer to next tx_conf queue that should be processed,
+ * it corresponds to last packet transmitted
+ */
+ struct dpaa2_queue *next_tx_conf_queue;
+#endif
+
+ struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
+
+ LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
};
int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
int eth_rx_queue_id,
- uint16_t dpcon_id,
+ struct dpaa2_dpcon_dev *dpcon,
const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
int eth_rx_queue_id);
+uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
+
uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
uint16_t nb_pkts);
uint16_t nb_pkts);
uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
-
+void dpaa2_flow_clean(struct rte_eth_dev *dev);
+uint16_t dpaa2_dev_tx_conf(void *queue) __attribute__((unused));
+
+#if defined(RTE_LIBRTE_IEEE1588)
+int dpaa2_timesync_enable(struct rte_eth_dev *dev);
+int dpaa2_timesync_disable(struct rte_eth_dev *dev);
+int dpaa2_timesync_read_time(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+int dpaa2_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *timestamp);
+int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp,
+ uint32_t flags __rte_unused);
+int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+#endif
#endif /* _DPAA2_ETHDEV_H */