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net/bnxt: fix Rx configuration
[dpdk.git] / drivers / net / dpaa2 / dpaa2_ethdev.h
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index 94cf253..a459181 100644 (file)
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2020 NXP
+ *   Copyright 2016-2022 NXP
  *
  */
 
@@ -11,21 +11,29 @@
 #include <rte_event_eth_rx_adapter.h>
 #include <rte_pmd_dpaa2.h>
 
+#include <rte_fslmc.h>
 #include <dpaa2_hw_pvt.h>
+#include "dpaa2_tm.h"
 
 #include <mc/fsl_dpni.h>
 #include <mc/fsl_mc_sys.h>
 
 #define DPAA2_MIN_RX_BUF_SIZE 512
 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
+#define NET_DPAA2_PMD_DRIVER_NAME net_dpaa2
 
 #define MAX_TCS                        DPNI_MAX_TC
 #define MAX_RX_QUEUES          128
 #define MAX_TX_QUEUES          16
 #define MAX_DPNI               8
+#define DPAA2_MAX_CHANNELS     16
 
 #define DPAA2_RX_DEFAULT_NBDESC 512
 
+#define DPAA2_ETH_MAX_LEN (RTE_ETHER_MTU + \
+                          RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
+                          VLAN_TAG_SIZE)
+
 /*default tc to be used for ,congestion, distribution etc configuration. */
 #define DPAA2_DEF_TC           0
 
@@ -55,13 +63,33 @@
 
 /* Disable RX tail drop, default is enable */
 #define DPAA2_RX_TAILDROP_OFF  0x04
+/* Tx confirmation enabled */
+#define DPAA2_TX_CONF_ENABLE   0x06
+
+/* HW loopback the egress traffic to self ingress*/
+#define DPAA2_TX_MAC_LOOPBACK_MODE 0x20
+
+#define DPAA2_TX_SERDES_LOOPBACK_MODE 0x40
+
+#define DPAA2_TX_DPNI_LOOPBACK_MODE 0x80
+
+#define DPAA2_TX_LOOPBACK_MODE \
+       (DPAA2_TX_MAC_LOOPBACK_MODE | \
+       DPAA2_TX_SERDES_LOOPBACK_MODE | \
+       DPAA2_TX_DPNI_LOOPBACK_MODE)
 
 #define DPAA2_RSS_OFFLOAD_ALL ( \
-       ETH_RSS_L2_PAYLOAD | \
-       ETH_RSS_IP | \
-       ETH_RSS_UDP | \
-       ETH_RSS_TCP | \
-       ETH_RSS_SCTP)
+       RTE_ETH_RSS_L2_PAYLOAD | \
+       RTE_ETH_RSS_IP | \
+       RTE_ETH_RSS_UDP | \
+       RTE_ETH_RSS_TCP | \
+       RTE_ETH_RSS_SCTP | \
+       RTE_ETH_RSS_MPLS | \
+       RTE_ETH_RSS_C_VLAN | \
+       RTE_ETH_RSS_S_VLAN | \
+       RTE_ETH_RSS_ESP | \
+       RTE_ETH_RSS_AH | \
+       RTE_ETH_RSS_PPPOE)
 
 /* LX2 FRC Parsed values (Little Endian) */
 #define DPAA2_PKT_TYPE_ETHER           0x0060
@@ -92,6 +120,8 @@
 
 /* enable timestamp in mbuf*/
 extern bool dpaa2_enable_ts[];
+extern uint64_t dpaa2_timestamp_rx_dynflag;
+extern int dpaa2_timestamp_dynfield_offset;
 
 #define DPAA2_QOS_TABLE_RECONFIGURE    1
 #define DPAA2_FS_TABLE_RECONFIGURE     2
@@ -101,9 +131,12 @@ extern bool dpaa2_enable_ts[];
 
 #define DPAA2_FLOW_MAX_KEY_SIZE                16
 
-/*Externaly defined*/
+/* Externally defined */
 extern const struct rte_flow_ops dpaa2_flow_ops;
-extern enum rte_filter_type dpaa2_filter_type;
+
+extern const struct rte_tm_ops dpaa2_tm_ops;
+
+extern bool dpaa2_enable_err_queue;
 
 #define IP_ADDRESS_OFFSET_INVALID (-1)
 
@@ -141,15 +174,17 @@ struct dpaa2_dev_priv {
        void *rx_vq[MAX_RX_QUEUES];
        void *tx_vq[MAX_TX_QUEUES];
        struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
-       void *tx_conf_vq[MAX_TX_QUEUES];
-       uint8_t tx_conf_en;
+       void *tx_conf_vq[MAX_TX_QUEUES * DPAA2_MAX_CHANNELS];
+       void *rx_err_vq;
+       uint8_t flags; /*dpaa2 config flags */
        uint8_t max_mac_filters;
        uint8_t max_vlan_filters;
        uint8_t num_rx_tc;
+       uint8_t num_tx_tc;
        uint16_t qos_entries;
        uint16_t fs_entries;
        uint8_t dist_queues;
-       uint8_t flags; /*dpaa2 config flags */
+       uint8_t num_channels;
        uint8_t en_ordered;
        uint8_t en_loose_ordered;
        uint8_t max_cgs;
@@ -170,8 +205,12 @@ struct dpaa2_dev_priv {
        struct dpaa2_queue *next_tx_conf_queue;
 
        struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
+       rte_spinlock_t lpbk_qp_lock;
 
+       uint8_t channel_inuse;
        LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
+       LIST_HEAD(nodes, dpaa2_tm_node) nodes;
+       LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles;
 };
 
 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
@@ -183,7 +222,8 @@ int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
                           uint8_t tc_index);
 
-int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
+int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv,
+       struct fsl_mc_io *dpni, void *blist);
 
 __rte_internal
 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
@@ -220,10 +260,14 @@ void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
                              uint16_t nb_pkts);
-uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
-void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
+__rte_internal
+uint16_t dpaa2_dev_tx_multi_txq_ordered(void **queue,
+               struct rte_mbuf **bufs, uint16_t nb_pkts);
+
+void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci, struct dpaa2_queue *dpaa2_q);
 void dpaa2_flow_clean(struct rte_eth_dev *dev);
 uint16_t dpaa2_dev_tx_conf(void *queue)  __rte_unused;
+int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev);
 
 int dpaa2_timesync_enable(struct rte_eth_dev *dev);
 int dpaa2_timesync_disable(struct rte_eth_dev *dev);
@@ -237,4 +281,13 @@ int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
                                                uint32_t flags __rte_unused);
 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
                                          struct timespec *timestamp);
+
+int dpaa2_dev_recycle_config(struct rte_eth_dev *eth_dev);
+int dpaa2_dev_recycle_deconfig(struct rte_eth_dev *eth_dev);
+int dpaa2_dev_recycle_qp_setup(struct rte_dpaa2_device *dpaa2_dev,
+       uint16_t qidx, uint64_t cntx,
+       eth_rx_burst_t tx_lpbk, eth_tx_burst_t rx_lpbk,
+       struct dpaa2_queue **txq,
+       struct dpaa2_queue **rxq);
+
 #endif /* _DPAA2_ETHDEV_H */
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