#define DPAA2_MIN_RX_BUF_SIZE 512
#define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
+#define NET_DPAA2_PMD_DRIVER_NAME net_dpaa2
#define MAX_TCS DPNI_MAX_TC
#define MAX_RX_QUEUES 128
ETH_RSS_UDP | \
ETH_RSS_TCP | \
ETH_RSS_SCTP | \
- ETH_RSS_MPLS)
+ ETH_RSS_MPLS | \
+ ETH_RSS_C_VLAN | \
+ ETH_RSS_S_VLAN | \
+ ETH_RSS_ESP | \
+ ETH_RSS_AH | \
+ ETH_RSS_PPPOE)
/* LX2 FRC Parsed values (Little Endian) */
#define DPAA2_PKT_TYPE_ETHER 0x0060
/*Externaly defined*/
extern const struct rte_flow_ops dpaa2_flow_ops;
-extern enum rte_filter_type dpaa2_filter_type;
extern const struct rte_tm_ops dpaa2_tm_ops;
void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
void dpaa2_flow_clean(struct rte_eth_dev *dev);
uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused;
+int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev);
int dpaa2_timesync_enable(struct rte_eth_dev *dev);
int dpaa2_timesync_disable(struct rte_eth_dev *dev);