/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2021 NXP
*
*/
#define DPAA2_MIN_RX_BUF_SIZE 512
#define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
+#define NET_DPAA2_PMD_DRIVER_NAME net_dpaa2
#define MAX_TCS DPNI_MAX_TC
#define MAX_RX_QUEUES 128
/* Disable RX tail drop, default is enable */
#define DPAA2_RX_TAILDROP_OFF 0x04
+/* Tx confirmation enabled */
+#define DPAA2_TX_CONF_ENABLE 0x08
#define DPAA2_RSS_OFFLOAD_ALL ( \
ETH_RSS_L2_PAYLOAD | \
ETH_RSS_UDP | \
ETH_RSS_TCP | \
ETH_RSS_SCTP | \
- ETH_RSS_MPLS)
+ ETH_RSS_MPLS | \
+ ETH_RSS_C_VLAN | \
+ ETH_RSS_S_VLAN | \
+ ETH_RSS_ESP | \
+ ETH_RSS_AH | \
+ ETH_RSS_PPPOE)
/* LX2 FRC Parsed values (Little Endian) */
#define DPAA2_PKT_TYPE_ETHER 0x0060
/*Externaly defined*/
extern const struct rte_flow_ops dpaa2_flow_ops;
-extern enum rte_filter_type dpaa2_filter_type;
extern const struct rte_tm_ops dpaa2_tm_ops;
+extern bool dpaa2_enable_err_queue;
+
#define IP_ADDRESS_OFFSET_INVALID (-1)
struct dpaa2_key_info {
void *tx_vq[MAX_TX_QUEUES];
struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
void *tx_conf_vq[MAX_TX_QUEUES];
- uint8_t tx_conf_en;
+ void *rx_err_vq;
+ uint8_t flags; /*dpaa2 config flags */
uint8_t max_mac_filters;
uint8_t max_vlan_filters;
uint8_t num_rx_tc;
uint16_t qos_entries;
uint16_t fs_entries;
uint8_t dist_queues;
- uint8_t flags; /*dpaa2 config flags */
uint8_t en_ordered;
uint8_t en_loose_ordered;
uint8_t max_cgs;
void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
void dpaa2_flow_clean(struct rte_eth_dev *dev);
uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused;
+int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev);
int dpaa2_timesync_enable(struct rte_eth_dev *dev);
int dpaa2_timesync_disable(struct rte_eth_dev *dev);