/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
*
* Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2020 NXP
*
*/
#ifndef _FSL_DPNI_CMD_H
/* DPNI Version */
#define DPNI_VER_MAJOR 7
-#define DPNI_VER_MINOR 9
+#define DPNI_VER_MINOR 13
#define DPNI_CMD_BASE_VERSION 1
#define DPNI_CMD_VERSION_2 2
#define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016)
#define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017)
-#define DPNI_CMDID_SET_POOLS DPNI_CMD_V2(0x200)
+#define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200)
#define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B)
#define DPNI_CMDID_GET_QDID DPNI_CMD(0x210)
#define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223)
#define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224)
#define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225)
-#define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD(0x226)
+#define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD_V2(0x226)
#define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227)
#define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228)
#define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230)
-#define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD(0x231)
+#define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231)
#define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232)
#define DPNI_CMDID_CLR_VLAN_FILTERS DPNI_CMD(0x233)
#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V3(0x235)
+#define DPNI_CMDID_SET_RX_TC_POLICING DPNI_CMD(0x23E)
+
#define DPNI_CMDID_SET_QOS_TBL DPNI_CMD_V2(0x240)
-#define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD(0x241)
+#define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD_V2(0x241)
#define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242)
#define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243)
#define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244)
#define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245)
#define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246)
+#define DPNI_CMDID_SET_TX_PRIORITIES DPNI_CMD_V2(0x250)
+#define DPNI_CMDID_GET_RX_TC_POLICING DPNI_CMD(0x251)
+
#define DPNI_CMDID_GET_STATISTICS DPNI_CMD_V3(0x25D)
#define DPNI_CMDID_RESET_STATISTICS DPNI_CMD(0x25E)
#define DPNI_CMDID_GET_QUEUE DPNI_CMD_V2(0x25F)
#define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C)
#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266)
#define DPNI_CMDID_GET_TX_CONFIRMATION_MODE DPNI_CMD(0x26D)
+#define DPNI_CMDID_LOAD_SW_SEQUENCE DPNI_CMD(0x270)
+#define DPNI_CMDID_ENABLE_SW_SEQUENCE DPNI_CMD(0x271)
+#define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT DPNI_CMD(0x272)
#define DPNI_CMDID_SET_OPR DPNI_CMD(0x26e)
#define DPNI_CMDID_GET_OPR DPNI_CMD(0x26f)
#define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273)
struct dpni_cmd_set_pools {
uint8_t num_dpbp;
uint8_t backup_pool_mask;
- uint16_t pad;
+ uint8_t pad;
+ uint8_t pool_options;
struct dpni_cmd_pool pool[8];
uint16_t buffer_size[8];
};
uint64_t advertising;
};
+#define DPNI_COUPLED_SHIFT 0
+#define DPNI_COUPLED_SIZE 1
+
+struct dpni_cmd_set_tx_shaping {
+ uint16_t tx_cr_max_burst_size;
+ uint16_t tx_er_max_burst_size;
+ uint32_t pad;
+ uint32_t tx_cr_rate_limit;
+ uint32_t tx_er_rate_limit;
+ /* from LSB: coupled:1 */
+ uint8_t coupled;
+};
+
struct dpni_cmd_set_max_frame_length {
uint16_t max_frame_length;
};
uint8_t mac_addr[6];
};
+#define DPNI_MAC_SET_QUEUE_ACTION 1
+
struct dpni_cmd_add_mac_addr {
- uint16_t pad;
+ uint8_t flags;
+ uint8_t pad;
uint8_t mac_addr[6];
+ uint8_t tc_id;
+ uint8_t fq_id;
};
struct dpni_cmd_remove_mac_addr {
uint8_t en;
};
+#define DPNI_VLAN_SET_QUEUE_ACTION 1
+
struct dpni_cmd_vlan_id {
- uint32_t pad;
+ uint8_t flags;
+ uint8_t tc_id;
+ uint8_t flow_id;
+ uint8_t pad;
uint16_t vlan_id;
};
uint64_t key_cfg_iova;
};
+#define DPNI_QOS_OPT_SET_TC_ONLY 0x0
+#define DPNI_QOS_OPT_SET_FLOW_ID 0x1
+
struct dpni_cmd_add_qos_entry {
- uint16_t pad;
+ uint8_t flags;
+ uint8_t flow_id;
uint8_t tc_id;
uint8_t key_size;
uint16_t index;
uint8_t tc_id;
};
+#define DPNI_MODE_SHIFT 0
+#define DPNI_MODE_SIZE 4
+#define DPNI_COLOR_SHIFT 4
+#define DPNI_COLOR_SIZE 4
+#define DPNI_UNITS_SHIFT 0
+#define DPNI_UNITS_SIZE 4
+
+struct dpni_cmd_set_rx_tc_policing {
+ /* from LSB: mode:4 color:4 */
+ uint8_t mode_color;
+ /* from LSB: units: 4 */
+ uint8_t units;
+ uint8_t tc_id;
+ uint8_t pad;
+ uint32_t options;
+ uint32_t cir;
+ uint32_t cbs;
+ uint32_t eir;
+ uint32_t ebs;
+};
+
+struct dpni_cmd_get_rx_tc_policing {
+ uint16_t pad;
+ uint8_t tc_id;
+};
+
+struct dpni_rsp_get_rx_tc_policing {
+ /* from LSB: mode:4 color:4 */
+ uint8_t mode_color;
+ /* from LSB: units: 4 */
+ uint8_t units;
+ uint16_t pad;
+ uint32_t options;
+ uint32_t cir;
+ uint32_t cbs;
+ uint32_t eir;
+ uint32_t ebs;
+};
+
#define DPNI_DROP_ENABLE_SHIFT 0
#define DPNI_DROP_ENABLE_SIZE 1
#define DPNI_DROP_UNITS_SHIFT 2
uint64_t key_cfg_iova;
};
+struct dpni_load_sw_sequence {
+ uint8_t dest;
+ uint8_t pad0[7];
+ uint16_t ss_offset;
+ uint16_t pad1;
+ uint16_t ss_size;
+ uint16_t pad2;
+ uint64_t ss_iova;
+};
+
+struct dpni_enable_sw_sequence {
+ uint8_t dest;
+ uint8_t pad0[7];
+ uint16_t ss_offset;
+ uint16_t hxs;
+ uint8_t set_start;
+ uint8_t pad1[3];
+ uint8_t param_offset;
+ uint8_t pad2[3];
+ uint8_t param_size;
+ uint8_t pad3[3];
+ uint64_t param_iova;
+};
+
+struct dpni_get_sw_sequence_layout {
+ uint8_t src;
+ uint8_t pad0[7];
+ uint64_t layout_iova;
+};
+
+struct dpni_sw_sequence_layout_entry {
+ uint16_t ss_offset;
+ uint16_t ss_size;
+ uint8_t param_offset;
+ uint8_t param_size;
+ uint16_t pad;
+};
+
#pragma pack(pop)
#endif /* _FSL_DPNI_CMD_H */
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