net/hns3: fix secondary process reference count

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.c

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 85344eb..14f86b7 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001 - 2015 Intel Corporation
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 /* 82562G 10/100 Network Connection
@@ -51,11 +51,9 @@ STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
-#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
                                              u8 *mc_addr_list,
                                              u32 mc_addr_count);
-#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
@@ -297,13 +295,11 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
         */
        e1000_gate_hw_phy_config_ich8lan(hw, true);
 
-#ifdef ULP_SUPPORT
        /* It is not possible to be certain of the current state of ULP
         * so forcibly disable it.
         */
        hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 
-#endif /* ULP_SUPPORT */
        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val) {
                DEBUGOUT("Failed to initialize PHY flow\n");
@@ -318,6 +314,7 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -467,6 +464,7 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch_lpt:
                case e1000_pch_spt:
                case e1000_pch_cnp:
+               case e1000_pch_adp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -699,9 +697,7 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
-#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
        u16 pci_cfg;
-#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 
        DEBUGFUNC("e1000_init_mac_params_ich8lan");
 
@@ -772,14 +768,12 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
-#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
+       case e1000_pch_adp:
                /* multicast address update for pch2 */
                mac->ops.update_mc_addr_list =
                        e1000_update_mc_addr_list_pch2lan;
                /* fall-through */
-#endif
        case e1000_pchlan:
-#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
                /* save PCH revision_id */
                e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
                /* SPT uses full byte for revision ID,
@@ -789,7 +783,6 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
                        hw->revision_id = (u8)(pci_cfg &= 0x00FF);
                else
                        hw->revision_id = (u8)(pci_cfg &= 0x000F);
-#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
                /* ID LED init */
@@ -1073,7 +1066,6 @@ update_fextnvm6:
        return ret_val;
 }
 
-#ifdef ULP_SUPPORT
 /**
  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
  *  @hw: pointer to the HW structure
@@ -1452,7 +1444,6 @@ out:
        return ret_val;
 }
 
-#endif /* ULP_SUPPORT */
 
 
 /**
@@ -1764,6 +1755,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
                break;
        default:
@@ -2078,7 +2070,6 @@ out:
        return -E1000_ERR_CONFIG;
 }
 
-#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 /**
  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
  *  @hw: pointer to the HW structure
@@ -2123,7 +2114,6 @@ release:
        hw->phy.ops.release(hw);
 }
 
-#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
 /**
  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
  *  @hw: pointer to the HW structure
@@ -2231,6 +2221,7 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -2674,7 +2665,6 @@ release:
        hw->phy.ops.release(hw);
 }
 
-#ifndef CRC32_OS_SUPPORT
 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
 {
        u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
@@ -2693,7 +2683,6 @@ STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
        return ~crc;
 }
 
-#endif /* CRC32_OS_SUPPORT */
 /**
  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
  *  with 82579 PHY
@@ -2738,13 +2727,8 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
                        mac_addr[4] = (addr_high & 0xFF);
                        mac_addr[5] = ((addr_high >> 8) & 0xFF);
 
-#ifndef CRC32_OS_SUPPORT
                        E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
                                        e1000_calc_rx_da_crc(mac_addr));
-#else /* CRC32_OS_SUPPORT */
-                       E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
-                                       E1000_CRC32(ETH_ADDR_LEN, mac_addr));
-#endif /* CRC32_OS_SUPPORT */
                }
 
                /* Write Rx addresses to the PHY */
@@ -3358,6 +3342,7 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
        switch (hw->mac.type) {
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4329,6 +4314,7 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;